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  document number: 319537-003US intel? system controller hub (intel? sch) datasheet may 2010
2 datasheet l information in this document is prov ided in connection with intel? produc ts. no license, express or implied, by estoppel or otherwise, to any intellectual proper ty rights is granted by this document. except as provided in intel's terms and condit ions of sale for such products, in tel assumes no liability whatsoever, and intel disclaims any express or implied warranty, rela ting to sale and/or use of intel products including liability or warranties relating to fitness for a particul ar purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. unless otherwise agreed in writing by intel, the intel products are not designed nor intended for any application in which the failure of the intel product co uld create a situation where personal injury or death may occur. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions mark ed "reserved" or "undefined". intel reserves these for future definition and shall have no responsibility wh atsoever for conflicts or incompatibilitie s arising from future changes to them. the information here is subject to change without notice. do not finalize a design with this information. the intel? system controller hub (intel? sch) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. curr ent characterized errata are available on request. contact your local intel sales office or your distributor to obta in the latest specifications an d before placing your product o rder. this document contains information on products in the design phase of development. the information here is subject to change without notice. do not finalize a design with this information. intel? high definition audio (intel? hd audio) requires a syst em with an appropriate intel ch ipset and a motherboard with an appropriate codec and the necessary driver s installed. system sound quality will va ry depending on actual implementation, controller, codec, drivers and speakers. fo r more information about intel? high defi nition audio (intel? hd audio), refer to http://www.intel.com/. i 2 c is a two-wire communications bus/protocol de veloped by philips. smbus is a subset of the i 2 c bus/protocol and was developed by intel. implementations of the i 2 c bus/protocol may require licenses from various entities, including philips electronics n.v. and north american ph ilips corporation. intel, intel? graphics media accelerator 500 (intel? gma 500) , intel? high definition audio (intel? hd audio), enhanced intel speedstep? technology, intel? atom tm , and the intel logo are trademarks of intel corporation in the u.s. and other countries. *other names and brands may be cl aimed as the property of others. copyright ? 2008?2010, intel corporation. all rights reserved.
datasheet 3 contents 1introduction ............................................................................................................ 19 1.1 terminology ..................................................................................................... 20 1.2 reference documents ........................................................................................ 22 1.3 overview ......................................................................................................... 23 1.3.1 processor interface................................................................................. 23 1.3.2 system memory controller ...................................................................... 24 1.3.3 usb host .............................................................................................. 24 1.3.4 usb client............................................................................................. 24 1.3.5 pci express* ......................................................................................... 24 1.3.6 lpc interface......................................................................................... 24 1.3.7 parallel ata (pata) ................................................................................ 25 1.3.8 intel? graphics media accelerator 500 (intel? gma 500) ........................... 25 1.3.9 display interfaces .................................................................................. 25 1.3.10 secure digital i/o (sdio)/multimedia card (mmc) controller ....................... 26 1.3.11 smbus host controller ............................................................................ 26 1.3.12 intel? high definition audio (intel? hd audio) controller ........................... 26 1.3.13 general purpose i/o (gpio)..................................................................... 26 1.3.14 power management ................................................................................ 26 2 signal description ................................................................................................... 27 2.1 host interface signals........................................................................................ 29 2.2 system memory signals ..................................................................................... 32 2.3 integrated display interfaces .............................................................................. 34 2.3.1 lvds signals ......................................................................................... 34 2.3.2 serial digital video output (sdvo) signals ................................................ 34 2.3.3 display data channel (ddc) and gmbus support........................................ 35 2.4 universal serial bus (usb) signals....................................................................... 36 2.5 pci express* signals ......................................................................................... 36 2.6 secure digital i/o (sdio)/multimedia card (mmc ) signals ...................................... 37 2.7 parallel ata (pata) signals ................................................................................ 38 2.8 intel hd audio interface..................................................................................... 39 2.9 lpc interface.................................................................................................... 40 2.10 smbus interface................................................................................................ 40 2.11 power management interface.............................................................................. 41 2.12 real time clock interface ................................................................................... 42 2.13 jtag interface .................................................................................................. 43 2.14 miscellaneous signals and clocks......................................................................... 43 2.15 general purpose i/o .......................................................................................... 44 2.16 power and ground signals .................................................................................. 45 2.17 functional straps ..................................... ......................................................... 46 3 pin states ................................................................................................................ 47 3.1 pin reset states................................................................................................ 47 3.2 integrated termination resistors.................. ....................................................... 53 4system clock domains ............................................................................................. 55 5 register and memory mapping ................................................................................. 57 5.1 intel? sch register introduction ........................................................................ 58 5.2 pci configuration map ....................................................................................... 59
4 datasheet 5.3 system memory map..........................................................................................60 5.3.1 legacy video area (a0000h ? bffffh).......................................................62 5.3.2 expansion area (c0000h ? d ffffh) .............. .......... ........... ........ ......... ......62 5.3.3 extended system bios area (e0000h ? e ffffh) .............. .......... ........... ......62 5.3.4 system bios area (f0000h ? fffffh) ......... ............ ........... ........ ......... ......62 5.3.5 ehci controller area ...............................................................................62 5.3.6 programmable attribute map (pam)...........................................................62 5.3.7 top of memory segment (tseg) ...............................................................63 5.3.8 apic configuration space (fec00000h ? fe cfffffh)........ .......... ........... ......63 5.3.9 high bios area ......................................................................................63 5.3.10 boot block update ..................................................................................63 5.3.11 memory shadowing.................................................................................64 5.3.12 locked transactions................................................................................64 5.4 i/o address space .............................................................................................65 5.4.1 fixed i/o decode ranges.........................................................................65 5.4.2 variable i/o decode ranges .....................................................................66 5.5 i/o mapped registers.........................................................................................67 5.5.1 nsc?nmi status and control register ......................................................67 5.5.2 nmie?nmi enable register......................................................................67 5.5.3 config_address?configuration address register ....................................68 5.5.4 rstc?reset control register...................................................................69 5.5.5 config_data?configuration data register ..............................................69 6general chipse t configuration ..................................................................................71 6.1 root complex capability ........... ........... .......... ........... ........... ............ ........... ........71 6.1.1 rctcl?root complex topology capabilities list............ .......... ........... ........72 6.1.2 esd?element self description .................................................................72 6.1.3 hdd?intel? hd audio description ...........................................................73 6.1.4 hdba?intel? hd audio base address.......................................................73 6.2 interrupt pin and routing configuration ........... .....................................................74 6.2.1 interrupt pin configuration.......................................................................74 6.2.2 interrupt route configuration...................................................................77 6.3 general configuration register ............................................................................80 6.3.1 rc?rtc configuration register ................................................................80 7 host bridge (d0:f0) .................................................................................................81 7.1 functional description ........................................................................................81 7.1.1 dynamic bus inversion ............................................................................81 7.1.2 fsb interrupt overview ...........................................................................81 7.1.3 cpu bist strap ......................................................................................82 7.2 host pci configuration registers..........................................................................82 7.2.1 vid?identification register .....................................................................82 7.2.2 did?identification register .....................................................................83 7.2.3 pcicmd?pci command register ..............................................................83 7.2.4 pcists?pci status register ....................................................................83 7.2.5 rid?revision identification register ......... ................................................83 7.2.6 cc?class code register..........................................................................84 7.2.7 ss?subsystem identifiers register...........................................................84 7.2.8 miscellaneous (port 05h)..........................................................................88 8 memory controller (d0:f0) ......................................................................................89 8.1 functional overview ...........................................................................................89 8.1.1 dram frequencies and data rates ............................................................89 8.1.2 dram command scheduling ....................................................................89 8.1.3 page management ..................................................................................89
datasheet 5 8.2 dram technologies and organization............... .................................................... 90 8.2.1 dram address mapping........................................................................... 90 8.3 dram clock generation...................................................................................... 92 8.4 ddr2 on-die termination .................................................................................. 92 8.5 dram power management .................................................................................. 92 8.5.1 cke powerdown ..................................................................................... 92 8.5.2 interface high-impedance ....................................................................... 92 8.5.3 refresh ................................................................................................. 93 8.5.4 self-refresh .......................................................................................... 93 8.5.5 dynamic self-refresh ............................................................................. 93 8.5.6 ddr2 voltage ........................................................................................ 93 9 graphics, video, and display (d2:f0) ...................................................................... 95 9.1 graphics overview ............................................................................................ 95 9.1.1 3-d core key features ............................................................................ 95 9.1.2 shading engine key features ................................................................... 95 9.1.3 vertex processing................................................................................... 96 9.1.4 pixel processing ..................................................................................... 97 9.1.5 unified shader ....................................................................................... 97 9.1.6 multi level cache ................................................................................... 98 9.2 video decode overview...................................................................................... 98 9.2.1 entropy coding ...................................................................................... 99 9.2.2 motion compensation ............................................................................. 99 9.2.3 deblocking .......................................................................................... 100 9.2.4 output reference frame storage format ................................................. 100 9.3 display overview ............................................................................................ 101 9.3.1 planes ................................................................................................ 101 9.3.2 display pipes ....................................................................................... 102 9.3.3 display ports ....................................................................................... 102 9.4 configuration registers .................................................................................... 104 9.4.1 vid?vendor identification register ........................................................ 105 9.4.2 did?device identification register......................................................... 105 9.4.3 pcicmd?pci command register ........................................................... 105 9.4.4 pcists?pci status register.................................................................. 106 9.4.5 rid?revision identification................................................................... 106 9.4.6 cc?class codes register ...................................................................... 106 9.4.7 headtyp?header type register ............................................................ 107 9.4.8 mem_base?memory mapped base address register ................................ 107 9.4.9 io_base?i/o base address register...................................................... 107 9.4.10 gmem_base?graphics memory base address register ............................. 108 9.4.11 gtt_base?graphics translation table ba se address register ................... 108 9.4.12 ss?subsystem identifiers..................................................................... 109 9.4.13 cap_ptr?capabilities pointe r register ...... ................ ............ ........... ...... 109 9.4.14 int_ln?interrupt line register ............................................................. 109 9.4.15 int_pn?interrupt pin register .............................................................. 109 9.4.16 gc?graphics control register ............................................................... 110 9.4.17 ssrw?software scratch read/write register.......................................... 110 9.4.18 bsm?base of stolen memory register .................................................... 111 9.4.19 msac?multi size aperture control ......... ................................................ 111 9.4.20 msi_capid?msi capability register....................................................... 112 9.4.21 nxt_ptr3?next item pointer #3 register .............................................. 112 9.4.22 msi_ctl?message control register ....................................................... 112 9.4.23 msi_adr?message address register ..................................................... 113 9.4.24 msi_data?message data register ........................................................ 113 9.4.25 vend_capid?vendor capability register.... .......... ........... ........... ............ 113
6 datasheet 9.4.26 nxt_ptr2?next item pointer #2 register............................................... 113 9.4.27 fd?function disable register ................ ................................................ 114 9.4.28 pm_capid?power management capabilities id register ............................ 114 9.4.29 nxt_ptr1?next item pointer #1 register............................................... 114 9.4.30 pm_cap?power management capabilities re gister........... .......... ........... .... 115 9.4.31 pm_ctl_sts?power management control/ status register ........................ 115 9.4.32 swscismi?software sci/smi register ................................................... 116 9.4.33 asle?system display event register...................................................... 116 9.4.34 gcr?graphics clock ratio register .......... .............................................. 117 9.4.35 lbb?legacy backlight brightness register............................................... 117 9.4.36 asls?asl storage register .................................................................. 118 10 intel? hd audio (d27:f0) ...................................................................................... 119 10.1 functional overview ......................................................................................... 119 10.1.1 docking............................................................................................... 119 10.1.2 low voltage (lv) mode .......................................................................... 121 10.2 pci configuration register space ....................................................................... 122 10.2.1 vid?vendor identification register......................................................... 124 10.2.2 did?device identification register ........... .............................................. 124 10.2.3 pcicmd?pci command register ............................................................ 124 10.2.4 pcists?pci status register .................................................................. 125 10.2.5 rid?revision identification register ......... .............................................. 125 10.2.6 cc?class code register........................................................................ 125 10.2.7 cls?cache line size register................................................................ 126 10.2.8 lt?latency timer register .................................................................... 126 10.2.9 headtyp?header type register ............................................................ 126 10.2.10lbar?lower base address register........................................................ 127 10.2.11ubar?upper base address register ....................................................... 127 10.2.12ss?sub system identifiers register ....................................................... 127 10.2.13cap_ptr?capabilities pointer register ...... ............ ........... .......... ............. 128 10.2.14intln?interrupt line register ............................................................... 128 10.2.15intpn?interrupt pin register ................................................................ 128 10.2.16hdctl?hd control register .................................................................. 128 10.2.17dckctl?docking control register.......................................................... 129 10.2.18dcksts?docking status register .......................................................... 129 10.2.19pm_capid?pci power management capab ility id register...... ......... .......... 130 10.2.20pm_cap?power management capabilities re gister........... .......... ........... .... 130 10.2.21pm_ctl_sts?power management control and status register................... 131 10.2.22msi_capid?msi capability id register....... ............ ........... ........ ............. 131 10.2.23msi_ctl?msi message control register ................................................. 132 10.2.24msi_adr?msi message address register................................................ 132 10.2.25msi_data?msi message data register .................................................. 132 10.2.26pcie_capid?pci express ca pability id register............ .......... ........... ...... 133 10.2.27pciecap?pci express capab ilities register........ ........... .......... ........... ...... 133 10.2.28devcap?device capabilities register.............. ........... ............ ........... ...... 133 10.2.29devc?device control register ............................................................... 134 10.2.30devs?device status register ................................................................ 134 10.2.31fd?function disable register ................ ................................................ 135 10.2.32vccap?virtual channel en hanced capability header regi ster........... .......... 135 10.2.33pvccap1?port vc capability register 1 ..... ........................ ........ ............. 135 10.2.34pvcc2?port vc capability register 2 ...................................................... 136 10.2.35pcctl?port vc control ......................................................................... 136 10.2.36pvcsts?port vc status ........................................................................ 136 10.2.37vc0cap?vc0 resource capability register .............................................. 136 10.2.38vc0ctl?vc0 resource control register .................................................. 137
datasheet 7 10.2.39vcsts?vc0 resource status register .................................................... 137 10.2.40vc0cap?vc0 resource capability register.......... ........... .......... ........... .... 137 10.2.41vc1ctl?vc1 resource control register ................................................. 138 10.2.42vc1sts?vc1 resource status register .................................................. 138 10.2.43rccap?root complex link declaration enhanced capability header register...... .......... ........... ........... ............ ......... .......... 139 10.2.44esd?element self description register................................................... 139 10.2.45l1desc?link 1 description register....................................................... 140 10.2.46l1add?link 1 address register............................................................. 140 10.3 memory mapped configuration registers ............................................................ 141 10.3.1 gcap?global capabilities re gister ........... ............ ........... ........... ............ 144 10.3.2 vmin?minor version register ................................................................ 144 10.3.3 vmaj?major version register ................................................................ 144 10.3.4 outpay?output payload capability register ................ .......... ........... ...... 145 10.3.5 inpay?input payload capability register .... .......... ........... ........... ............ 145 10.3.6 gctl?global control register ............................................................... 146 10.3.7 statests - state change status ........................................................... 147 10.3.8 gsts?global status register ................................................................ 149 10.3.9 ecap?extended capabilities... .......... ........... ........... ............ ......... .......... 150 10.3.10strmpay?stream payload capability ......... .......... ........... ........... ............ 150 10.3.11intctl?interrupt control register........... .............................................. 151 10.3.12intsts?interrupt status register.......... ................................................ 152 10.3.13walclk?wall clock counter register..................................................... 153 10.3.14ssync?stream synchronization register.... ............................................ 153 10.3.15corbbase?corb base address register................................................ 153 10.3.16corbwp?corb write pointer register ................................................... 154 10.3.17corbrp?corb read pointer register .................................................... 154 10.3.18corbctl?corb control register .......................................................... 155 10.3.19corbst?corb status register ............................................................. 155 10.3.20corbsize?corb size register ............................................................. 155 10.3.21rirbbase?rirb base address register...... ............................................ 156 10.3.22rirbwp?rirb write pointer register ..................................................... 156 10.3.23rintcnt?response interrupt count register .......................................... 157 10.3.24rirbctl?rirb control register ............................................................ 157 10.3.25rirbsts?rirb status register ............................................................. 158 10.3.26rirbsize?rirb size register ................. .............................................. 158 10.3.27ic?immediate command register ......................................................... 159 10.3.28ir?immediate response register .......................................................... 159 10.3.29irs?immediate command status register.. ............................................ 160 10.3.30dpbase?dma position base address register.......................................... 160 10.3.31sdctl?stream descriptor control register ............................................. 161 10.3.32sdsts?stream descriptor status register.............................................. 163 10.3.33sdlpib?stream descriptor link position in buffer register........................ 164 10.3.34sdcbl?stream descriptor cyclic buffer length register ........................... 164 10.3.35sdlvi?stream descriptor last valid index register ................................. 165 10.3.36sdfifow?stream descriptor fifo watermark register ............................ 165 10.3.37sdfifos?stream descriptor fifo size regi ster....................................... 166 10.3.38sdfmt?stream descriptor format register............................................. 167 10.3.39sdbdpl?stream descriptor buffer descriptor pointer list base register ..... 168 10.4 vendor specific memory mapped registers ......................................................... 169 10.4.1 em1?extended mode 1 register............................................................. 169 10.4.2 inrc?input stream repeat count register ............................................. 170 10.4.3 outrc?output stream repeat count register ........................................ 170 10.4.4 fifotrk ? fifo tracking register .......... ................................................ 171 10.4.5 sdpib?stream dma position in buffer regi ster........................................ 171
8 datasheet 10.4.6 em2?extended mode 2 register ............................................................. 172 10.4.7 wlclka?wall clock counter alias register.............................................. 172 10.4.8 slpib?stream link position in buffer register ......................................... 172 11 pci express* (d28:f0, f1) ..................................................................................... 173 11.1 functional description ...................................................................................... 173 11.1.1 interrupt generation ............................................................................. 173 11.1.2 power management............................................................................... 173 11.1.3 hot-plug .............................................................................................. 174 11.1.4 additional clarifications ......................................................................... 175 11.2 pci express* configuration registers ................................................................. 175 11.2.1 vid?vendor identification register......................................................... 177 11.2.2 did?device identification register ........... .............................................. 177 11.2.3 pcicmd?pci command register ............................................................ 178 11.2.4 pcists?pci status register .................................................................. 179 11.2.5 rid?revision identification register ......... .............................................. 179 11.2.6 cc?class codes register ...................................................................... 180 11.2.7 cls?cache line size register................................................................ 180 11.2.8 plt?primary latency timer register....................................................... 180 11.2.9 headtyp?header type register ............................................................ 181 11.2.10bnum?bus number register ................................................................. 181 11.2.11slt?secondary latency timer ............................................................... 181 11.2.12iobl?i/o base and limit register .......................................................... 182 11.2.13ssts?secondary status register ........................................................... 182 11.2.14mbl?memory base and limit register .................................................... 183 11.2.15pmbl?prefetchable memory base and limit register ................................. 183 11.2.16cap_ptr?capabilities pointer register ...... ............ ........... .......... ............. 184 11.2.17int_ln?interrupt line register ............................................................. 184 11.2.18int_pn?interrupt pin register............... ................................................ 184 11.2.19bctrl?bridge control register .............................................................. 185 11.2.20pcie_capid?pci express ca pability id register............ .......... ........... ...... 186 11.2.21nxt_ptr1?next item pointer #1 register............................................... 186 11.2.22pciecap?pci express capab ilities register........ ........... .......... ........... ...... 186 11.2.23dcap?device capabilities re gister ........... ............ ........... .......... ............. 187 11.2.24dctl?device control register ............................................................... 188 11.2.25dsts?device status register ................................................................ 189 11.2.26lcap?link capabilities regist er ............. .......... ........... .......... ........... ...... 190 11.2.27lctl?link control register ................................................................... 191 11.2.28lsts?link status register .................................................................... 192 11.2.29slcap?slot capabilities regi ster.................. .......... ........... ........ ............. 193 11.2.30slctl?slot control register .................................................................. 194 11.2.31slsts?slot status register................................................................... 195 11.2.32rctl?root control register .................................................................. 196 11.2.33rcap?root capabilities........ ............ ........... .......... ........... ........ ............. 197 11.2.34rsts?root status register ................... ................................................ 197 11.2.35rcap?root capabilities regist er .................... ........... ............ ........... ...... 198 11.2.36sv_capid?subsystem vendor capability id register............. ......... .......... 198 11.2.37nxt_ptr3?next item pointer #3 register............................................... 198 11.2.38svid?subsystem vendor identification regi ster....................................... 198 11.2.39pci?power management capability id regi ster ........ ........... ........ ............. 199 11.2.40nxt_ptr4?next item pointer #4 register............................................... 199 11.2.41pm_cap?power management capabilities re gister........... .......... ........... .... 199 11.2.42pm_cntl_sts?power management control and status register................. 200 11.2.43mpc?miscellaneous port configuration register ........................................ 201 11.2.44smscs?smi/sci status register ........................................................... 202
datasheet 9 11.2.45fd?function disable register ................ ................................................ 202 12 uhci host controlle r (d29:f0, f1, f2) ................................................................... 203 12.1 functional description...................................................................................... 203 12.1.1 bus protocol ........................................................................................ 203 12.1.2 usb interrupts..................................................................................... 203 12.1.3 usb power management ....................................................................... 203 12.2 pci configuration registers .............................................................................. 205 12.2.1 vid?vendor identification register ........................................................ 206 12.2.2 did?device identification register......................................................... 206 12.2.3 pcicmd?pci command register ........................................................... 206 12.2.4 pcists?pci status register.................................................................. 207 12.2.5 rid?revision identification register ........ .............................................. 207 12.2.6 cc?class code register ....................................................................... 207 12.2.7 mlt?master latency timer register ....................................................... 208 12.2.8 headtyp?header type register ............................................................ 208 12.2.9 base?base address register ................................................................ 208 12.2.10ssid?subsystem identifiers register ..................................................... 208 12.2.11sid?subsystem identification register ................................................... 209 12.2.12cap_ptr?capabilities pointe r register ...... ................ ............ ........... ...... 209 12.2.13int_ln?interrupt line register ............................................................. 209 12.2.14int_pn?interrupt pin register .............................................................. 210 12.2.15usb_relnum?serial bus release number register.................................. 210 12.2.16usb_res?usb resume enable register ................................................. 210 12.2.17fd?function disable register ................ ................................................ 211 12.3 i/o registers .................................................................................................. 211 12.3.1 usbcmd?usb command register ......................................................... 212 12.3.2 usbsts?usb status register ............................................................... 215 12.3.3 usbintr?usb interrupt enable register ................................................ 216 12.3.4 frnum?frame number register............................................................ 217 12.3.5 frbaseadd?frame list base address register ....................................... 217 12.3.6 sofmod?start of frame modify register ................................................ 218 12.3.7 portsc[0,1]?port status and control regi sters ...................................... 219 13 ehci host controller (d29:f7) ............................................................................... 223 13.1 functional description...................................................................................... 223 13.1.1 ehci initialization ................................................................................ 223 13.1.2 usb 2.0 interrupts and error conditions .................................................. 224 13.1.3 usb 2.0 power management .................................................................. 225 13.1.4 interaction with uhci host controllers .... ................................................ 226 13.1.5 usb 2.0 based debug port .................................................................... 229 13.2 usb ehci configuration registers ..................................................................... 230 13.2.1 vid?vendor identification register ........................................................ 231 13.2.2 did?device identification register......................................................... 231 13.2.3 pcicmd?pci command register ........................................................... 231 13.2.4 pcists?pci status register.................................................................. 232 13.2.5 rid?revision identification register ........ .............................................. 232 13.2.6 cc?class codes register ...................................................................... 232 13.2.7 mlt?master latency timer register ....................................................... 233 13.2.8 headtyp?header type register ............................................................ 233 13.2.9 mem_base?base address register ........................................................ 233 13.2.10svid?usb ehci subsystem vendor id register ...................................... 234 13.2.11sid?usb ehci subsystem id register ................................................... 234 13.2.12cap_ptr?capabilities pointe r register ...... ................ ............ ........... ...... 234 13.2.13int_ln?interrupt line register ............................................................. 235 13.2.14int_pn?interrupt pin register .............................................................. 235
10 datasheet 13.2.15pm_capid?pci power management capab ility id register...... ......... .......... 235 13.2.16nxt_ptr1?next item pointer #1 register............................................... 236 13.2.17pm_cap?power management capabilities re gister........... .......... ........... .... 236 13.2.18pwr_cntl_sts?power management contro l/status register .................... 237 13.2.19debug_capid?debug port capability id re gister ........... .......... ........... .... 238 13.2.20nxt_ptr2?next item pointer #2 register............................................... 238 13.2.21debug_base?debug port base offset register ....................................... 238 13.2.22usb_relnum?usb release number register .......................................... 238 13.2.23fl_adj?frame length adjustment register............................................. 239 13.2.24pwake_cap?port wake capability register ............................................. 240 13.2.25cuo?classic usb override register........................................................ 240 13.2.26leg_ext_cap?usb ehci legacy support extended ca pability regist er....... 241 13.2.27leg_ext_cs?usb ehci legacy support extended control/status register.. 241 13.2.28special_smi?intel special usb 2.0 smi register .................................... 244 13.2.29access_cntl?access control register .................................................. 245 13.2.30fd?function disable register ................ ................................................ 246 13.3 memory-mapped i/o registers .......................................................................... 246 13.3.1 host controller capability registers........... ............ ........... .......... ............. 246 13.3.2 host controller operational registers ...................................................... 250 13.3.3 usb 2.0 based debug port register......................................................... 263 14 usb client controller (d26:f0) ............................................................................... 269 14.1 functional description ...................................................................................... 269 14.2 operation ....................................................................................................... 270 14.2.1 usb features ....................................................................................... 271 14.2.2 dma features....................................................................................... 272 14.2.3 reset .................................................................................................. 272 14.2.4 pci device reset .................................................................................. 272 14.2.5 wake of client...................................................................................... 272 14.2.6 wake of host (usb resume) .................................................................. 272 14.3 pci configuration registers............................................................................... 273 14.3.1 vid?vendor identification register......................................................... 273 14.3.2 did?device identification register ........... .............................................. 274 14.3.3 pcicmd?pci command register ............................................................ 274 14.3.4 pcists?pci status register .................................................................. 275 14.3.5 rid?revision identification register ......... .............................................. 275 14.3.6 cc?class codes register ...................................................................... 275 14.3.7 htype - header type register ................................................................ 276 14.3.8 mem_base? usb client memory base address register ............................ 276 14.3.9 sid?subsystem id register .................................................................. 277 14.3.10cap_ptr?capabilities pointer register ...... ............ ........... .......... ............. 277 14.3.11int_ln?interrupt line register ............................................................. 277 14.3.12int_pn?interrupt pin register............... ................................................ 278 14.3.13usbpr?usb port routing register ......................................................... 278 14.3.14pm_capid?pci power management capab ility id register...... ......... .......... 278 14.3.15nxt_ptr?next item pointer register ..................................................... 279 14.3.16pm_cap?power management capabilities re gister........... .......... ........... .... 279 14.3.17pm_cntl_sts?power management control/status register ...................... 280 14.3.18ure?usb resume enable ..................................................................... 281 14.3.19fd?function disable register ................ ................................................ 281 14.4 memory-mapped i/o registers .......................................................................... 282 14.4.1 gcap?global capabilities regi ster.................. ........... ............ ........... ...... 284 14.4.2 dev_sts?device status register........................................................... 285 14.4.3 frame?frame number register............................................................. 285 14.4.4 int_sts?interrupt status register ........................................................ 286
datasheet 11 14.4.5 int_ctrl?interrupt control register ..................................................... 287 14.4.6 dev_ctrl?device control register........................................................ 288 14.5 device endpoint register map ........................................................................... 290 14.5.1 epnib?endpoint [0..3] input base address register ................................. 290 14.5.2 epnil?endpoint [0,1] input length register............................................ 290 14.5.3 epnipb?endpoint [0..3] input position in buffer register .......................... 291 14.5.4 epnidl?endpoint [0..3] input descriptor in list register .......................... 291 14.5.5 epnitq?endpoint [0..3] input transfer in queue register ......................... 291 14.5.6 epnimps?endpoint [0..3] input maximum packet size register.................. 292 14.5.7 epnis?endpoint [0..3] input status register........................................... 292 14.5.8 epnic?endpoint [0..3] input configuration register ................................. 293 14.5.9 epnob?endpoint [0..3] output base address register .............................. 294 14.5.10epnol?endpoint [0..3] output length register ....................................... 295 14.5.11epnopb?endpoint [0..3] output position in buffer register ....................... 295 14.5.12epnodl?endpoint [0..3] output descriptor in list register ....................... 295 14.5.13epnotq?endpoint [0..3] output transfer in queue register...................... 296 14.5.14epnomps?endpoint [0..3] output maxi mum packet size register .............. 296 14.5.15epnos?endpoint [0..3] output status re gister........................................ 297 14.5.16epnoc?endpoint [0..3] output configuration register .............................. 297 14.5.17epnosps?endpoint [0..3] output setu p package status register ............... 299 14.5.18epnosp?endpoint [0..3] output setup packet register............................. 299 15 sdio/mmc (d30:f0, f1, f2) .................................................................................. 301 15.1 sdio functional description (d30:f0, f1, f2) ... .................................................. 301 15.1.1 protocol overview ................................................................................ 301 15.1.2 integrated pull-up resistors .................................................................. 302 15.2 pci configuration registers .............................................................................. 303 15.2.1 vid?vendor identification register ........................................................ 303 15.2.2 did?device identification register......................................................... 304 15.2.3 pcicmd?pci command register ........................................................... 304 15.2.4 pcists?pci status register.................................................................. 305 15.2.5 cc?class codes register ...................................................................... 305 15.2.6 headtyp?header type register ............................................................ 306 15.2.7 mem_base?base address register ........................................................ 306 15.2.8 ss?subsystem identifier register.......................................................... 306 15.2.9 int_ln?interrupt line register ............................................................. 307 15.2.10int_pn?interrupt pin register .............................................................. 307 15.2.11slotinf?slot information register.......... .............................................. 307 15.2.12bc?buffer control register ................................................................... 308 15.2.13sdioid?sdio identification register ..................................................... 309 15.2.14capcntl?sdio capability control register.. ................ .......... ........... ...... 309 15.2.15manid?manufacturer id ...................................................................... 310 15.2.16fd?function disable register ................ ................................................ 310 15.3 sdio/mmc memory-mapped registers ............................................................... 311 15.3.1 dmaadr?dma address register ............................................................ 312 15.3.2 blksz?block size register ................................................................... 313 15.3.3 blkcnt?block count register ............................................................... 314 15.3.4 cmdarg?command argument register ................................................. 314 15.3.5 xfrmode?transfer mode register ......................................................... 315 15.3.6 xfrmode?transfer mode register ......................................................... 316 15.3.7 cmd?command register ...................................................................... 317 15.3.8 resp?response register ...................................................................... 318 15.3.9 bufdata?buffer data register ............................................................. 318 15.3.10pstate?present state register ............................................................. 318 15.3.11hostctl?host control register ............................................................ 321
12 datasheet 15.3.12pwrctl?power control register ............................................................ 321 15.3.13blkgapctl?block gap control register ...... ............................................ 322 15.3.14wakectl?wake control register........................................................... 323 15.3.15clkctl?clock control register .............................................................. 324 15.3.16toctl?timeout control register............................................................ 325 15.3.17swrst?software reset register............................................................ 326 15.3.18nintsts?normal interrupt status register ............................................. 327 15.3.19erintsts?error interrupt status register .............................................. 329 15.3.20ninten?normal interrupt enable register .............................................. 330 15.3.21erinten?error interrupt enable register ................................................ 331 15.3.22nintsigen?normal interrupt signal enable register................................ 332 15.3.23erintsigen?error interrupt signal enable register ................................. 333 15.3.24ac12errsts?automatic cmd12 error status register .............................. 334 15.3.25cap?capabilities register .... ............ ........... .......... ........... ........ ............. 334 15.3.26mccap?maximum current capabilities regist er .............. .......... ........... .... 336 15.3.27sltintsts?slot interrupt status register.. ............................................. 336 15.3.28hcver?host controller version register ................................................. 336 16 parallel ata (d31:f1) ............................................................................................ 339 16.1 functional overview ......................................................................................... 339 16.1.1 programmed i/o transfers..................................................................... 339 16.1.2 multi-word dma transfers ..................................................................... 342 16.1.3 synchronous (ultra) dma transfers......................................................... 344 16.2 pci configuration registers............................................................................... 345 16.2.1 id?identifiers register ......................................................................... 346 16.2.2 pcicmd?command register.................................................................. 346 16.2.3 pcists?device status register ............................................................. 346 16.2.4 rid?revision id register...................................................................... 347 16.2.5 cc?class code register........................................................................ 347 16.2.6 cls?cache line size register................................................................ 347 16.2.7 mlt?master latency timer register ....................................................... 347 16.2.8 bmbar?bus master base address register .............................................. 348 16.2.9 ss?sub system identifiers register ....................................................... 348 16.2.10intr?interrupt information register ........ .............................................. 348 16.2.11mc?miscellaneous configuration register ................................................ 349 16.2.12d0tim/d1tim?device 0/1 timing register .............................................. 349 16.3 i/o registers .................................................................................................. 351 16.3.1 pcmd?primary command register ......................................................... 351 16.3.2 psts?primary status register ............................................................... 352 16.3.3 pdtp?primary descriptor table pointer register....................................... 352 17 lpc interface (d31:f0) .......................................................................................... 353 17.1 functional overview ......................................................................................... 353 17.1.1 memory cycle notes ............................................................................. 353 17.1.2 tpm 1.2 support................................................................................... 353 17.1.3 fwh cycle notes .................................................................................. 353 17.1.4 lpc output clocks ................................................................................ 354 17.2 pci configuration registers............................................................................... 354 17.2.1 vid?vendor identification register......................................................... 355 17.2.2 did?device identification register ........... .............................................. 355 17.2.3 pcicmd?pci command register ........................................................... 355 17.2.4 pcists?pci status register .................................................................. 355 17.2.5 rid?revision identification register ......... .............................................. 356 17.2.6 cc?class codes register ...................................................................... 356 17.2.7 headtyp?header type register ............................................................ 356 17.2.8 ss?sub system identifiers register ....................................................... 357
datasheet 13 17.3 acpi device configuration ................................................................................ 357 17.3.1 smbase?smbus base address register .................................................. 357 17.3.2 gpiobase?gpio base address register ................................................. 358 17.3.3 pm1base?pm1_blk base address register ............................................. 358 17.3.4 gpe0base?gpe0_blk base address register.......................................... 359 17.3.5 lpcs?lpc clock control register ........................................................... 359 17.3.6 acpi_ctl?acpi control register ........................................................... 360 17.3.7 mc - miscellaneous control register........................................................ 360 17.4 interrupt control ............................................................................................. 361 17.4.1 pirq[n]_rout?pirq[a,b,c,d] routing cont rol register ........................... 361 17.4.2 sirq_ctl?serial irq control register ...... ............................................. 361 17.5 fwh configuration registers............................................................................. 362 17.5.1 fwh_idsel?fwh id select register...................................................... 362 17.5.2 bde?bios decode enable .................................................................... 363 17.5.3 bios_ctl?bios control register .......................................................... 364 17.6 root complex register block configuration ......................................................... 364 17.6.1 rcba?root complex base address register ............................................ 364 18 acpi functions ..................................................................................................... 365 18.1 8254 timer .................................................................................................... 365 18.1.1 overview ............................................................................................ 365 18.1.2 timer programming .............................................................................. 366 18.1.3 reading from the interval timer ............................................................ 367 18.1.4 i/o registers ....................................................................................... 368 18.2 high precision event timer ............................................................................... 373 18.2.1 functional overview ............................................................................. 373 18.2.2 registers............................................................................................. 374 18.3 8259 interrupt controller ................................................................................. 379 18.3.1 overview ............................................................................................ 379 18.3.2 interrupt handling................................................................................ 380 18.3.3 initialization command words (icw) .......... ............................................ 381 18.3.4 operation command words (ocw) ......................................................... 382 18.3.5 modes of operation .............................................................................. 382 18.3.6 end of interrupt (eoi)........................................................................... 384 18.3.7 masking interrupts ............................................................................... 384 18.3.8 steering of pci interrupts...................................................................... 385 18.3.9 i/o registers ....................................................................................... 385 18.4 advanced peripheral interrupt controller (ioxapic) ............................................. 392 18.4.1 functional overview ............................................................................. 392 18.4.2 unsupported modes .............................................................................. 392 18.4.3 pci express interrupts .......................................................................... 393 18.4.4 routing of internal device interrupts ...................................................... 394 18.4.5 memory registers ................................................................................ 394 18.5 serial interrupt ............................................................................................... 397 18.5.1 overview ............................................................................................ 397 18.5.2 start frame......................................................................................... 397 18.5.3 data frames........................................................................................ 398 18.5.4 stop frame ......................................................................................... 398 18.5.5 unsupported serial interrupts ................................................................ 398 18.5.6 data frame format .............................................................................. 399 18.6 real time clock .............................................................................................. 400 18.6.1 overview ............................................................................................ 400 18.6.2 update cycles...................................................................................... 400 18.6.3 interrupts ........................................................................................... 400 18.6.4 lockable ram ranges ........................................................................... 400
14 datasheet 18.6.5 month and year alarms ......................................................................... 400 18.6.6 i/o registers ....................................................................................... 401 18.6.7 indexed registers ................................................................................. 401 18.7 general purpose i/o......................................................................................... 405 18.7.1 functional description ........................................................................... 405 18.7.2 i/o registers ....................................................................................... 406 18.7.3 resume well gpio i/o registers............................................................. 410 18.8 smbus controller ............................................................................................. 411 18.8.1 overview ............................................................................................. 411 18.8.2 bus arbitration ..................................................................................... 411 18.8.3 bus timings ......................................................................................... 411 18.8.4 smi# .................................................................................................. 412 18.8.5 i/o registers ....................................................................................... 412 19 absolute maximums and operating conditions ....................................................... 417 19.1 absolute maximums ......................................................................................... 417 20 dc characteristics .................................................................................................. 419 20.1 signal groups ................................................................................................. 419 20.2 power and current characteristics................. ..................................................... 421 20.3 general dc characteristics................................................................................ 423 21 ballout and package information ........................................................................... 429 21.1 package diagrams ........................................................................................... 430 21.2 ballout definition and signal locations........... ..................................................... 435
datasheet 15 figures 1 system block diagram example ................................................................................. 19 2 signal information diagram....................................................................................... 28 3 system address ranges............................................................................................ 60 4 intel? sch usb port connections ............................................................................ 227 5 communication protocol layers in the usb client controller ........................................ 270 6 response token formats ........................................................................................ 302 7 package dimensions (top view)............................................................................... 430 8 package dimensions (bottom view).......................................................................... 431 9 package dimensions (side view, unmounted) .......... .................................................. 432 10 package dimensions (solder ball detail ?c?) .............................................................. 433 11 package dimensions (underfill detail ?b?) ................................................................. 433 12 package dimensions (solder resist opening) ............................................................. 434 13 intel? sch ball map (top view, columns 1?17)......................................................... 436 14 intel? sch ball map (top view, columns 18?33) ....................................................... 437 15 intel? sch ball map (top view, columns 34?50) ....................................................... 438
16 datasheet tables 1 pci devices and functions ................................ .........................................................23 2 intel? sch buffer types ...........................................................................................27 3 functional strap definitions .............................. .........................................................46 4 reset state definitions ..............................................................................................47 5 intel? sch reset state.............................................................................................48 6 intel? sch integrated termination resistors ......... ......................................................53 7 intel? sch clock domains ........................................................................................55 8 register access types and definitions .........................................................................57 9 pci devices and functions ................................ .........................................................59 10 intel? sch memory map ...........................................................................................60 11 programmable attribute map......................................................................................62 12 fixed i/o decode ranges ..........................................................................................65 13 variable i/o decode ranges.......................................................................................66 14 root complex configuration registers .........................................................................71 15 interrupt pin field bit decoding ..................................................................................74 16 interrupt pin register map .........................................................................................74 17 interrupt route field bit decoding ..............................................................................77 18 interrupt route register map .....................................................................................77 19 host bridge configuration register address map ..... ......................................................82 20 dram attributes.......................................................................................................90 21 dram address decoder .............................................................................................91 22 hardware-accelerated video codec support .................................................................98 23 pixel format for the luma (y) plane .......................................................................... 100 24 pixel formats for the cr/cb (v/u) plane..................................................................... 100 25 graphics and video pci configuration register address map......................................... 104 26 intel hd audio pci configuration registers ................................................................ 122 27 intel hd audio memory mapped configuration registers .............................................. 141 28 msi vs. pci irq actions .......................................................................................... 173 29 pci express* register address map .......................................................................... 175 30 bits maintained in low power states .................. ....................................................... 204 31 uhci controller pci register address map (d29:f0/f1/f2) .......................................... 205 32 usb i/o registers .................................................................................................. 211 33 run/stop, debug bit interaction swdbg (bit 5), run/stop (bit 0) operation .................. 214 34 uhci vs. ehci ....................................................................................................... 223 35 usb ehci pci register address map ......................................................................... 230 36 ehci capability registers ... ...................... ............ ........... ........... ............ ........... ...... 247 37 enhanced host controller operational register ad dress map......................................... 250 38 debug port register address map ............................................................................. 263 39 usb client controller pci register address map (d26:f0) ............................................ 273 40 usb client i/o registers.......................................................................................... 282 41 determining the response type ............................................................................... 301 42 response register mapping ..................................................................................... 302 43 sdio/mmc pci register address map........................................................................ 303 44 sdio/mmc memory-mapped register address map ..................................................... 311 45 supported pata standards and modes ...................................................................... 339 46 ata command block registers (pata_dcs1#)........................................................... 340 47 ata control block registers (pata_dcs3#)............................................................... 340 48 prd base address .................................................................................................. 342 49 prd descriptor information ..................................................................................... 342 50 interrupt/active bit interaction................................................................................. 343 51 pata register address map ..................................................................................... 345 52 pata memory-mapped i/o register address map ........................................................ 351 53 lpc interface pci register address map .................................................................... 354
datasheet 17 54 counter operating modes........................................................................................ 366 55 i/o register map.................................................................................................... 368 56 legacy timer interrupt mapping............................................................................... 374 57 master 8259 input mapping ..................................................................................... 379 58 slave 8259 input mapping....................................................................................... 379 59 content of interrupt vector byte .............................................................................. 380 60 8259 i/o register mapping...................................................................................... 385 61 interrupt delivery address value.............................................................................. 393 62 interrupt delivery data value .................................................................................. 393 63 apic memory-mapped register locations ............. ..................................................... 394 64 idx register values................................................................................................ 394 65 serial interrupt mode selection ................................................................................ 398 66 data frame format ................................................................................................ 399 67 rtc i/o registers .................................................................................................. 401 68 rtc (standard) ram bank....................................................................................... 401 69 gpio i/o register map ........................................................................................... 406 70 smbus timings ...................................................................................................... 411 71 smbus i/o register map ......................................................................................... 412 72 intel? sch absolute maximum ratings..................................................................... 417 73 intel? sch maximum power consumption ................................................................ 418 74 intel? sch buffer types......................................................................................... 419 75 intel? sch signal group definitions................... ...................................................... 420 76 thermal design power ............................................................................................ 421 77 dc current characteristics ...................................................................................... 421 78 operating condition power supply and reference dc characteristics............................. 423 79 active signal dc characteristics ... ............................................................................ 424 80 pll noise rejection specifications ..................... ....................................................... 427 81 intel? sch pin list arranged by signal name ............................................................ 439
18 datasheet revision history revision number description revision date -001 ? initial release april 2008 -002 ? updated reference documents ? chapter 1.3.2 ? added support of 2gb of memory and of 2048mb devices ? chapter 2.1 ? corrected cmos/agtl+ assignments ? chapter 2.5 ? added that pcie compensation pins also act for lvds and sdvo interfaces ? chapter 2.10 ? clarified that smb_alert# does not wake the system or generate an interrupt ? chapter 2.11 ? clarified that rtcrst# does not clear cmos ? chapter 2.14 ? clarified that the in tel? sch will not de-assert clkreq# ? chapter 3.1 ? corrected reset states for cl kreq# (vox-known), rsmrst# (vli), and lvds (voh) ? chapter 5.3 ? added support of up to 2gb of memory ? chapter 8.2 ? added 2048 mbit device support ? chapter 9.3.2 ? removed assertion that display plls can be disabled ? chapter 9.4.2 ? updated device id register ? chapter 11.1.4 ? added section asserting that no snoop is not supported ? chapter 11.2.15 ? corrected default value ? chapter 12.2.16 ? corrected bit[1:0] definitions ? chapter 15.2.8 ? removed crid description - wrong place ? chapter 15.3.10 ? corrected bit 10 definition ? chapter 17.1 ? clarified that the intel? sch does not support lpc dma ? chapter 17.5.1 ? corrected bit[15:12] definitions ? chapter 18.7.2 ? corrected cgio default value ? chapter 20.2 ? added i vcc33rtc , i vcc5ref and i vcc5refsus and corrected i vccpciebg parameter description march 2009 -003 ? 1.3.2 - added support of x8 memory device width ? 2.17 - updated functional straps conf iguration for 266 mhz gfx in table 3 ? 5.4.1 - changed pata port disable to "no" in table 12 ? 8.2 - add x8-width devices to tables 20 and 21 ? 9.2 - add 1080p @ 24fps to the codecs supporting 1080i in table 22 ? 9.3.2 - corrected bottom of pixel clocks range ? 9.4.34 - changed bits [1:0] for 266 mhz gfx support ? 10.3.7 - removed wakeen register ? 11.2.27 - disclosed bit 8 (clkreq# enabled) with instruction ? 12.1.4 - removed support of usb legacy keyboard ? 12.2.16 - clarified usb_res is in the resume well ? 13.1.5 - removed support of usb legacy keyboard ? 13.3.1.3 - clarified hcsparams is in the suspend well ? 16.2 - corrected offsets for d0tim and d1tim in table 52 ? 18 - corrected chapter title ? 18.6.7.2 - clarified that rtc_regb is in the resume well and reset by rsmrst# ? 18.7.2 - corrected rgio default value in table 70 ? 18.7.3.1 - corrected rgen default value ? 20.1 - moved tdo to cmos open drain in table 76 ? 20.2 - adjusted tdp range to include us15x in table 77 ? 20.2 - added second spec to isus_vccsm, corrected ivcc 33rtc, and added us15x core current in table 78 ? 20.3 - corrected cmos and cmos_od vil(max) and vih(min), and added vil,lvm and vih,lvm to cmos_hda in table 80 may 2010
datasheet 19 introduction 1 introduction the intel? system controller hub (intel? sch) is a component of intel? atom? processor technology. the intel? sch combines functionality normally found in separate gmch (integrated graphics, proces sor interface, memory controller) and ich (on-board and end-user i/o expansion) components into a single component consuming less than 2.3 w of thermal design power. the features of the intel? sch provide functionality necessary for traditio nal operating systems (such as microsoft windows vista* or linux*) as well as functi onality normally associated with handheld devices (such as sdio/mmc and usb client). the intel? sch was designed to be used with the intel? atom? processor z5xx series processor. figure 1 shows an example system block diagram. section 1.3 provides an overview of the major features of the intel? sch. this document is the datasheet for the in tel system controller hub component. the document content includes signal descr iption, system memory map, register descriptions, a description of the intel? sch interfaces and major functional units, electrical characteristics, ballout definitions, and package characteristics. figure 1. system block diagram example processor ddr2 sdram 400/533 mhz external display sdvo intel? sch usb 8 host ports, or 7 hosts + 1 client intel? high definition audio lpc interface system management controller clock generation smbus 1.0 system devices pci express* x1 fwh legacy i/o sdio/mmc internal display lvds integrated graphics and video 2 ports 400/533 mhz p-ata hdd 3 ports gpio
introduction 20 datasheet 1.1 terminology term description acpi advanced control programmable interface. add2 advanced digital display 2. an interface specification that accepts serial dvo inputs and translates them into different display ou tputs such as dvo, tv- out, and lvds. core the internal base logic in the intel? sch. crt cathode ray tube dbi dynamic bus inversion ddr2 a second generation double data rate sdram memory technology. dvi digital video interface. dvi is a specif ication that defines the connector and interface for digital displays. smc system management controller or extern al controller. refers to a separate system management controller that handles reset sequences, sleep state transitions, and other system management tasks. ehci enhanced host controller interface. a co ntroller interface that, on the intel? sch, supports up to eight usb 2.0 high-s peed root ports, two of which are to be used internally only. fsb front side bus. fsb is synonymous with host bus or processor bus. fwh firmware hub cold reset full reset is when pwrok is deasserted and all system rails except v ccrtc are powered down. warm reset warm reset is when both reset# and pwrok are asserted. hdmi high definition multimed ia interface. hdmi supports standard, enhanced, or high-definition video, plus multi-channel digital audio on a single cable. hdmi transmits all atsc hdtv standards and supports 8-channel digital audio, with bandwidth to spare for future requir ements and enhancements (additional details available through: http://www.hdmi.org/ ). host this term is used sy nonymously with processor. intel graphics media adapter internal graphics device. generic na me for a graphics accelerator that performs decoding of digital video signals. intel? gma 500 intel? graphics media acce lerator 500. a hardware accelerator for 2d and 3d graphics. intx an interrupt request si gnal where ?x? stands for interrupts a, b, c, and d. lcd liquid crystal display. lvds low voltage differential signaling. lvds is a high speed, low power data transmission standard used for di splay connections to lcd panels. msi message signaled interrupt. msi is a tr ansaction initiated outside the host, conveying interrupt informat ion to the receiving agent through the same path that normally carries re ad and write commands. pci express* pci express* is a high-speed serial interface. the pci express configuration is software compatible with the existing pci specifications. processor intel? atom? processor z5xx series
datasheet 21 introduction rank a unit of dram corresponding to number of sdram devices in parallel such that a full 64-bit data bus is formed. intel? sch intel? system controller hub: a sing le-chip component that contains the processor interface, ddr2 sdram controller, intel graphics media accelerator 500 (intel? gma 500), various display interfaces, usb, sdio, pci express*, pata, lpc, and othe r i/o capabilities. sci system control interrupt. sci is used in the acpi protocol. sdvo serial digital video out (sdvo). sdvo is a digital display channel that serially transmits digital display data to an ex ternal sdvo device . the sdvo device accepts this serialized form at and then translates the data into the appropriate display format (i.e., tmds, lvds, tv-out). sdvo device third-party codec that use sdvo as an input may have a variety of output formats, including dvi, lvds, hdmi, tv-out, etc. serr system error. serr is an indication that an unre coverable error has occurred on an i/o bus. smi system management interrupt. smi is used to indicate any of several system conditions (such as thermal sensor events, throttling activated, access to system management ram, chassis open, or other system state-related activity). tmds transition minimized differential signaling. tmds is a signaling interface from silicon image that is used in dvi and hdmi. tmds is based on low-voltage differential signaling and co nverts an 8-bit signal into a 10-bit transition- minimized and dc-balanced si gnal (equal number of 0? s and 1?s) in order to reduce emi generation and improve reliability. tolm top of low memory. the highest addr ess below 4 gb where a processor- initiated memory read or write transactio n will create a corresponding cycle to dram on the memory interface. uhci universal host controller interface. a controller interface that supports two usb 1.1 ports. the in tel? sch contains th ree uhci controllers. uma unified memory architectu re. uma describes an inte l graphics media adapter using system memory for its frame buffers. vco voltage controlled oscillator term description
introduction 22 datasheet 1.2 reference documents document location intel ? atom? processor z5 xx series datasheet http://www.intel.com/products/atom/ techdocs.htm intel ? system controller hub (intel ? sch) specification update http://www.intel.com/products/atom/ techdocs.htm pci express base specification, revision 1.0a http://www.pcisig.com/specifications/ pciexpress/ mobile graphics low-powe r addendum to the pci express ? base specification revision 1.0 http://www.pcisig.com/specifications/ pciexpress/ low pin count interface specification, revision 1.1 (lpc) http://developer.intel.com/design/ chipsets/industry/lpc.htm system management bus specification, version 1.0 (smbus) http://www.smbus.org/specs/ pci local bus specification, revision 2.3 (pci) http://www.pcisig.com/specifications pci power management specification, revision 1.1 http://www.pcisig.com/specifications advanced configuration an d power interface, version 3.0 (acpi) http://www.acpi.info/spec.htm enhanced host controller interface specification for universal serial bus, revision 1.0 (ehci) http://developer.intel.com/ technology/usb/ehcispec.htm universal serial bus specification (usb), revision 2.0 http://www.usb.org/developers/docs at attachment - 6 with pack et interface (ata/atapi - 6) http://t13.org ia-pc hpet (high precision event timers) specification, revision 1.0 http://www.intel.com/ hardwaredesign/hpetspec_1.pdf
datasheet 23 introduction 1.3 overview the intel? sch is designed for use with intel atom processor z5xx series-based platforms. the intel? sch connects to the processor as shown in figure 1 . the intel? sch incorporates a variety of pci functions as listed in ta b l e 1 . note: all devices are on pci bus 0. 1.3.1 processor interface the intel? sch supports the intel atom processor z5xx series subset of the enhanced mode scalable bus protocol, and implements a low-power cmos bus. the intel? sch supports a single bus agent with fsb data rates of 400 mt/s and 533 mt/s. the intel? sch features include: ? intel atom processor z5xx series support ? cmos frontside bus signaling for reduced power ? 400-mt/s or 533-mt/s data rate operation ? 64-byte cache-line size ? 64-bit data bus, 32-bit address bus ? supports one physical processor attachment with up to two logical processors ? 16 deep ioq ? 1 deep defer queue ? fsb interrupt delivery ? power-saving sideband control (dpwr#) for enabling/disabling processor data input sense amplifiers ?1.05-v v tt operation table 1. pci devices and functions device function function description 0 0 host bridge 2 0 integrated graphics and video device 26 0 usb client 27 0 intel? high definition audi o (intel? hd audio) controller 28 0 pci express port 1 1 pci express port 2 29 0 usb classic uhci controller 1 1 usb classic uhci controller 2 2 usb classic uhci controller 3 7 usb2 ehci controller 30 0 sdio/mmc port 0 1 sdio/mmc port 1 2 sdio/mmc port 2 31 0 lpc interface 1pata controller
introduction 24 datasheet 1.3.2 system memory controller the intel? sch integrates a ddr2 memory controller with a single 64-bit wide interface. only ddr2 memory is supported . the memory controller interface is fully configurable through a set of control regist ers. features of the intel? sch memory controller include: ? supports 1.8-v ddr2 sdram, up to 2 ranks ? supports 1.5-v ddr2 sdram, 1 rank only ? supports 400 mt/s and 533 mt/s data rates ? single 64-bit wide channel ? single command per clock (1-n) operation ? support for a maximum of 2gb of dram ? device density support for 512mb, 1024mb, and 2048mb devices ? device widths of x8 and x16 ? aggressive power management to reduce idle power consumption ? page closing policies to proactively close pages after idle periods ? no on-die termination (odt) support ? supports non-terminated and board-terminated bus topologies 1.3.3 usb host the intel? sch contains three universal host controller interface (uhci) usb 1.1 controllers and an enhanced host controller interface (ehci) usb 2.0 controller. port- routing logic on the intel? sch determines which usb controller is used to operate a given usb port. a total of eight usb ports are supported. all eight of these ports are capable of high- speed data transfers up to 480 mb/s, and six of the ports are also capable of full-speed and low-speed signaling. the two high-s peed-only usb ports may only be used internally within the system platform. 1.3.4 usb client the intel? sch supports usb client functiona lity on port 2 of the usb interface. this permits the platform to attach to a separate usb host as a peripheral mass storage volume or rndis device. 1.3.5 pci express* the intel? sch has two pci express root ports supporting the pci express base specification, revision 1.0a . pci express root ports 1?2 can be statically configured as two x1 lanes. each root port supports 2.5 gb/s bandwidth in each direction. an external graphics device can be used with one of the x1 pci express lanes/ports. 1.3.6 lpc interface the intel? sch implements an lpc interface as described in the lpc 1.1 specification . the lpc bridge function of the intel? sch resides in pci device 31:function 0. the lpc interface has three pci-based clock ou tputs that may be provided to different i/o devices, such as firmware hub flash memory or a legacy i/o chip. the lpc_clkout signals run at one-fourth of the h_clkinp/n frequency and support a total of six loads (two loads per clock pair) with no external buffering.
datasheet 25 introduction 1.3.7 parallel ata (pata) the pata host controller supports three types of data transfers: ? programmed i/o (pio): processor is in control of the data transfer. ? multi-word dma (ata-5): dma protocol that resembles the dma on the isa bus. allows transfer rates of up to 66 mb/s. ? ultra dma: synchronous dma protocol that redefines signals on the pata cable to allow both host and target throttling of data and transfer rates up to 100 mb/s. ultra dma 100/66/33 are supported. 1.3.8 intel? graphics media accelerator 500 (intel? gma 500) the intel? sch provides integrated grap hics (2d and 3d) and high-definition video decode capabilities with minimal power consumption. 1.3.8.1 graphics the highly compact intel graphics media adapter contains an advanced shader architecture (model 3.0+) that performs pixel shading and vertex shading within a single hardware accelerator. the processing of pixels is deferred until they are determined to be visible, which minimizes access to memory and improves render performance. 1.3.8.2 video the intel? sch supports full hardware accelera tion of video decode standards, such as h.264, mpeg2, mpeg4, vc1, and wmv9. 1.3.9 display interfaces the intel graphics media adapter includes lvds and serial dvo display ports permitting simultaneous independent operat ion of two displays, depending on intel? sch component. if external graphics is used instead of th e internal graphics device, lvds and sdvo ports will not function. 1.3.9.1 lvds the intel? sch supports a low-voltage differe ntial signaling interface that allows the intel graphics media adapter to communicate dire ctly to an on-board flat-panel display. the lvds interface supports pixel color depths of 18 and 24 bits. 1.3.9.2 serial dvo (sdvo) display the intel? sch has a digital display channe l capable of driving sdvo adapters that provide interfaces to a variety of external display technologies (e.g., dvi, tv-out, analog crt). sdvo lane reversal is not supported.
introduction 26 datasheet 1.3.10 secure digital i/o (s dio)/multimedia card (mmc) controller the intel? sch contains three sdio/mmc ex pansion ports used to communicate with a variety of internal or external sdio and mmc devices. each port supports sdio revision 1.1 and mmc revision 4.1 and is backward-compatible with previous interface specifications. 1.3.11 smbus host controller the intel? sch contains an smbus host interface that allows the processor to communicate with smbus slaves. this interface is compatible with most i 2 c devices. the intel? sch smbus host controller provides a mechanism for the processor to initiate communications with smbus peripherals (slaves). see the system management bus (smbus) specification, version 1.0. 1.3.12 intel? high definition au dio (intel? hd audio) controller the intel ? high definition audio specification defines a digital interface that can be used to attach different types of codecs (such as audio and modem codecs). the intel hd audio controller supports up to fo ur audio streams, two in and two out. with the support of multi-channel audio stre am, 32-bit sample depth, and sample rate up to 192 khz, the intel hd audio controlle r provides audio quality that can deliver consumer electronic (ce) levels of audio ex perience. on the input side, the intel? sch adds support for an array of microphones. the intel hd audio controller uses a set of dma engines to effectively manage the link bandwidth and support simultaneous indepe ndent streams on the link. the capability enables new exciting usage models with inte l hd audio (e.g., listening to music while playing a multi-player game on the internet.) the intel hd audio controller also supports isochronous data transfers allo wing glitch-free audio to the system. 1.3.13 general purpose i/o (gpio) the intel? sch contains a total of 14 gpio pins. ten gpios are powered by the core power rail and are turned off during sleep modes (s3 and higher). the remaining four gpios are powered by the intel? sch susp end well power supply. these gpios remain active during s3. the suspend well gpios can be used to wake the system from the suspend-to-ram state. the gpios are not 5-v tolerant. 1.3.14 power management the intel? sch contains a mechanism to allow flexible configuration of various device maintenance routines as well as power ma nagement functions including enhanced clock control and low-power state transitions (e.g., suspend-to-ram and suspend-to- disk). a hardware-based thermal manageme nt circuit permits software-independent entrance to low-power states. the intel? sch contains full support for the advanced configuration and power interface (acpi) specification , revision 3.0.
datasheet 27 signal description 2 signal description this chapter provides a detailed description of the intel? sch signals and boot strap definitions. the signals are arranged in functional groups according to their associated interface (see figure 2 ). each signal description table has the following headings: ? signal : the name of the signal/pin ? type : the buffer direction and type. buffer dire ction can be either input, output, or i/o (bidirectional). see ta b l e 2 for definitions of the different buffer types. ? power well : the power plane used to supply power to that signal. choices are core, ddr, suspend, and rtc. ? description : a brief explanation of the signal?s function table 2. intel? sch buffer types buffer type buffer description agtl+ assisted gunning transcei ver logic plus. cmos open drain interface signals that require termination. refer to the agtl+ i/o specification for complete details. cmos, cmos_od 1.05-v cmos buffer, or cmos open drain cmos_hda cmos buffers for intel? hd audio interf ace that can be configured for either 1.5-v or 3.3-v operation. cmos1.8 1.8-v cmos buffer. these buffers can be configured as stub series termination logic (sstl1.8) cmos3.3, cmos3.3_od 3.3-v cmos buffer, or cmos 3.3-v open drain cmos3.3-5 3.3-v cmos buffer, 5-v tolerant usb compliant with usb 1.1 and usb 2.0 specifications. pcie pci express interface signals. these si gnals are compatible with pci express 1.0a signaling environment ac specificat ions and are ac coupled. the buffers are not 3.3-v tolerant. sdvo serial-dvo differential buffe rs. these signals are ac coupled. these buffers are not 3.3-v tolerant. lvds low voltage differential signal output bu ffers. these pure ou tputs should drive across a 100- resistor at the receiver when driving. a analog reference or output maybe used as a threshold voltage or for buffer compensation.
signal description 28 datasheet figure 2. signal information diagram type your search here processor front side bus interface h_a[31:3]# h_d[63:0]# h_ads# h_bnr# h_bpri# h_dbsy# h_defer# h_drdy# h_dpwr# h_hit# h_hitm# h_lock# h_req[4:0]# h_trdy# h_rs[2:0]# h_cpurst# h_breq0# h_dinv[3:0]# h_adstb[1:0]# h_dstbp[3:0]#, h_dstbn[3:0]# h_thrmtrip# h_cpuslp# h_pbe# h_init# h_intr h_nmi h_smi# h_stpclk# h_clkinp, h_clkinn h_rcompo h_gvref h_cgvref h_swing h_dpslp# h_cpupwrgd h_cpupwrgd, h_dprstp# intel ? sdvo device interface sdvob_green+, sdvob_green- sdvob_blue+, sdvob_blue- sdvob_red+, sdvob_red- sdvob_clk+, sdvob_clk- sdvob_int+, sdvob_int- sdvo_tvclkin+, sdvo_tvclkin- sdvo_stall+, sdvo_stall- sdvo_ctrlclk, sdvo_ctrldata display (lvds) interface la_datap[3:0], la_datan[3:0] la_clkp la_clkn sm_dq[63:0] sm_dqs[7:0] sm_ma[14:0] sm_bs[2:0] sm_ras# sm_cas# sm_we# sm_rcvenin# sm_rcvenout# sm_ck[1:0] sm_ck[1:0]# sm_cs[1:0]# sm_cke[1:0] sm_rcompo sm_vref system memory interface thrm# reset# pwrok rsmrst# rtcrst# susclk wake# stpcpu# dprslpvr slpmode rstwarn slprdy# rstrdy# gpe# power mangm?t interface smbus interface smb_data smb_clk smb_alert# pcie_petp[2:1], pcie_petn[2:1] pcie_perp[2:1], pcie_pern[2:1] pcie_clkinp, pcie_clkinn pcie_icompo, pcie_icompi pci express* interface usb_dp[7:0]/usb_dn[7:0] usb_oc[7:0]# usb_rbiasp usb_rbiasn usb_clk48 usb interface sd[2..0]_pwr#, sd{1,0}_data[3..0], sd2_data[7..0] sd[2:0]_cmd, sd[2:0]_cd# sd[2:0]_clk sd[2:0]_wp sd[2:0]_pwr# sd[2:0]_led sd/mmc interface lpc_ad[3:0] lpc_frame# lpc_serirq lpc_clkout[2:0] lpc_clkrun# lpc interface intel ? hd audio interface hda_rst# hda_sync hda_clk hda_sdo hda_sdi[1:0] hda_docken# hda_dockrst# parallel ata (pata) interface pata_dcs1# pata_dcs3# pata_da[2:0] pata_dd[15:0] pata_ddreq pata_ddack# pata_dior# pata_diow# pata_iordy pata_ideirq rtc interface rtc_x1 rtc_x2 misc. signals and clocks da_refclkinp, da_refclkinn db_refclkinpssc, db_refclkinnssc bsel2 cfg[1:0] clk14 intvrmen spkr smi#, extts0 clkreq# gpio gpio[9:0] gpiosus[3:0] jtag interface tck tms tdi tdo trst# display data channel l_ddc_clk, l_ddc_data l_ctla_clk / l_ctlb_data l_vdden l_bklten, l_bkltctl
datasheet 29 signal description 2.1 host interface signals signal type power well description h_ads# i/o agtl+ core address strobe: the host bus owner asserts h_ads# to indicate the first of two cycles of a request phase. h_bnr# i/o cmos core block next request: this signal is used to block the current request bus owner from issuing a new request. this signal is used to dynamically control the processor bus pipeline depth. h_bpri# o agtl+ core priority agent bus request: the intel? sch is the only priority agent on the processor bus. it asserts this signal to obtain the ownership of the a ddress bus. this signal has priority over symmetric bus requests and wi ll cause the current symmetric owner to stop issuing new transactions unless the h_lock# signal was asserted. h_breq0# i/o cmos core bus request 0#: the intel? sch pulls the processor bus h_breq0# signal low during h_cpurst#. the signal is sampled by the processor on the active-to-inactive transition of h_cpurst#. h_breq0# should be tri-stated after the hold time requirement has been satisfied. h_cpurst# o agtl+ core cpu reset: h_cpurst # allows the processor to begin execution in a known state. the intel? sch asserts h_cpurst# and deasserts h_ cpupwrgd upon exit from its reset. h_cpurst# is deasserted 2?10 ms after h_cpupwrgd is asserted. h_dbsy# i/o agtl+ core data bus busy: this signal is used by the data bus owner to hold the data bus for transfers requiring more than one cycle. h_defer# i/o agtl+ core defer: the intel? sch will gene rate a deferred response as defined by the rules of the dynamic defer policy. the intel? sch will also use the h_defer# signal to indicate a processor retry response. h_dinv[3:0]# i/o cmos core dynamic bus inversion: these signals are driven along with the h_d[63:0]# signals. they indicate if the associated data bus signals are inverted or not. h_dinv[3:0]# are asserted such that the number of data bits driven electrically low (low voltage) within the corresponding 16-bit gr oup never exceeds 8. h_dinv[x]# data bits h_dinv3# h_d[63:48] h_dinv2# h_d[47:32] h_dinv1# h_d[31:16] h_dinv0# h_d[15:0] h_dpwr# o agtl+ core data power: used by intel? sch to indicate that a data return cycle is pending within 2 host clock cycles or more. the processor uses this sign al during a read-cycle to activate the data input buffers in preparation for h_drdy# and the related data. h_drdy# i/o agtl+ core data ready: this signal is asserted for each cycle that data is transferred.
signal description 30 datasheet h_a[31:3]# i/o cmos core host address bus: h_a[31:3]# connect to the processor address bus. during proce ssor cycles, h_a[31:3]# are inputs. note that the address bus is inverted on the processor bus. h_adstb[1:0]# i/o agtl+ core host address strobe: the source synchronous strobes are used to transfer h_a[31:3]# and h_req[4:0]# at the 2x transfer rate. h_adstb0# maps to h_ a[16:3]#, h_req[4:0]# h_adstb1# maps to h_a[31:17]# h_d[63:0]# i/o cmos core host data: these signals are connected to the processor data bus. note that the data signals are inverted on the processor bus. h_dstbp[3:0]# h_dstbn[3:0]# i/o agtl+ core host data strobes: the source synchronous strobes used to transfer h_d[63:0]# and h_dinv[3:0]# at the 4x transfer rate. strobe data bits h_dstb[p/n]3# h_d[63:48]#, h_dinv3# h_dstb[p/n]2# h_d[47:32]#, h_dinv2# h_dstb[p/n]1# h_d[31:16]#, h_dinv1# h_dstb[p/n]0# h_d[15:0]#, h_dinv0# h_hit# i/o cmos core hit: this signal indicates that a caching agent holds an unmodified version of the requ ested line. also, driven in conjunction with h_hitm# by the target to extend the snoop window. h_hitm# i/o cmos core hit modified: this signal indicates that a caching agent holds a modified version of the requested line and that this agent assumes responsibility for providing the line. this signal is also driven in conjunction with h_hit# to extend the snoop window. h_lock# i cmos core host lock: all processor bus cycles sampled with the assertion of h_lock# and h_ad s#, until the negation of h_lock# must be atomic. h_req[4:0]# i/o cmos core host request command: these signals are asserted during both clocks of the requ est phase. in the first clock, the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. in the second clock, the signals carry addition al information to define the complete transaction type. th e transactions supported by the intel? sch are defined in the host interface functional description section of this document. h_trdy# o agtl+ core host target ready: this signal indicates that the target of the processor transaction is able to enter the data transfer phase. signal type power well description
datasheet 31 signal description h_rs[2:0]# o agtl+ core response signals: these signals indicate the type of response as shown below: 000 = idle state 001 = retry response 010 = deferred response 011 = reserved (not driven by intel? sch) 100 = hard failure (not driven by intel? sch) 101 = no data response 110 = implicit writeback 111 = normal data response h_thrmtrip# i cmos core thermal trip: when low, this signal indicates that a thermal trip from the processor occurred, and corrective action will be taken. h_cpuslp# o cmos core cpu slp: this signal puts the pr ocessor into a state that saves power vs. the stop-grant state. however, during that time, no snoops occur. it will go active for all other sleep states. h_pbe# i cmos core pending break event: this signal can be used in some states for notification by the processor of pending interrupt events. h_init# o cmos _od core initialization: the intel? sch can be configured to support a special meaning to the processor during h_cpurst# deassertion. h_ init# functionality for resetting the processor is not supported. this signal requires a boar d-level pull-up. h_intr o cmos core processor interrupt: h_intr is assert ed by the intel? sch to signal the processor th at an interrupt request is pending and needs to be servic ed. it is an asynchronous output normally driven low. h_nmi o cmos core non-maskable interrupt: the h_nmi is used to force a non-maskable interrupt to th e processor. the processor detects the rising edge of h_ nmi. a non-maskable interrupt is reset by setting the corre sponding nmi source enable/ disable bit in the nmi stat us and control register. h_smi# o cmos core system management interrupt: the h_smi# is an output synchronous to lpc cloc k that is asserted by the intel? sch in response to on e of many enabled hardware or software events. h_stpclk# o cmos core stop clock request: h_stpclk# is an active-low output synchronous to lpc clock that is asserted by intel? sch in response to one of many hardware or software events. when the processor samples h_stpclk# asserted, it responds by stopping its internal clock. signal type power well description
signal description 32 datasheet 2.2 system memory signals h_dpslp# o cmos core deep sleep: this signal is asserted by the intel? sch to the processor. when the signal is low, the processor enters the deep sleep state by gating off the processor core clock inside the processor. when the signal is high (default), the processor is not in the deep sl eep state. this signal and the h_stpclk# pin shut the clock in the processor and at the clock generator, respectively. the h_dpslp# assertion time is wider than the h_stpclk# assertion time in order for the processor to receive an active clock input whenever h_dpslp# is deasserted. h_dprstp# o cmos core deeper sleep: when asserted on the platform, this signal causes the processor to tran sition from the deep sleep state to the deeper sleep state. to return to the deep sleep state, h_dprstp# mu st be deasserted. h_cpupwrgd o cmos core cpu power good: this signal is used for enhanced intel speedstep? technology suppo rt. h_cpupwrgd goes to the processor. it is kept hi gh during the enhanced intel speedstep ? technology state transition to prevent loss of processor context. host interface referen ce and compensation h_clkinp h_clkinn i cmos 0.8 core differential clock input for the host pll: this low- voltage differential signal pair is used for fsb transactions. the clock input also supplies a signal to the internal core and memory interface clocks. h_rcompo i/o a core host resistor compensation: this is connected to a reference resistor to dynami cally calibrate the driver strengths. h_swing i a core voltage swing calibration h_gvref h_cgvref i a core voltage reference: these pins are for the input buffer differential amplifier to determ ine a high versus a low input voltage. signal type power well description sm_dq[63:0] i/o cmos1.8 ddr data lines: the sm_dq[63:0] signals interface to the dram data bus. sm_dqs[7:0] i/o cmos1.8 ddr data strobes: these signals are the data strobes used for capturing data. each stro be signal corresponds to 8 data bits. during writes, sm_dqsx is centered in data. during reads, sm_dqsx is edge aligned with data. sm_ma[14:0] o cmos1.8 ddr memory address: these signals are used to provide the multiplexed row and colu mn address to the sdram. signal type power well description
datasheet 33 signal description sm_bs[2:0] o cmos1.8 ddr bank select (bank address): these signals define which banks are selected within each sdram row. bank select and memory address signals combine to address every possible location within an sdram device. sm_ras# o cmos1.8 ddr row address strobe: sm_ras# is used to signify the presence of the row address on sm_ma to the dram device bein g selected. sm_cas# o cmos1.8 ddr column address strobe: sm_cas# is used to signify the presence of the column address on sm_ma to the dram device being selected. sm_we# o cmos1.8 ddr write enable: sm_we# tells the dram memory that it is performing a write operation on the bus. sm_rcvenin# i cmos1.8 ddr receive enable in: this signal connects to sm_srcvenout# internally. this input (driven from sm_srcvenout#) enables the dqs input buffers during reads. sm_rcvenout# o cmos1.8 ddr receive enable out: this signal connects to sm_srcvenin# internally. it is part of the feedback used to enable the dqs in put buffers during reads. sm_ck[1:0] sm_ck[1:0]# o cmos1.8 ddr differential ddr clock: sm_ckx and sm_ckx# pairs are differential clock output s. the crossing of the positive edge of sm_ckx and the negative edge of sm_ckx# is used to sample the address and control signals on the dram. sm_cs[1:0]# o cmos1.8 ddr chip select: these signals select particular dram components during the active state. there is one sm_csx# for each dram rank, toggled on the positive edge of sm_ckx. sm_cke[1:0] o cmos1.8 ddr clock enable: sm_ckex is used to initialize dram during power-up and to place all dram rows into and out of self-refresh during the s3 suspend-to-ram low power state. sm_ckex is also used to dynamically power down inactive dram rows. there is one sm_ckex per sdram row, toggled on the positive edge of sm_ckx. sm_vref i a ddr input buffer vref: this signal is for the input buffer differential amplifier to dete rmine a high versus a low input voltage. sm_rcompo i/o a ddr resistor compensation output pin: this pin is connected to a reference resistor to dynamically calibrate the driver strengths. signal type power well description
signal description 34 datasheet 2.3 integrated display interfaces 2.3.1 lvds signals 2.3.2 serial digital video output (sdvo) signals signal type power well description la_datap[3:0] la_datan[3:0] o lvds core channel a differential data output: differential signal pair. la_clkp la_clkn o lvds core channel a differential clock output: differential signal pair. signal name type power well description sdvob_red+ sdvob_red- o pcie core serial digital video channel b red: sdvob_red[] is a differential data pair that provides red pixel data for the sdvob channel during active periods. during blanking periods it may provid e additional such as sync information, auxiliary configuration data, etc. this data pair must be sampled with respect to the sdvob_clk[] signal pair. sdvob_green+ sdvob_green- o pcie core serial digital video channel b green: sdvob_green[] is a differential data pair that provides green pixel data for the sdvob channel during active periods. during blan king periods it may provide additional such as sync information, auxiliary configuration data, etc. this data pair must be sampled with respect to the sdvob_clk[] signal pair. sdvob_blue+ sdvob_blue- o pcie core serial digital video channel b blue: sdvob_blue[] is a differentia l data pair that provides blue pixel data for the sd vob channel during active periods. during blanking periods it may provide additional such as sync information, auxiliary configuration data, etc. this data pair must be sampled with respect to the sdvob_clk[] signal pair. sdvob_clk+ sdvob_clk- o pcie core serial digital video channel b clock: this differential clock signal pair is generated by the intel? sch internal pll and ru ns between 100 mhz and 200 mhz. if tv-out mode is used, the sdvo_tvclkin[] clock input is used as the freque ncy reference for the pll. the sdvob_clk[] output pair is then driven back to the sdvo device. sdvob_int+ sdvob_int- i pcie core serial digital video input interrupt: differential input pair that may be used as an interrupt notification from the sdvo device to the intel? sch. this signal pair can be used to monitor hot plug attach/detach notifications for a monitor driven by an sdvo device.
datasheet 35 signal description 2.3.3 display data channe l (ddc) and gmbus support sdvo_tvclkin+ sdvo_tvclkin- i pcie core serial digital video tv-out synchronization clock: differential clock pair that is driven by the sdvo device to the intel? sch. if sdvo_tvclkin[] is used, it becomes the frequency reference for the intel? sch dot clock pll, but will be driven back to the sdvo device through the sdvob_ clk[] differential pair. this signal pair has an operating range of 100?200 mhz, so if the desired display frequency is less than 100 mhz, the sdvo device must apply a multiplier to get the sdvo_tvclkin[] frequency into the 100- to 200-mhz range. sdvo_stall+ sdvo_stall- i pcie core serial digital video field stall: differential input pair that allows a scaling sdvo device to stall the intel? sch pixel pipeline. sdvo_ctrlclk i/o cmos3.3 _od core sdvo control clock: single-ended control clock line from the intel? sch to the sdvo device. similar to i 2 c clock functionality, but may run at faster frequencies. sdvo_ctrlclk is used in conjunction with sdvo_ctrldata to transfer device config, prom, and monitor ddc information. this interface directly connects the intel? sch to the sdvo device. sdvo_ctrldata i/o cmos3.3 _od core sdvo control data: sdvo_ctrldata is used in conjunction with sdvo_ctrlc lk to transfer device config, prom, and monitor ddc information. this interface directly connects the intel? sch to the sdvo device. signal name type power well description l_ddc_clk i/o cmos3.3 _od core display data channel clock: i 2 c-based control signal (clock) for edid control. l_ddc_data i/o cmos3.3 _od core display data channel data: i 2 c-based control signal (data) for edid control. l_ctla_clk i/o cmos3.3 _od core control a clock : this signal can be used to control external clock chip for ssc - optional. l_ctlb_data i/o cmos3.3 _od core control b data : this signal can be used to control external clock chip for ssc ? optional. l_vdden o cmos3.3 core lcd power enable: panel power enable control. l_bklten o cmos3.3 core lcd backlight enable : panel backlight enable control. l_bkltctl o cmos3.3 core lcd backlight control: this signal allows control of lcd brightness. signal name type power well description
signal description 36 datasheet 2.4 universal serial bus (usb) signals 2.5 pci express* signals signal name type power well description usb_dp[5:0]/ usb_dn[5:0] i/o usb sus usb port 5:0 differentials: bus data/address/ command bus: these differential pairs are used to transmit data/address/command signals for ports 0 through 5. these ports can be routed to either the ehci controller or one of the three uhci controllers and are capable of running at either high-, full-, or low-speed. usb_dp[7:6]/ usb_dn[7:6] i/o usb sus usb port 7:6 differentials: bus data/address/ command bus: these differential pairs are used to transmit data/address/command signals for ports 6 and 7. these ports are routed only to the ehci controller and should be used only for in-system usb 2.0 devices. usb_rbiasp o a sus resistor bias p: this pin is an anal og connection point for an external resistor. th is signal is used to set transmit currents and in ternal load resistors. usb_rbiasn i a sus resistor bias n: this pin is an analog connection point for an external resistor. th is signal is used to set transmit currents and in ternal load resistors. usb_clk48 i usb sus 48-mhz clock: this optional clock is used to run the usb controller. by default, the intel? sch uses da_refclkin to clock the usb logic. usb_oc[7:0]# i cmos3.3 sus overcurrent indicators: these signals set corresponding bits in the usb controllers to indicate that an overcurrent condition has occurred. note: usb_oc[7:0]# are not 5-v tolerant. usbcc/ gpiosus3 i/o cmos3.3 sus usb client connect: this signal, on gpiosus3, may be used in systems where usb port 2 is configured for client mode. this indicates connection to an external usb host has been established. note: if usb client support is en abled, then this signal is dedicated for us b client connect. signal name type power well description pcie_petp[2:1] pcie_petn[2:1] o pcie core pci express transmit: pcie_petp[2:1] are pci express ports 2:1 transmit pair (p and n) signals. pcie_perp[2:1] pcie_pern[2:1] i pcie core pci express receive: pcie_perp[2:1] pci express ports 2:1 receive pair (p and n) signals. pcie_clkinp pcie_clkinn i pcie core pci express input clock: 100-mhz differential clock signals. pcie_icompo i/o a core pci express compensation pin: output compensation for both current and resistance. also for lvds and sdvo interfaces. pcie_icompi i/o a core pci express comp ensation pin: input compensation for current. also for lv ds and sdvo interfaces.
datasheet 37 signal description 2.6 secure digital i/o (sdio)/multimedia card (mmc) signals signal name type power well description sd0_data[3:0] sd1_data[3:0] sd2_data[7:0] i/o cmos3.3 core sdio controller 0/1/2 data: these signals operate in push-pull mode. the sd card includes internal pull-up resistors for all data lines. by default, after power-up, only sdn_data0 is used for data transfer. wider data bus widths can be configured for data transfer. note: port 0 and 1 are 4 bits wide while ports 2 is 8 bits wide. sd0_cmd sd1_cmd sd2_cmd i/o cmos3.3 core sdio controller 0/1/2 command: this signal is used for card initialization and tr ansfer of commands. it has two operating modes: open-drain for initialization mode, and push-pull for fast command transfer. sd0_clk sd1_clk sd2_clk o cmos3.3 core sdio controller 0/1/2 clock: with each cycle of this signal a one-bit transfer on the command and each data line occurs. this signal is generated by the intel? sch at a maximum frequency of: 24 mhz for sd and sdio. 48 mhz for mmc. sd0_wp sd1_wp sd2_wp i cmos3.3 core sdio controller 0/1/2 write protect : these signals denote the state of the write-protect tab on sd cards. sd0_cd# sd1_cd# sd2_cd# i cmos3.3 core sdio controller 0/1/2 card detect: these signals indicates when a card is pr esent in an external slot. sd0_led sd1_led sd2_led o cmos3.3 core sdio controller 0/1/2 led: these signals can be used to drive an external led and indicate when transfers are occurring on the bus. sd0_pwr# sd1_pwr# sd2_pwr# i/o cmos3.3 core sdio/mmc power enable: these pins can be used to enable the power being su pplied to an sdio/mmc device.
signal description 38 datasheet 2.7 parallel ata (pata) signals signal name type power well description pata_dd[15:0] i/o cmos3.3-5 core device data: these signals drive the corresponding signals on the pata connector. there is an internal 13.3-k pull-down on pata_dd7. pata_da[2:0] o cmos3.3-5 core device address: these output signals are connected to the corresponding signals on the pata connectors. they are used to indicate which byte in either the ata command block or control block is being addressed. pata_dior# o cmos3.3-5 core disk i/o read (pio and non-ultra dma): this is the command to the pata device that it may drive data onto the dd lines. data is latched by the intel? sch on the deassertion edge of pata_dior#. the pata device is selected either by the ata register file chip selects (pata_dcs1# or pata_dcs3#) and the pata_da lines, or the pata dma acknowledge (pata_ddak#). pata_diow# o cmos3.3-5 core disk i/o write (pio and non-ultra dma): this is the command to the pata device that it may latch data from the pata_dd lines. data is latched by the pata device on the deassertion edge of pata_diow#. the pata device is selected eith er by the ata register file chip selects (pata_dcs1# or pata_dcs3#) and the pata_da lines, or the pata dma acknowledge (pata_ddak#). pata_ddack# o cmos3.3-5 core device dma acknowledge: this signal directly drives the dak# signals on the pata connectors. each is asserted by the intel? sch to indicate to pata dma slave devices that a given data transfer cycle (assertion of pata_dior# or pata_diow#) is a dma data transfer cycle. this signal is used in conjunction with the pci bus master pa ta function and are not associated with any at -compatible dma channel. pata_dcs3# o cmos3.3-5 core device chip select for 300 range: this chip select is for the ata control regist er block. this signal is connected to the corres ponding signal on the connector. pata_dcs1# o cmos3.3-5 core device chip selects for 100 range: this chip select is for the ata command regist er block. this signal is connected to the correspond ing signal on the pata connector. pata_ddreq i cmos3.3-5 core device dma request: this input sign al is directly driven from the drq signals on the pata connector. it is asserted by the pata device to request a data transfer, and used in conjunction with the pci bus master pata function and ar e not associated with any at-compatible dma channel. there is an internal 13.3 k pull-down on this pin. pata_iordy i cmos3.3-5 core i/o channel ready (pio): this signal will keep the strobe active (pata_dior# on reads, pata_diow# on writes) longer than the minimum width. it adds wait states to pio transfers.
datasheet 39 signal description 2.8 intel hd audio interface pata_ideirq i cmos3.3-5 core ide interrupt : input from the pata device indicating request for an interrupt. ti ed internally to irq14. signal name type power well description hda_rst# o cmos_hda core intel? hd audio reset: this signal is the reset to external codecs hda_sync o cmos_hda core intel hd audio sync: this signal is an 48-khz fixed rate sample sync to the codec(s). it is also used to encode the stream number. hda_clk o cmos_hda core intel hd audio clock (output): this signal is a 24.000-mhz serial data cloc k generated by the intel hd audio controller. this signal contains an integrated pull-down resistor so that it does not float when an intel hd audio codec (or no codec) is connected. hda_sdo o cmos_hda core intel hd audio serial data out: this signal is a serial tdm data output to the codec(s). the serial output is double-pumped for a bit rate of 48 mb/s for hd audio. hda_sdi[1:0] i cmos_hda core intel hd audio serial data in: these serial inputs are single-pumped for a bit rate of 24 mb/s. they have integrated pull-down resistors that are always enabled. hda_docken# o cmos_hda core intel hd audio dock enable: this active low signal controls the external intel hd audio docking isolation logic. when deasserted, the external docking switch is in isolate mode. when asserted, the external docking switch electrically connects the intel hd audio dock signals to the corresponding intel sch signals. hda_dockrst# o cmos_hda core intel hd audio dock reset: this signal is a dedicated reset signal for th e codec(s) in the docking station. it works similar to, but independent of, the normal hda_rst# signal. signal name type power well description
signal description 40 datasheet 2.9 lpc interface 2.10 smbus interface signal name type power well description lpc_ad[3:0] i/o cmos3.3 core lpc address/data: multiplexed command, address, data lpc_frame# o cmos3.3 core lpc frame: this signal indicates the start of an lpc/ fhw cycle. lpc_serirq i/o cmos3.3 core serial interrupt request: this signal conveys the serial interrupt protocol. lpc_clkrun# i/o cmos3.3 core clock run: this signal gates the operation of the lpc_clkoutx. once an interrupt sequence has started, lpc_clkr un# should remain asserted to allow the lpc_clkoutx to run. lpc_clkout[2:0] o cmos3.3 core lpc clock: these signals are the clocks driven by the intel? sch to lpc devices. each clock can support up to two loads. note: the primary boot device like fwh and spi (behind smc) should be connected to lpc_clkout[0] signal name type power well description smb_data i/o cmos3.3 _od core smbus data: this signal is the smbus data pin. an external pull-up resistor is required. smb_clk i/o cmos3.3 _od core smbus clock: this signal is the smbus clock pin. an external pull-up resistor is required. smb_alert# i cmos3.3 _od core smbus alert: this signal can be used to generate an smi#.
datasheet 41 signal description 2.11 power management interface signal name type power well description thrm# i cmos3.3 core thermal alarm: this signal is an active low signal generated by external hard ware to generate an smi or sci. reset# i cmos3.3 ddr system reset: this signal forces a reset after being de-bounced. this signal is powered by v ccsm . pwrok i cmos3.3 rtc power ok: when asserted, pwrok is an indication to the intel? sch that co re power is stable. pwrok can be driven asynchronously. rsmrst# i cmos3.3 rtc resume well reset: this signal is us ed for resetting the resume well. an external rc circuit is required to ensure that the re sume well power is valid prior to rsmrst# going high. rtcrst# i cmos3.3 rtc rtc well reset: this signal is normally held high (to v cc_rtc ), but can be driven low on the motherboard to test the rtc power well and reset some bits in the rtc well registers that are otherwise not reset by slpmode or rsmrst#. an ex ternal rc circuit on the rtcrst# signal creates a time delay such that rtcrst# will go high some time after the battery voltage is valid. this allows the intel? sch to detect when a new battery has been installed. the rtcrst# input must always be high when other non-rtc power planes are on. note: unlike many previous products, the intel? sch does not use rtcrst# to clear cmos. rtcrst# does not set a bit which bios can then read as a directive to clear cmos. this signal is in the rtc power well. susclk o cmos3.3 sus suspend clock: this signal is an output of the rtc generator circuit (32.768 khz). susclk can have a duty cycle from 30% to 70%. wake# i cmos3.3 sus pci express* wake event: this signal indicates a pci express port wants to wake the system. stpcpu# o cmos3.3 core stop cpu clock: this signal is us ed to support the c3 state. asserting this signal halts the clocks to the processor by controlling the enable of the clock chip. dprslpvr o cmos3.3 core deeper sleep voltage regulator: this signal is asserted by the intel? sch to the processors voltage regulator. when the sign al is high, the voltage regulator outputs the lower ?deeper sleep? voltage. when the signal is low (default), the voltage regulator outputs the higher ?normal? voltage. this signal is in the core i/o plane and has a standard cmos output (not open drain). slpiovr# o cmos3.3 core sleep i/o voltage regulator disable: the slpiovr# can be connected to an external vr and be used to control power suppl ied to the processors i/o rail in the c6 state.
signal description 42 datasheet 2.12 real time clock interface slpmode o cmos3.3 sus sleep mode: slpmode determines which sleep state is entered. when slpmode is high, s3 will be chosen. when slpmode is low, s4/s5 will be the selected sleep mode. rstwarn i cmos3.3 sus reset warning : asserting the rstwarn signal tells the intel? sch to enter a sleep state or begin to power down. a system mana gement controller might do so after an external event, such as pressing of the power button or occurre nce of a thermal event. slprdy# o cmos3.3 sus sleep ready : the intel? sch will drive the slprdy# signal low to indicate to the system management controller that the intel? sch is awake and able to placed into a sleep state. deassertion of this signal indicates that a wake is being requested from a system device. rstrdy# o cmos3.3 sus reset ready : assertion of the rstrdy# signal indicates to the system management controller that it is ready to be placed into a low power state. during a transition from s0 to s3/4/5 sleep states, the intel? sch asserts rstrdy# and cpurst# after detecting assertion of the rstwarn si gnal from the external system management controller. gpe# i cmos3.3 _od sus general purpose event : gpe# is asserted by an external device (typically, the system management controller) to log an event in the intel? sch acpi space and cause an sci (if enabled). signal name type power well description rtc_x1 special a rtc crystal input 1: this signal is connected to the 32.768-khz crystal. if no exte rnal crystal is used, then rtc_x1 can be driven with the desired clock rate. rtc_x2 special a rtc crystal output 2: this signal is connected to the 32.768-khz crystal. if no exte rnal crystal is used, then rtc_x2 should be left floating. signal name type power well description
datasheet 43 signal description 2.13 jtag interface the jtag interface is accessible only after pwrok is asserted. 2.14 miscellaneous signals and clocks signal name type power well description tck i cmos sus jtag test clock: tck is a clock input used to drive test access port (tap) stat e machine during test and debugging. this input may change asynchronous to the host clock. tdi i cmos sus jtag test data in: tdi is used to serially shift data and instructions into the tap. tdo o cmos_od sus jtag test data out: tdo is used to serially shift data out of the device. tms i cmos sus test mode select: this signal is us ed to control the state of the tap controller. trst# i cmos sus test reset: this signal resets th e controller logic. it should be pulled down unless tck is active. signal name type power well description da_refclkinp/ da_refclkinn icore display plla clk differential pair: 96 mhz, no ssc support. db_refclkinpssc/ db_refclkinnssc icore display pllb clk differential pair: display pll differential clock pair for super ssc. clkreq# o cmos3.3 _od core clock required : the intel? sch will not de-assert clkreq# and will not thus enable a power management mode to the clock chip. clk14 i cmos3.3 core oscillator clock: this signal is used for 8254 timers and hpet. it runs at 14.31818 mhz. this clock stops (and should be low) duri ng s3, s4, and s5 states. clk14 must be accurate to within 500 ppm over 100 s (and longer periods) to meet hpet accuracy requirements. intvrmen i cmos3.3 rtc internal vrm enable: this signal is used to enable or disable the integrated 1.5-v voltage regulators for the suspend and auxiliary wells on the intel? sch. when connected to v ss , the vrms are disabled; when connected to the rtc power well, the vrms are enabled. this signal is in the rtc well. it is not latched and must remain valid for the vrms to behave properly. spkr o cmos3.3 core speaker: the spkr signal is the output of counter 2 and is internally anded with port 61h bit 1 to provide speaker data enable. this signal drives an external speaker driver devi ce, which in turn drives the system speaker. upon slpmode, its output state is 0.
signal description 44 datasheet 2.15 general purpose i/o smi# i cmos3.3 core system management interrupt: this signal is generated by the extern al system management controller. extts0# i cmos3.3 core external thermal sensor 0 event extts1#/gpio9 i cmos3.3 core external thermal sensor 1 event: extts1# is multiplexed with gpio9 bsel2 i cmos core host bus speed select: at the deassertion of reset#, the value sample d on bsel2 determines the expected frequency of the bus. refer to ta b l e 3 for more details. cfg[1:0] i cmos core configuration: strap pins used to configure the graphics/display cloc k frequency. refer to ta b l e 3 for more details. signal name type power well description gpio9/extts1# i/o cmos3.3 core general purpose i/o #9 / external thermal sensor 1: this gpio can function as a second external thermal sensor input. gpio8/ prochot# i/o cmos3.3 / od core general purpose i/o #8/processor hot: defaults to a gpio. as prochot#, this signal can function as an open- drain output to the processor or smc to signify a processor thermal event. gpio[6:0] i/o cmos3.3 core general purpose i/o: these signals are powered off of the core well power pl ane within the intel? sch. gpiosus3/ usbcc i/o cmos3.3 sus resume well general purpose i/o #3/usb client connect: this gpio can function as an input signifying connection to an external usb host. note: if a usb client is enabled in the system, then gpiosus3 cannot be used as a general purpose i/o. gpiosus[2:0] i/o cmos3.3 sus general purpose i/o: these signals are powered from the suspend well power plane within the intel? sch. they are accessible during the s3 sleep state. signal name type power well description
datasheet 45 signal description 2.16 power and ground signals note: 1. nctf (non-critical to function) signals have been designed into the package footprint to enhance the solder joint reliability of our pr oducts. the nctf signals have been designed to absorb some of the stress introduced by the characte ristic thermal expansion (cte) interface ball name nominal voltage description common vcc 1.05 core supply vss vss_nctf 1 0ground host vtt 1.05 used for fsb input and output devices vccahpll 1.5 analog power supply vccdhpll 1.5 digital power supply ddr2 vccsm 1.8 1.5 driver and rx supply configurable for 1.8-v/1.5-v operation sdvo/ pcie/ lvds vcclvds 1.5 dedicated lvds suppl y (must be supplied even if the sdvo only interface is used). vccsdvo 1.5 dedicated sdvo supply (must be supplied if the interface is used. if sdvo is not used, this supply is not needed for the intel? sch). vccpcie 1.5 dedicated pcie* analog/digital supply vccapciepll 1.5 pcie pll vccapciebg 3.3 band gap (needs to be enabled for pcie, sdvo or lvds) vssapciebg 0 pcie band gap vss display pll vccadplla 1.5 display pll a power supply (digital and analog) must be powered even if dplla is not used. vccadpllb 1.5 display pll b power supply (digital and analog) must be powere d even if dpllb is not used. intel high definition audio vcc15 1.5 used for i/o digital logic vcchda 3.3/1.5 configurable for 3.3-v or 1.5-v operation vcc33 3.3 used for some internal 3.3-v circuits sdio/mmc/ cmos/lpc/ pata vcc15 1.5 used for i/o digital logic vcc33 3.3 used for i/o analog driver vcc5ref 5 used for 5-v tolera nce on core group inputs usb vccausbpll 1.5 usb pll supply. must be powered even if usb is not used vcc15usb 1.5 power for usb logic and analogs. vccp33usbsus 3.3 usb 3.3-v supply vccausbbgsus 3.3 usb band gap vssausbbgsus 0 usb band gap v ss vcc5refsus 5 5-v supply in suspend power well cmos suspend vcc33sus 3.3 3.3-v suspend power supply vcc33rtc 3.3 used for real time clock
signal description 46 datasheet mismatch between the die-to-package interface . if cracking between the die-to-package interface occurs, produc t performance or reliability is not affected. 2.17 functional straps the following signals are used to configur e certain intel? sch features. all strap signals are in the core power well. they ar e sampled at the rising edge of pwrok and then revert later to their normal usage. stra ps should be driven to the desired state at least four lpc (pci) clocks prio r to the rising edge of pwrok. table 3. functional strap definitions signal name strap function comments bsel2 cfg[1:0] fsb/ddr frequency select graphics frequency select bsel2: selects the frequency of the host interface and ddr interface. normal system configuration will have this signal connected to the processor?s bsel2 signal and will not requir e external pull-up/pull- down resistors. cfg[1:0]: selects the frequ ency of the internal graphics device. gpio3 gpio0 cmc (chipset microcode) base address selects the starting address that the cmc will use to start fetching code (gpio3 is the most significant). reserved1 lpc_clkout[0] buffer strength selects the drive strength of the lpc_clkout0 clock. 0 = 1 load driver strength 1 = 2 load driver strength xor_test xor chain enable enables xor chain mode 0 = xor mode enable 1 = xor mode disable (default) note: xor_test includes an internal pullup resistor. bsel2 cfg1 cfg0 fsb freq gfx freq 1 0 0 100 mhz 200 mhz 0 0 0 133 mhz 266 mhz 0 0 1 133 mhz 200 mhz all other combinations are reserved gpio3 gpio0 cmc base address 00 fffb0000h 01 fffc0000h 10 fffd0000h (default) 11 fffe0000h
datasheet 47 pin states 3 pin states this chapter describes the states of each inte l? sch signal in and around reset. it also documents what signals have internal pull-up/pull-down/series termination resistors and their values. 3.1 pin reset states table 4. reset state definitions signal state description high-z the intel? sch places this output in a high-impedance state. for i/os, external drivers are not expected. don?t care the state of the input (driven or tri-stated) does not effect the intel? sch. for i/o, it is assumed the output buffer is in a high-impedance state. v oh the intel? sch drives this signal high v ol the intel? sch drives this signal low vox?known the intel? sch drives this signal to a level defined by internal function configuration vox?unknown the intel? sch drives this signal, but to an indeterminate value v ih the intel? sch expects/requires the signal to be driven high. v il the intel? sch expects/requires the signal to be driven low. pull-up this signal is pulled high by a pull-up resistor (internal or external) pull-down this signal is pulled low by a pu ll-down resistor (internal or external) vix-unknown the intel? sch expects the signal to be driven by an external source, but the exact electrical level of that input is unknown. running the clock is toggling or signal is tran sitioning because the function has not stopped. off the power plane for this signal is powered down. the intel? sch does not drive outputs and inputs should not be driven to the intel? sch.
pin states 48 datasheet table 5. intel? sch reset state (sheet 1 of 5) signal name direction r eset post-reset s3 s4/s5 host interface h_a[31:3]# i/o voh pull-up off off h_d[63:0]# i/o voh pull-up off off h_ads# i/o voh pull-up off off h_bnr# i/o voh pull-up off off h_bpri# o voh pull-up off off h_dbsy# i/o voh pull-up off off h_defer# i/o voh pull-up off off h_drdy# i/o voh pull-up off off h_dpwr# o voh vol off off h_hit# i/o voh pull-up off off h_hitm# i/o voh pull-up off off h_lock# i vih pull-up off off h_req[4:0]# i/o voh pull-up off off h_cpuslp# o voh voh off off h_trdy# o voh pull-up off off h_rs[2:0]# o voh pull-up off off h_cpurst# o vol pull-up off off h_breq0# i/o vil pull-up off off h_dinv[3:0]# i/o voh pull-up off off h_adstb[1:0]# i/o voh pull-up off off h_dstbp[3:0]#, h_dstbn[3:0]# i/o voh pull-up off off h_thermtrip i vix-unknown pull-up off off h_pbe# i vih pull-up off off h_init# o vox-unknown pull-up off off h_intr o vol vol off off h_nmi o vol vol off off h_smi# o voh voh off off h_stpclk# o voh voh off off h_clkinp, h_clkinn i running running off off h_rcompo i/o-a high-z high-z off off h_gvref i-a vix-unknown vix-unknown off off h_gcvref i-a vix-unknown vix-unknown off off h_swing i-a vix-unknown vix-unknown off off h_dpslp# o voh voh off off h_cpupwrgd o vol vol off off
datasheet 49 pin states h_dprstp# o voh voh off off system memory interface sm_dq[63:0] i/o high-z high-z off off sm_dqs[7:0] i/o high-z high-z off off sm_ma[14:0] o high-z vol off off sm_bs[2:0] o high-z vol off off sm_ras# o high-z voh off off sm_cas# o high-z voh off off sm_we# o high-z voh off off sm_rcevenin# i high-z high-z off off sm_rcvenout# o high-z high-z off off sm_ck[1:0] o high-z voh off off sm_ck[1:0]# o high-z vol off off sm_cs[1:0]# o high-z voh off off sm_cke[1:0] o vol vol vol off sm_vref i-a vix-unknown vix-unknown don't care off sm_rcomp i-a high-z high-z high-z off lvds la_datap[3:0], la_datan[3:0] o voh voh off off la_clkp/n o voh voh off off sdvo sdvob_green+, sdvob_green- opull-uphigh-zoffoff sdvob_blue+, sdvob_blue- opull-uphigh-zoffoff sdvob_red+, sdvob_red- opull-uphigh-zoffoff sdvob_clk+, sdvob_clk- opull-uphigh-zoffoff sdvob_tvclkin+, sdvob_tvclkin- i don't care don't care off off sdvo_int+, sdvo_int- i don't care don't care off off sdvo_stall+, sdvo_stall- i don't care don't care off off sdvo_ctrlclk i/o pull-up high-z off off sdvo_ctrldata i/o pull-up high-z off off table 5. intel? sch reset state (sheet 2 of 5) signal name direction reset post-reset s3 s4/s5
pin states 50 datasheet ddc l_ddc_clk i/o pull-up high-z off off l_ddc_data i/o pull-up high-z off off l_ctlclka/b i/o pull-up high-z off off l_vdden o high-z high-z off off l_bklten o high-z high-z off off l_bkltctl o high-z high-z off off usb usb_dp[7:0] usb_dn[7:0] i/o vol vol vox-unknown off usb_oc[7:0]# i vix-unknown vi x-unknown vix-unknown off usb_rbiasp i-a high-z high-z high-z off usb_rbiasn i-a high-z high-z high-z off usb_clk48 i don't care don't care off off pci express* clkreq# o vox-known vox-known off off pcie_petp[2:1] o pull-up vol off off pcie_petn[2:1] o voh voh off off pcie_perp[2:1] i don't care don't care off off pcie_pern[2:1] i don't care don't care off off pcie_clkinp, pcie_clkinn i don't care don't care off off pcie_icompo, pcie_icompi i/o high-z high-z off off sdio/mmc sd0_data[3:0] i/o pull-up high-z off off sd1_data[3:0] i/o pull-up high-z off off sd2_data[7:0] i/o pull-up high-z off off sd[2:0]_cmd i/o pull-up high-z off off sd[2:0]_clk o vol vol off off sd[2:0]_wp i/o don't care don't care off off sd[2:0]_cd# i/o don't care don't care off off sd[2:0]_led o vol high-z off off sd[2:0]_pwr# o vol high-z off off table 5. intel? sch reset state (sheet 3 of 5) signal name direction r eset post-reset s3 s4/s5
datasheet 51 pin states pata pata_dcs1# o voh voh off off pata_dcs3# o voh voh off off pata_da[2:0] o vox-unknown vox- unknown off off pata_dd[15:0] i/o high-z high-z off off pata_ddreq i vil vil off off pata_ddack# o voh voh off off pata_dior# o voh voh off off pata_diow# o voh voh off off pata_iordy i vih vih off off pata_ideirq i vil vil off off intel? hd audio) hda_rst# o vol vol off off hda_sync o high-z high-z off off hda_clk o high-z vol off off hda_sdo o high-z high-z off off hda_sdi[1:0] i don't care don't care off off hda_docken# o voh voh off off hda_dockrst# o voh voh off off lpc lpc_lad[3:0] i/o high-z high-z off off lpc_frame# o voh voh voh off lpc_serirq i/o high-z high-z off off lpc_clkout[2:0] o vol vol vol off lpc_clkrun# i/o voh voh voh off smbus smb_data i/o high-z high-z off off smb_clk i/o high-z high-z off off smb_alert# i high-z high-z off off power management thrm# i vix-unknown vix-unknown off off reset# i vil vih vil off pwrok i vix-unknown vil vil vil rsmrst# i vix-unknown vih vih vil rtcrst# i vix-unknown vih vih vih susclk o running running running off table 5. intel? sch reset state (sheet 4 of 5) signal name direction reset post-reset s3 s4/s5
pin states 52 datasheet notes: 1. the intel? sch power-on is a very cont rolled sequence with several intermediate transitional states before th e true reset is reached (thi s is a reset state from pwrok asserted high to reset# deas serted high). pin values ar e not ensured to be at the specified reset state until all power supplies and input clocks are stable. the 3.3 v i/o pins may glitch, toggle or float. wake# i vix-unknown vix-unknown vix-unknown off stpcpu# o voh voh off off dprslpvr o vol vol off off slpmode o vol vol voh off rstwarn i vih vih vih off slprdy# o voh voh vol off rstrdy# o voh voh vol off gpe# i vix-unknown vix-unknown vix-unknown off slpiovr# i/o high-z high-z off off real time clock rtc_x1 i-a running running running running rtc_x2 i-a running running running running jtag tck i pull-up pull-up off off tms i pull-up pull-up off off tdi i pull-up pull-up off off tdo o high-z high-z off off trst# i pull-up pull-up off off miscellaneous bsel2 i vix-unknown vix-unknown off off cfg[1:0] i vix-unknown vix-unknown off off clk14 i running running off off intvrmen i vih vih vih vih spkr o vol vol vol off smi#, i vix-unknown vix-unknown off off extts i x x off off gpio gpio[6:0], gpio[9:8] i/o high-z high-z off off gpiosus[3:0] i/o high-z high-z vix-unknown off table 5. intel? sch reset state (sheet 5 of 5) signal name direction r eset post-reset s3 s4/s5
datasheet 53 pin states 3.2 integrated termination resistors table 6. intel? sch integrat ed termination resistors signal resistor type nominal value tolerance gpio3 pull-up 22 k 20% gpio0 pull-down 22 k 20% hda_clk pull-down 22 k 20% hda_dockrst# pull-down 20 k 20% hda_rst# pull-down 22 k 20% hda_sdi[1:0] pull-down 22 k 20% hda_sdo pull-down 22 k 20% hda_sync pull-down 22 k 20% la_clkn, la_clk_p pull-up 50 20% la_datan[3:0], la_datap[3:0] pull-up 50 20% lpc_lad[3:0] pull-up 20 k 20% pata_da[2:0] series 33 20% pata_dcs1# series 33 20% pata_dcs3# series 33 20% pata_dd[16:0] series 33 20% pata_dd7 pull-down 13.3 k 20% pata_ddack# series 33 20% pata_ddreq series 33 20% pata_ddreq pull-down 13.3 k 20% pata_dior# series 33 20% pata_diow# series 33 20% pata_ideirq series 33 20% pata_iordy series 33 20% pcie_pern[2:1], pcie_p erp[2:1] pull-down 50 20% pcie_petn[2:1], pcie _petp[2:1] pull-up 50 20% reserved1 pull-up 300 k 20% reset# pull-down 50 k 20% sd[2:0]_pwr# pull-up 60 k 20% sd2_data[7:0] sd[1,0]_data[3:0] pull-up 75 k 30% sdvob_red, sdvob_red# pull-up 50 20% sdvob_blue, sdvo b_blue# pull-up 50 20% sdvob_green, sdvo b_green# pull-up 50 20% sdvob_clk, sdvob_clk# pull-up 50 20% sdvob_clk# pull-up 50 20%
pin states 54 datasheet sdvob_int, sdvob_int# pull-down 50 20% sdvob_stall, sdvob_stall# pull-down 50 20% sdvob_tvclkin, sdvob_tvclkin# pull-down 50 20% stpcpu# pull-down 20 k 20% tck pull-up 5 k 40% tms pull-up 5 k 40% tdi pull-up 5 k 40% usb_dn[7:0]. usb_dp[7:0] pull-down 15 k 20% usb_dn2, usb_dp2 (client mode) pull-up 1.5 k 20% table 6. intel? sch integrat ed termination resistors signal resistor type nominal value tolerance
datasheet 55 system clock domains 4system clock domains the intel? sch contains many clock frequency domains to support its various interfaces. ta b l e 7 summarizes these domains. note: these are clock domains that are fractional multiples of existing clock frequencies. table 7. intel? sch clock domains clock domain signal name frequency source usage fsb h_clkinp h_clkinn 100 mhz or 133 mhz main clock generator used to generate core and sm internal clocks. pci express* pcie_clkin[p:n] 100 mhz mai n clock generator pci express ports display reference clock da_refclkin db_refclkinssc 96 mhz 100 mhz main clock generator primary clock source for display clocks, usb controllers, sdio, hd audio clk14 clk14 14.31818 mhz main clock generator used by acpi timer and the multimedia timers logic. stopped during s1 or higher. rtc rtc_x1, rtc_x2 32.768 khz cyrstal oscillator rtc, power management. always running. derivative clocks: see note ddr2 sm_ck[1:0] sm_ck[1:0]# 200 mhz or 266 mhz intel? sch (2x fsb clock) drives sdram ranks 0 and 1. data rate is 2x the clock rate. lvds, sdvo la_clk[p/n] sdvob_clk 100?200 mhz intel? sch (multiple of da_refclkin) display clock outputs lpc lpc_clkout[1:0] up to 33 mhz intel? sch (? fsb clock) supplied for external devices requiring pciclk usb2 n/a 480 mhz intel? sch (5x da_refclkin) usb pll intel hd audio hda_clk 24 mhz intel? sch (1/4 da_refclkin) drives external codecs sd/sdio mmc sd[2:0]_clk 24 mhz 48 mhz 1/4 da_refclkin 1/2 da_refclkin
system clock domains 56 datasheet (this page intentionally left blank.)
datasheet 57 register and memory mapping 5 register and memory mapping the intel? sch contains registers that are located in the processor?s memory and i/o space. it also contains sets of pci configuration registers that are located in separate configuration space. this chapter describes the intel? sch i/o and memory maps at the register-set level. register-level a ddress maps and individual register-bit descriptions are provided in the following ch apters and constitute the bulk of this document. the following notations and definitions are us ed in the register/instruction description chapters. table 8. register access types and definitions access type meaning description ro read only in some cases, if a register is read only, wr ites to this register location have no effect . however, in other cases, two separate registers are located at the same location where a read accesses one of the registers and a write accesses the other register. see the i/o and memory map tables for details. wo write only in some cases, if a register is write only, reads to this register location have no effect . however, in other cases, two separate registers are located at the same location where a read accesses one of the registers and a write accesses the other register. see the i/o and memory map tables for details. r/w read/write a register with this attribute can be re ad and written. r/wc read/write clear a register bit with this attribute can be read and written. however, a write of 1 clears (sets to 0) the corresponding bit and a write of 0 has no effect. r/wo read/write- once a register bit with this attribute can be written only once after power up. after the first write, the bit becomes read only. r/wlo read/write, lock-once a register bit with this attribute can be written to the non- locked value multiple times, but to the locked value only once. after the locked value has been written, the bit becomes read only. default default when the intel? sch is reset, it sets its registers to predetermined default states. the default state represents the minimum functionality feature set required to successfully bring up the system. hence, it does not represent the optimal system configuration. it is the responsibility of the system initialization software to determine configuration, operat ing parameters, and optional system features that are a pplicable, and to program the intel? sch registers accordingly.
register and memory mapping 58 datasheet 5.1 intel? sch register introduction the intel? sch contains two sets of software accessible registers accessed through the host processor i/o address space: control registers and internal configuration registers. 1. control registers are i/o mapped into the processor i/o space that control access to pci and pci express configuration space (see section entitled i/o mapped registers). 2. internal configuration registers residing within the intel? sch are partitioned into eight logical device register sets, one for each pci device listed in ta b l e 9 . (these are ?logical? devices because they reside within a single physical device). the intel? sch internal registers (i/o mapped, configuration and pci express extended configuration registers) are accessible by the host processor. the registers that reside within the lower 256 bytes of each device can be accessed as byte, word (16-bit), or dword (32-bit) quantities, wi th the exception of config_address, which can only be accessed as a dword. all multi-byte numeric fields use little-endian ordering (i.e., lower addresses contain the least significant parts of the field). registers which reside in bytes 256 through 4095 of each device may only be accessed using memory mapped transactions in dword (32-bit) quantities. some of the intel? sch registers described in this section contain reserved bits. these bits are labeled reserved. software must deal correctly with fields that are reserved. on reads, software must use appropriate mask s to extract the defined bits and not rely on reserved bits being any particular value. on writes, software must ensure that the values of reserved-bit positions are preserved. that is, the values of reserved-bit positions must first be read, merged with the new values for other-bit positions and then written back. note: the software does not need to perform read, merge, and write operation for the configuration address register. in addition to reserved bits within a regist er, the intel? sch contains address locations in the configuration space of the host bridge entity that are marked either reserved or intel reserved. the intel? sch responds to accesses to reserved address locations by completing the host cycle. when a reserved register location is read, a zero value is returned. (reserved registers can be 8, 16, or 32 bits in size). writes to reserved registers have no effect on the intel? sch. registers that are marked as intel reserved must not be modified by system so ftware. writes to intel reserved registers may cause system failure. reads from intel reserved registers may return a non-zero value. upon a cold reset, the intel? sch sets all configuration registers to predetermined default states. some default register values are determined by external strapping options. the default state represents the mi nimum functionality feature set required to successfully bringing up the system, it does not represent the optimal system configuration. it is the responsibility of the system initialization software (usually bios) to properly determine the dram configurat ions, operating parameters and optional system features that are applicable an d to program the intel? sch registers accordingly.
datasheet 59 register and memory mapping 5.2 pci configuration map the intel? sch incorporates a variety of pci devices and functions, as shown in ta b l e 9 . there are two access mechanisms to the co nfiguration space within the intel? sch: ? through i/o ports cf8h/cfch ? through a direct memory mapped space table 9. pci devices and functions device function function description 0 0 host bridge 2 0 integrated graphi cs and video device 26 0 usb client 27 0 hd audio controller 28 0 pci express port 1 1 pci express port 2 29 0 usb classic uhci controller 1 1 usb classic uhci controller 2 2 usb classic uhci controller 3 7 usb2 ehci controller 30 0 sdio/mmc port 0 1 sdio/mmc port 1 2 sdio/mmc port 2 31 0 lpc interface 1pata controller
register and memory mapping 60 datasheet 5.3 system memory map the intel? sch supports up to 2 gb of ph ysical ddr2 memory space and 64 kb+3 of addressable i/o space. there is a programmable memory address space under the 1 mb region which is divided into regions that can be individually controlled with programmable attributes such as disable, read/write, write only, or read only. this section describes how the memory space is partitioned and how those partitions are used. top of memory (tom) is the highest address of physical memory actually installed in the system. tom greater than 2gb is not supported. memory addresses above 2 gb will be routed to internal controllers or external i/o devices. any memory access between tom and 2 gb will return indeterminate results, and writes will be ignored. figure 3 represents system memory address map in a simplified form. figure 3. system address ranges pci memory address range main memory address range legacy address range 2 gb 1 mb 4 gb 0 (tom) table 10. intel? sch memory map (sheet 1 of 2) device starting address ending address comment legacy address range (0 to 1 mb) legacy video (vga) 000a0000h 000bffffh access to this range will be forward to pci express if the intel graphics media adapter is disabled. expansion area 000c0000h 000dffffh extended bios (lpc) 000e0000h 000effffh bios (lpc) 000f0000h 000fffffh lpc 000e0000h 000fffffh main memory 1 (1 mb to top of memory 2 ) tseg variable variable system management mode memory graphics variable variable
datasheet 61 register and memory mapping notes: 1. all accesses to addresses within the main me mory range will be forwarded by the intel? sch to the dram unless they fall into one of the optional ranges specified in this section. 2. top of memory is determined by examinin g the contents of the dram rank population register and calculating the total system memory based on the device width, device density, and number of ranks installed. up to 2 gb of total system memory is supported. 3. the chipset microcode (cmc) base address locates within the lpc space and consumes 64 kb of space. the starting address for the cmc code can be fffb0000h, fffc0000h, fffd0000h, or fffe0000h. refer to section 2.17 for selecting the cmc start address. make sure to avoid using the same starting address for other lpc devices in the system. pci configuration space (2 gb to 4 gb) ioxapic fec00000h fec00040h hpet fed00000h fed003ffh high performance event timer tpm 1.2 fefd40000h fed4bfffh lpc high bios fff80000h ffffffffh lpc, see note 3 for cmc address space configurable main memo ry configuration spaces pci express port 1 anywhere in 32-b it range configured by d30:f0:mbl pci express port 1 (prefetchable) anywhere in 32-bit range c onfigured by d30:f0:pmbl pci express port 2 anywhere in 32-b it range configured by d30:f1:mbl pci express port 2 (prefetchable) anywhere in 32-bit range c onfigured by d30:f1:pmbl root complex base register 1 kb anywhere in 32-bit rang e configured by d30:f0:rcba usb2 host controller 1 kb anywhere in 32-bit rang e configured by d20:f7:mem_base intel hd audio host controller 512 kb anywhere in 32-bit range configured by d27:f0:lbar sdio 1 1 kb anywhere in 32-bit range configured by d30:f0:mem_base sdio 2 1 kb anywhere in 32-bit range configured by d30:f1:mem_base sdio 3 1 kb anywhere in 32-bit range configured by d30:f2:mem_base table 10. intel? sch memory map (sheet 2 of 2) device starting address ending address comment
register and memory mapping 62 datasheet 5.3.1 legacy video ar ea (a0000h ? bffffh) the legacy 128 kb vga-memory range can be mapped to the intel graphics media adapter (device 2) or forwarded to an exte rnal graphics device located on one of the two pci express i/o ports. the vga-disable bit in the graphics control register of the intel graphics media adapter pci config space can be set to ignore vga memory or i/o cycles. if that bit is set, the intel? sch will steer vga accesses to the appropriate pci express port. if such a device does not exist in the system, the cycles will be ignored. 5.3.2 expansion area (c0000h ? dffffh) this 128-kb isa-expansion region is always mapped to dram. this region is typically used by bios to shadow (copy) option ro ms, including video bios. this region cannot be write protected. 5.3.3 extended system bios area (e0000h ? effffh) this area is a single, 64-kb segment that can be assigned independent read/write attributes and is mapped only to main dram typically, this area is used for ram or rom. memory segments that are disabled are not remapped elsewhere. 5.3.4 system bios area (f0000h ? fffffh) this area is a single, 64-kb segment that can be assigned read and write attributes. after reset, this region defaults to ?dis abled? and cycles are forwarded to the lpc interface. by manipulating the read/write a ttributes of this memory range, the intel? sch can ?shadow? bios into the main dram. when disabled, this segment is not remapped. 5.3.5 ehci controller area the ehci controller (device 29, function 7) requires a single, 1-kb to be reserved out of the 1-gb main memory area for configuration purposes. see chapter 13 for more details. 5.3.6 programmable attribute map (pam) the two, 64-kb memory regions below 1- mb comprise the pam memory area. see ta b l e 1 1 for these ranges and default attributes. any attempts by the processor or an intel? sch device to read a segment marked with the read disable attribute will return undefined data. table 11. programmable attribute map region memory segments default attributes ?segment e? 0e0000h ? 0effffh r/w ?segment f? 0f0000h ? 0fffffh we re
datasheet 63 register and memory mapping 5.3.7 top of memory segment (tseg) tseg is a 1-mb, 2-mb, or 8-mb memory region located below intel graphics media adapter stolen memory, which is at the top of physical memory (tom). it is used for system management mode accesses by the processor. see ta b l e 1 0 for more information on smm. processor accesses to the tseg range without smm attribute or without wb attribute are forwarded to memory as invalid accesses. non-smm-mode write back cycles that target tseg space are completed to dram for cache coherency. the tseg memory region is not accessible by non-processor bu s masters (that is, pci express, usb, etc.) 5.3.8 apic configuration space (fec00000h ? fecfffffh) this range is reserved for apic configurat ion space which includes an ioxapic and a local (processor) apic. the ioxapic is loca ted at the default address fec00000h to fec70fffh and is part of the lpc bridge co ntroller (device 31, function 0). the default local apic configuration space goes from fec80000h to fecfffffh. processor accesses to the local apic configuration space do not result in external bus activity since the local apic configuration sp ace is internal to the processor. however, an mtrr must be programmed to make the local apic range uncacheable (uc). the local apic base address in each processo r should be relocated to the fec00000h to fecfffffh range so that one mtrr can be pr ogrammed to 64 kb for the local and ioxapic. 5.3.9 high bios area the top 2 mb (ffc00000h ? ffffffffh) of the pci memory address range is reserved for system bios (high bios), extended bios for pci devices. the processor begins execution from the high bios after reset. th is region is mapped to the lpc controller so that the upper subset of this region aliases to the 16-mb through 256-kb range . the actual address space required for the bios is less than 2 mb but the minimum processor mtrr range for this region is 2 mb so that full 2 mb must be considered. 5.3.10 boot block update the intel? sch supports a top-block swap mode where the top boot block on the firmware hub (fwh) is swapped with a block in a different location. this allows the boot block to be safely updated while prot ecting the system from a power loss when bc.ts is set, the inte l? sch inverts a16 for cycles going to the upper two 64 kb blocks in the firmware. when bc.ts is cleared, the intel? sch will not invert a16. this bit is cleared by rtcrst#. the scheme is based on the concept that the top block is reserved as the ?boot? block, and the block immediately below the top block is reserved for doing boot-block updates.
register and memory mapping 64 datasheet the algorithm is as follows: 1. software copies the contents of the top boot-block to the swap block below it. 2. software checks that the copy was successful by checksum or other validation technique. 3. software sets the top_swap bit. this will invert a16 for cycles going to the firmware hub and force the processor to read from the swapped block location. (processor access to fff f 0000h through fff f ffffh will be directed to fff e 0000h through fff e ffffh in the firmware hub.) 4. software erases the top block. 5. software writes the new top block. 6. software validates the new top block is correct. 7. software clears the top_swap bit allowing normal processor access to the top block address range (ffff0000h through ffffffffh). 8. software sets the top_swap lock-down bit. if a power failure occurs at any point after st ep 3, the system will be able to boot from the copy of the boot block that is stored in the block below the top. this is because a copy of the top_swap bit is stored in the rtc well. note: the top-block swap mode may be forced by an external strapping option. when top- block swap mode is forced in this manner, the top_swap bit cannot be cleared by software. system management mode (smm) uses main memory for system management ram (smm ram). smm uses either a 1-mb, 2-mb, or 8-mb memory region located at the top of memory segment (tseg) in main memory (above the 1-mb boundary). this memory segment in ram is available for the smi handlers and code and data storage, and it is normally hidden from the system os so that the processor has immediate access to this memory space upon entry to smm. the tseg area can be mapped to any address within the 32-bit address range. for more details on the location and size of the smm memory areas, refer to ta b l e 1 0 or the host smm control (hsmmctl) regist er definition later in this chapter. note: other intel? sch bus masters are no t allowed to access the smm space. 5.3.11 memory shadowing any block of memory that can be designat ed as read-only or write-only can be ?shadowed? into intel? sch dram memory. typically this is done to allow rom code to execute more rapidly out of main dram. rom is used as read-only during the copy process while dram at the same time is designated write-only. after copying, the dram is designated read-onl y so that rom is shadowed. processor fsb transactions are routed accordingly. 5.3.12 locked transactions only locked cycles to dram are supported by the intel? sch. locked cycles to non- dram space are unsupported in the intel? sc h. this includes all non-physical dram address spaces including peripheral de vice memory, vga memory, memory-mapped i/o, and other memory spaces besides standard dram.
datasheet 65 register and memory mapping 5.4 i/o address space the i/o map is divided into fixed ranges and variable ranges. fixed ranges cannot be moved, but in some cases can be disabled. variable ranges can be both moved and disabled. 5.4.1 fixed i/o decode ranges ta b l e 1 2 shows the fixed i/o decode ranges from the processor. for each port there may be separate behavior for reads and writes. processor cycles that go to reserved ranges are internally aborted; if the cycle was a read, all 1s will be returned to the processor. table 12. fixed i/o decode ranges (sheet 1 of 2) port number size (bytes) read target write target can disable? 20h 2 8259 master 8259 master no 24h 2 8259 master 8259 master no 28h 2 8259 master 8259 master no 2ch 2 8259 master 8259 master no 30h 2 8259 master 8259 master no 34h 2 8259 master 8259 master no 38h 2 8259 master 8259 master no 3ch 2 8259 master 8259 master no 40h 3 8254 8254 no 43h 1 none 8254 no 50h 3 8254 8254 no 53h 1 none 8254 no 61h 1 nmi controller nmi controller 1 no 63h 1 nmi controller nmi controller 1 yes, alias to 61h 65h 1 nmi controller nmi controller 1 yes, alias to 61h 67h 1 nmi controller nmi controller 1 yes, alias to 61h 70h 1 none nmi and rtc no 71h 1 rtc rtc no 72h 1 rtc nmi and rtc yes, w/ 73h 73h 1 rtc rtc yes, w/ 72h 74h 1 rtc nmi and rtc no 75h 1 rtc rtc no 76h 1 rtc nmi and rtc no 77h 1 rtc rtc no 84h 3 internal internal/lpc no 88h 1 internal internal/lpc no 8ch 3 internal internal/lpc no
register and memory mapping 66 datasheet note: 1. only if the port 61 alias-enable bi t (gcs.p61ae) is set?otherwise, none. 5.4.2 variable i/o decode ranges ta b l e 1 3 shows the variable i/o decode ranges. they are set using base address registers (bars) or other configuration bits in the various configuration spaces. the pnp software (pci or acpi) can use its configuration mechanism to set and adjust these values. these values should not be mapped on top of fixed address ranges as unpredictable behavior will result. f a0h 2 8259 slave 8259 slave no a4h 2 8259 slave 8259 slave no a8h 2 8259 slave 8259 slave no ach 2 8259 slave 8259 slave no b0h 2 8259 slave 8259 slave no b2h 2 power management power management no b4h 2 8259 slave 8259 slave no b8h 2 8259 slave 8259 slave no bch 2 8259 slave 8259 slave no 170h 8 pata pata no 1f0h 8 pata pata no 376h 1 pata pata no 3f6h 1 pata pata no cf8h 4 internal internal no cfch 4 internal internal no table 12. fixed i/o decode ranges (sheet 2 of 2) port number size (bytes) read target write target can disable? table 13. variable i/o decode ranges range name mappable size (bytes) target acpi anywhere in 64-k i/o space 64 power management bus master ide anywhere in 64-k i/o space 16 pata smbus anywhere in 64-k i/o space 32 smb unit gpio anywhere in 64-k i/o space 64 gpio unit usb 1 anywhere in 64-k i/o space 32 uhci host controller 1 usb 2 anywhere in 64-k i/o space 32 uhci host controller 2 usb 3 anywhere in 64-k i/o space 32 uhci host controller 3
datasheet 67 register and memory mapping 5.5 i/o mapped registers the intel? sch contains two registers that reside in the processor i/o address space ? the configuration address (config_address) register and the configuration data (config_data) register. the configuration address register enables/disables the configuration space and determines what po rtion of configuration space is visible through the configuration data window. 5.5.1 nsc?nmi status and control register i/o offset (port): 61h attribute: ro, r/w default value: 00h size: 8 bits 5.5.2 nmie?nmi enable register i/o offset (port): 70h attribute: r/w default value: 00h size: 8 bits bit access and default description 7 0 ro serr# nmi status (sns): set on errors from a pcie port or internal functions that generate serr#. sne in this regist er must be cleared in order for this bit to be set. to reset the interrupt, set bit 2 to 1 and then set it to 0. 6 0 ro iochk nmi status (ins): set when serirq asserts iochk# and ine in this register is cleared. to rese t the interrupt, set bit 3 to 1 and then set it to 0. 5 0 ro timer counter 2 status (t2s): reflects the current state of the 8254 counter 2 output. counter 2 must be programmed for this bit to have a determinate value. 4 0 ro refresh cycle toggle status (rts): this signal toggles from 0 to 1 or 1 to 0 at a rate that is equiva lent to when a refresh cycles would occur. 3 0 r/w iochk nmi enable (ine): when set, iochk# nmis are disabled and cleared. when cleared, iochk# nmis are enabled. 2 0 r/w serr# nmi enable (sne): when set, serr# nmis are disabled and cleared. when cleared, serr# nmis are enabled. 1 0 r/w speaker data enable (sde): when this bit is a 0, the spkr output is a 0. when this bit is a 1, the spkr output is equivalent to the counter 2 out signal value. 0 0 r/w timer counter 2 enable (tc2e): when cleared, counter 2 counting is disabled. when set, counting is enabled. bit access and default description 7 0 wo nmi enable (en): 1 = nmi sources disabled. 0 = nmi sources enabled. 6:0 0 wo real time clock index (ridx): selects the rtc register or cmos ram address to access.
register and memory mapping 68 datasheet 5.5.3 config_address?configuration address register i/o offset (port): 0cf8h attribute: ro, r/w default value: 00000000h size: 32 bits config_address is a 32-bit register that can be accessed only as a dw. a byte or word reference will pass through the config uration address register and onto the internal intel? sch backbone as an i/o cycle. the config_address register contains the bus number, device number, function number, and register number for which a subsequent configuration access is intended. bit access and default description 31 r/w 0b configuration enable (cfge): 0 = disable accesses to pci configuration space. 1 = enable accesses to pci configuration space. 30:24 ro 00h reserved 23:16 r/w 00h bus number: if the bus number is programmed to 00h the target of the configuration cycle is a pci bus 0 agent. if this is the case and the intel? sch is not the target (i.e., the device number is 3 and not equal to 7), then a type 0 configuration cycle is generated. if the bus number is non-zero, and does not fall within the ranges enumerated by device 1?s secondary bus number or subordinate bus number register, then a type 1 configuration cycle is generated. this field is mapped to byte 8 [7:0] of the request head er format during pci express configuration cycles and a[23:16] during the type 1 configuration cycles. 15:11 r/w 00h device number: this field selects one agent on the pci bus selected by the bus number. when the bus number field is ?00? the intel? sch decodes the device number field. the intel? sch is always device number 0 for the host bridge entity , device number 1 for the host-pci express entity. therefore, when the bus number =0 and the device number equals 0, 1, 2 or 7 the inte rnal intel? sch devices are selected. this field is mapped to byte 6 [7:3] of the request head er format during pci configuration cycles. 10:8 r/w 000b function number: this field allows the configuration registers of a particular function in a multi-function device to be accessed. the intel? sch ignores configuration cycles to its internal devices if the function number is not equal to 0 or 1. this field is mapped to byte 6 [2:0] of the request head er format during pci configuration cycles. 7:2 r/w 00h register number: this field selects one register within a particular bus, device, and function as specified by the other fields in the configuration address register. this field is mapped to byte 7 [7:2 ] of the request he ader format for during pci configuration cycles. 1:0 ro 00b reserved
datasheet 69 register and memory mapping 5.5.4 rstc?reset control register i/o offset (port): 0cf9h attribute: r/w, ro default value: 00h size: 8 bits 5.5.5 config_data?configu ration data register i/o offset (port): 0cfch attribute: r/w default value: 00000000h size: 32 bits config_data is a 32-bit read/write window into configuration space. the portion of configuration space that is referenced by config_data is determined by the contents of config_address. bit access and default description 7:4 0 ro reserved 3 0 r/w cold reset (cold): this bit will cause a cold reset to the platform, which is performed by driving slpmode low, slprdy# low, and rstrdy# low. in response to this, the platform will perform a full power cycle. 2 0 ro reserved 1 0 r/w warm reset (warm): this bit will cause a warm reset to the platform, which is performed by driv ing rstrdy# low. in response to this, the platform will drive reset# low to reset the processor and all peripherals. 0 0 r/w cpu-only reset (cpu): this bit causes h_cpur st# to be asserted, with processor timing requirements met for minimum pulse width. the processor power-on-config register (h poc) contents will be driven on the host address bus, and latched on the deassertion edge of h_cpurst#. bit access and default description 31:0 r/w 0000 0000h configuration data window (cdw): if bit 31 of the config_address is 1, any i/o access to the config_data register will produce a configuration transaction using the contents of config_address to determ ine the bus, device, function, and offset of the register to be accessed.
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datasheet 71 general chipset configuration 6 general chipset configuration this chapter lists the core registers used to configure the intel? sch chipset. these registers are not specific to any particular in terface or pci configuration space, so they are documented here. there are four groups of registers that meet this description: ? root complex topology capability ? interrupt pin and route definitions ? general configuration the start and end address offsets listed in the following sections are relative to the root complex base address. 6.1 root complex capability the root complex is used by pci express aware operating systems to identify pci express capabilities. it indicates to the os that the intel? sch is capable of isochronous transfers and that an intel hd audio controller exists within the intel? sch. the following registers follow the pci express capability list structure as defined in the pci express specification. table 14. root complex co nfiguration registers address symbol register name 0000?0003h rctcl root complex topology capability list 0004?0007h esd element self description 0010?0013h hdd intel? hd audio descriptor (port 15) 0014?0017h reserved reserved 0018?008fh hdba intel hd audio base address (port 15)
general chipset configuration 72 datasheet 6.1.1 rctcl?root complex to pology capabilities list address offset: 0000h attribute: ro default value: 00010005h size: 32 bits 6.1.2 esd?element self description address offset: 0004h attribute: ro, r/wo default value: 00000102h size: 32 bits bits default and access description 31:20 000h ro next capability (next): this field indicates next item in the list. 19:16 1h ro capability version (cv): this field indicates the version of the capability structure. 15:0 0005h ro capability id (cid): this field indicates this is a pci express link capability section of an rcrb. bits default and access description 31:24 00h ro port number (pn): a value of 0 to indicate the egress port for intel? sch. 23:16 00h r/wo component id (cid): this field indicates the co mponent id assigned to this element by software. this is wr itten once by platform bios and is locked until a platform reset. 15:08 01h ro number of link entries (nle): this field indicates that one link entry (corresponding to intel? hd audi o) is described by this rcrb. 7:4 0 ro reserved 3:0 2h ro element type (et): this field indicates that the element type is a root complex internal link.
datasheet 73 general chipset configuration 6.1.3 hdd?intel? hd audio description address offset: 0010h attribute: ro default value: see description size: 32 bits 6.1.4 hdba?intel? hd audio base address address offset: 0018h attribute: ro default value: 00000000 000d8000h size: 64 bits bits default and access description 31:24 fh ro target port number (pn): this field indicates the target port number is 15 (intel? hd audio). 23:16 init ro target component id (tcid): this field returns the value of the esd.cid field programmed by platform bi os, since the root port is in the same component as the root complex register blocks (rcrb). 15:2 0 ro reserved 1 1 ro link type (lt): this bit indicates that the link points to a root port. 0 1 ro link valid (lv): link is always valid. bits default and access description 63:32 0h ro config space base address upper (cbau): reserved 31:28 0h ro config space base a ddress lower (cbal): reserved 27:20 0h ro bus number (bn): indicates intel? hd audio is on bus 0 19:15 1bh ro device number (dn): indicates intel hd audio is in device 27 14:12 0h ro function number (fn): indicates intel hd audio is in function 0 11:00 0 ro reserved
general chipset configuration 74 datasheet 6.2 interrupt pin and routing configuration configuration of interrupts involves setting both the interrupt pin that a particular device/function should be mapped to, as well as the routing of that pin to the appropriate pirqx signal that ultimately go es to either the pic or apic controller. 6.2.1 interrupt pin configuration the following registers tell each device which interrupt pin to report in the ipin register of their configuration space. each register has one or more 4-bit field assigned to a particular pci function. this 4-bit field is defined as shown in ta b l e 1 5 . table 15. interrupt pin field bit decoding bits pin 0h no interrupt 1h inta# 2h intb# 3h intc# 4h intd# 5h ? fh reserved table 16. interrupt pin register map address symbol register name interface 3100?3103h d31ip device 31 interrupt pin lpc interface 3104?3107h d30ip device 30 interrupt pin sdio/mmc (ports 1-3) 3108?310bh d29ip device 29 interrupt pin usb host (uhci 1-3, ehci) 310c?310fh d28ip device 28 interrupt pin pci express (ports 1 and 2) 3110?3113h d27ip device 27 interrupt pin intel hd audio 3114?3117h d26ip device 26 interrupt pin usb target 3118?311ch d02ip device 2 interrupt pin intel gma 500
datasheet 75 general chipset configuration 6.2.1.1 d31ip?device 31 interrupt pin offset address: 3100h?3103h attribute: r/w, ro default value: 00000210h size: 32 bits 6.2.1.2 d30ip?device 30 interrupt pin offset address: 3104?3107h attribute: r/w, ro default value: 00000321h size: 32 bits 6.2.1.3 d29ip?device 29 interrupt pin offset address: 3108?310bh attribute: r/w, ro default value: 40000321h size: 32 bits 6.2.1.4 d28ip?device 28 interrupt pin offset address: 310c?310fh attribute: r/w, ro default value: 00000021h size: 32 bits bits type reset description 31:4 ro 0 reserved 3:0 ro 0h lpc bridge pin (lip): the lpc bridge does not generate an interrupt. bits type reset description 31:12 ro 0 reserved 11:8 r/w 3h sdio port 2 interrupt pin (sd2): indicates which pin sdio controller 2 uses. 7:4 r/w 2h sdio port 1 interrupt pin (sd1: indicates which pin sdio controller 1 uses. 3:0 r/w 1h sdio port 0 interrupt pin (sd0): indicates which pin sdio controller 0 uses. bits type reset description 31:28 r/w 4h ehci pin (eip): indicates which pin the ehci controller uses. 27:12 ro 0 reserved 11:8 r/w 3h uhci 2 pin (u2p): indicates which pin us b controller 2 uses. 7:4 r/w 2h uhci 1 pin (u1p): indicates which pin us b controller 1 uses. 3:0 r/w 1h uhci 0 pin (u0p): indicates which pin us b controller 0 uses. bits type reset description 31:8 ro 0 reserved 7:4 r/w 2h pci express 2 pin (p2ip): indicates which pin pci express port 2 uses. 3:0 r/w 1h pci express 1 pin (p1ip): indicates which pin pci express port 1 uses.
general chipset configuration 76 datasheet 6.2.1.5 d27ip?device 27 interrupt pin offset address: 3110?3113h attribute: r/w, ro default value: 00000001h size: 32 bits 6.2.1.6 d26ip?device 26 interrupt pin offset address: 3114?3117h attribute: r/w, ro default value: 00000001h size: 32 bits 6.2.1.7 d02ip?device 2 interrupt pin offset address: 3118?311bh attribute: r/w, ro default value: 00000001h size: 32 bits bits type reset description 31:4 ro 0 reserved 3:0 r/w 1h intel hd audio pin (hdaip): indicates which pin the intel? hd audio controller uses. bits type reset description 31:4 ro 0 reserved 3:0 r/w 1h usb target pin (utip): indicates which pin the usb target controller uses. bits type reset description 31:4 ro 0 reserved 3:0 r/w 1h graphics pin (gp): indicates which pin the graphics controller uses for interrupts.
datasheet 77 general chipset configuration 6.2.2 interrupt route configuration the interrupt route configuration registers indicates which pirqx# pin on the intel? sch is connected to the inta/b/c/d pins repo rted in the device x interrupt pin register fields. this will be the internal pin/message the device will generate to either the 8259 interrupt controller or the ioxapic. table 17. interrupt ro ute field bit decoding bits interrupt 0000 pirqa# 0001 pirqb# 0010 pirqc# 0011 pirqd# 0100 pirqe# 0101 pirqf# 0110 pirqg# 0111 pirqh# 1000 ? 1111 reserved table 18. interrupt route register map address symbol register name interface 3140?3141h d31ir device 31 interrupt route lpc interface 3142?3143h d30ir device 30 interrupt route sdio/mmc (ports 1-3) 3144?3145h d29ir device 29 interrupt route usb host (uhci1-3, ehci) 3146?3147h d28ir device 28 interrupt route pci express (ports 1 and 2) 3148?3149h d27ir device 27 interrupt route intel? high definition audio 314a?314bh d26ir device 26 interrupt route usb target 314c?314dh d02ir device 2 interrupt route intel? graphics media accelerator 500
general chipset configuration 78 datasheet 6.2.2.1 d31ir?device 31 interrupt route offset address: 3140-3141h attribute: r/w default value: 3210h size: 16 bits 6.2.2.2 d30ir?device 30 interrupt route offset address: 3142-3143h attribute: r/w default value: 3210h size: 16 bits 6.2.2.3 d29ir?device 29 interrupt route offset address: 3144-3145h attribute: r/w default value: 3210h size: 16 bits bits default and access description 15:12 3h r/w interrupt d pin route (idr): indicates which physic al pin intd# uses for device 31. 11:8 2h r/w interrupt c pin route (icr): indicates which physical pin intc# uses for device 31. 7:4 1h r/w interrupt b pin route (ibr): indicates which physical pin intb# uses for device 31. 3:0 0h r/w interrupt a pin route (iar): indicates which physic al pin inta# uses for device 31. bits default and access description 15:12 3h r/w interrupt d pin route (idr): indicates which physic al pin intd# uses for device 30. 11:8 2h r/w interrupt c pin route (icr): indicates which physical pin intc# uses for device 30. 7:4 1h r/w interrupt b pin route (ibr): indicates which physical pin intb# uses for device 30. 3:0 0h r/w interrupt a pin route (iar): indicates which physic al pin inta# uses for device 30. bits default and access description 15:12 3h r/w interrupt d pin route (idr): indicates which physic al pin intd# uses for device 29. 11:8 2h r/w interrupt c pin route (icr): indicates which physical pin intc# uses for device 29. 7:4 1h r/w interrupt b pin route (ibr): indicates which physical pin intb# uses for device 29. 3:0 0h r/w interrupt a pin route (iar): indicates which physic al pin inta# uses for device 29.
datasheet 79 general chipset configuration 6.2.2.4 d28ir?device 28 interrupt route offset address: 3146-3147h attribute: r/w default value: 3210h size: 16 bits 6.2.2.5 d27ir?device 27 interrupt route offset address: 3148-3149h attribute: r/w default value: 3210h size: 16 bits 6.2.2.6 d26ir?device 26 interrupt route offset address: 314a-314bh attribute: r/w default value: 3210h size: 16 bits bits default and access description 15:12 3h r/w interrupt d pin route (idr): indicates which physical pin intd# uses for device 28. 11:8 2h r/w interrupt c pin route (icr): indicates which physical pin intc# uses for device 28. 7:4 1h r/w interrupt b pin route (ibr): indicates which physical pin intb# uses for device 28. 3:0 0h r/w interrupt a pin route (iar): indicates which physical pin inta# uses for device 28. bits default and access description 15:12 3h r/w interrupt d pin route (idr): indicates which physic al pin intd# uses for device 27. 11:8 2h r/w interrupt c pin route (icr): indicates which physic al pin intc# uses for device 27. 7:4 1h r/w interrupt b pin route (ibr): indicates which physic al pin intb# uses for device 27. 3:0 0h r/w interrupt a pin route (iar): indicates which physical pin inta# uses for device 27. bits default and access description 15:12 3h r/w interrupt d pin route (idr): indicates which physical pin intd# uses for device 26. 11:8 2h r/w interrupt c pin route (icr): indicates which physical pin intc# uses for device 26. 7:4 1h r/w interrupt b pin route (ibr): indicates which physical pin intb# uses for device 26. 3:0 0h r/w interrupt a pin route (iar): indicates which physic al pin inta# uses for device 26.
general chipset configuration 80 datasheet 6.2.2.7 d02ir?device 2 interrupt route offset address: 314c-314dh attribute: r/w default value: 3210h size: 16 bits 6.3 general configuration register 6.3.1 rc?rtc configuration register offset address: 3400?3403h attribute: ro, r/wlo default value: 00000000h size: 32-bit bits default and access description 15:12 3h r/w interrupt d pin route (idr): indicates which physic al pin intd# uses for device 2. 11:8 2h r/w interrupt c pin route (icr): indicates which physical pin intc# uses for device 2. 7:4 1h r/w interrupt b pin route (ibr): indicates which physic al pin intb# uses for device 2. 3:0 0h r/w interrupt a pin route (iar): indicates which physic al pin inta# uses for device 2. bit default and access description 31:3 0000000h ro reserved 2 0b r/wlo reserved 1 0 r/wlo upper 128-byte lock (ul): when set, bytes 38h ?3fh in the upper 128-byte bank of rtc ram are locked. writes will be ignored and reads will not return any ensured data. 0 0 r/wlo lower 128-byte lock (ll): when set, bytes 38h?3fh in the lower 128-byte bank of rtc ram are locked. writes will be ignored and reads will not return any ensured data.
datasheet 81 host bridge (d0:f0) 7 host bridge (d0:f0) 7.1 functional description the host bridge logic manages many of the intel? sch central functions most specifically the fsb controller, memory controller, and thermal and power management. the host bridge contains all the registers ne cessary to configure these functions. these registers are organized into two groups, each with its own method of access: 1. pci configuration space. these registers are accessed using the standard pci cycle methodology. 2. custom register space. these registers are accessed through two specific pci configuration registers, and they are used to issue messages onto the intel? sch internal message network. 7.1.1 dynamic bus inversion when the processor or the intel? sch drives data, each 16-bit segment is analyzed. if more than 8 of the 16 signals would no rmally be driven low on the bus the corresponding h_dinv# signal will be asserted and the data will be inverted prior to being driven on the bus. conversely, wh enever the processor or the intel? sch receives data, it monitors h_dinv[3:0]# to determine if the corresponding data segment should be inverted. 7.1.2 fsb interrupt overview the processor supports fsb interrupt delivery. it does not support the apic serial bus interrupt delivery mechanism. interrupt-related messages are encoded on the fsb as ?interrupt message transactions?. fsb interrupts may originate from a device part of, or attached to, the intel? sch, such as a usb controller or the intel graphics media accelerator 500. in such a case the intel? sch drives the ?interrupt message transaction? onto the fsb. in the ioxapic environment, an interrupt is generated from the intel? sch ioxapic to the processor in the form of a memory wr ite to the fsb. furthermore, the pci 2.3 specification and pci express specification de fine msis (message signaled interrupts) that also take the form of memory writes. msi-capable devices, such as pci express or usb, may generate an interrupt using th e msi mechanism, writing the interrupt message directly to the fsb. alternatively, an interrupt message transaction can be directed to the ioxapic which in turn routes the interrupt message to the fsb using the traditional ioxapic interrupt memory write method. the target of an msi transaction is dependent upon the target address of the interrupt memory write. caution: improperly formed msis, including any non-dword writes to the space reserved for msi, may cause unexpected system behavior.
host bridge (d0:f0) 82 datasheet 7.1.3 cpu bist strap to enter cpu bist, software first sets the pm sw.cbe (bist enable) bit, and then does a warm reset by writing to rstc.warm. th e bist strap sequence is as follows: ? as part of the boot sequence, the power management controller will check whether pmsw.cbe has been set. if so, it will set the state of the bist bit in the poc vector accordingly. ? the power management controller prepares the full poc vector and writes it to the hpoc register internally. these values are driven onto the ha[31:3] and init# pins. ? cpurst# is deasserted to the processor after ensuring that at least 4 host bus clocks have elapsed after driving poc. ? poc pins all take their normal usage two host clocks after cpurst# deassertion. 7.2 host pci configuration registers note: address locations that are not shown should be treated as reserved. 7.2.1 vid?identification register offset: 00h ? 01h attribute: ro default value: 8086h size: 16 bits table 19. host bridge configur ation register address map offset mnemonic register name default type 00h?01h vid vendor id 8086 ro 02h?03h did device id 8100-8107 ro 04h?05h pcicmd pci command 0007h r/w, ro 06h?07h pcists pci status 0280h r/wc, ro 08h rid revision id see description ro 0ah?0bh cc class codes 0805h ro 2ch?2fh ss subsystem identifiers see description ro bit default and access description 15:0 8086h ro vendor id (vid): pci standard identification for intel.
datasheet 83 host bridge (d0:f0) 7.2.2 did?identification register offset: 02h ? 03h attribute: ro default value: 810xh size: 16 bits 7.2.3 pcicmd?pci command register offset: 04h ? 05h attribute: r/w, ro default value: 0007h size: 16 bits 7.2.4 pcists?pci status register offset: 06h ? 07h attribute: ro default value: 0000h size: 16 bits 7.2.5 rid?revision identification register offset address: 08h attribute: ro default value: tbd size: 8 bits bit default and access description 15:0 8100- 8107h ro device id (did): this is a 16-bit value assigned to the controller. refer to the intel? sch specification upda te for the did for various product sku. bit default and access description 15:3 0 ro reserved 2 1 ro bus master enable (bme): the intel? sch is always enabled as a bus master. 1 1 ro memory space enable (mse): the intel? sch is always allowed to access memory. 0 1 ro i/o access enable (ioae): the memory controller always allows access to i/o. bit default and access description 15:0 0000h ro reserved bit default and access description 7:0 tbd ro revision id: this value is tied to the value in the lpc bridge (device 31, function 0).
host bridge (d0:f0) 84 datasheet 7.2.6 cc?class co de register offset: 0ah?0bh attribute: ro default value: 0600h size: 16 bits 7.2.7 ss?subsystem identifiers register offset: 2ch?2fh attribute: ro default value: 00000000h size: 32 bits bit default and access description 15:8 06h ro base class code (bcc): 06h indicates a bridge device. 7:0 00h ro sub class code (scc): 00h indicates a host bridge. bit default and access description 31:16 ro subsystem id (ssid) 15:0 ro subsystem vendor id (svid)
datasheet 85 host bridge (d0:f0) 7.2.7.1 ttb?thermal trip behavior register offset: b6h attribute: ro, r/w, r/wlo default value: 00000000h size: 32 bits (sheet 1 of 2) bit default and access description 31 0 r/w internal thermal hardware throttling enable bit (ithte): this is a master enable for internal thermal sensor-based hardware throttling. interrupts are not affected by this bit. this is for hot trip throttling only. 30:28 000b ro reserved 27:26 00b r/w catastrophic shutdown select (css): chooses which option to take upon a catastrophic thermal event. 25 0 r/wlo reserved 24 0 r/w prochot# enable (phe): when this bit is set, prochot# is asserted on aux2 trip. 0 = prochot# is not asserted 1 = prochot# can be asserted on aux2 trip prochot# pulse width has a minimum duration of 500 s to meet the processor specifications. 23 0 r/w smi on extts1# thermal sensor trip (sme1t): 1 = smi is generated on an ex ternal thermal sensor 1 trip. 22 0 r/w smi on extts0# thermal sensor trip (sme1t): 1 = smi is generated on an ex ternal thermal sensor 0 trip. 21 0 ro reserved bit definition 00 no external assertions?internal hardware throttling only. 01 power-down immediately : slprdy#, slpmode, and rstrdy# are all driven to 0s within 100 s. this powers off the platform. a system reboot is required. this is the lowest-latency option. 10 request s5: slprdy# is asserted after s5-ready; powers off the platform afte r sleep-readiness ha s been checked by the intel? sch. a system reboot is required. once the trip point is reached, slprdy# stay s asserted even if the trip deasserts before the platform is shut down. this has the longest latency, but allows for transactions to finish so as to avoid data from being lost/corrupted. however, there is still no assurance of corruption prevention, as functionality to enter s5 is not ensured in the temperature region where ca tastrophic trip is normally reserved 11 reserved
host bridge (d0:f0) 86 datasheet 20 0 r/w smi on hot trip (smht): 1 = smi is generated on a hot trip. 19 0 r/w smi on aux3 trip (sma3t): 1 = smi is generated on an aux3 trip. 18 0 r/w smi on aux2 trip (sma2t): 1 = smi is generated on an aux2 trip. 17 0 r/w smi on aux1 trip (sma1t): 1 = smi is generated on an aux1 trip. 16 0 r/w smi on aux0 trip (sma0t): 1 = smi is generated on an aux0 trip. 15 0 r/w sci on extts1# thermal sensor trip (sce1t): 1 = sci is generated on an ex ternal thermal sensor 1 trip. 14 0 r/w sci on extts0# thermal sensor trip (sce1t): 1 = sci is generated on an ex ternal thermal sensor 1 trip. 13 0 ro reserved 12 0 r/w sci on hot tr ip (scht): 1 = sci is generated on a hot trip. 11 0 r/w sci on aux3 trip (sca3t): 1 = sci is generated on an aux3 trip. 10 0 r/w sci on aux2 trip (sca2t): 1 = sci is generated on an aux2 trip. 9 0 r/w sci on aux1 trip (sca1t): 1 = sci is generated on an aux1 trip. 8 0 r/w sci on aux0 trip (sca0t): 1 = sci is generated on an aux0 trip. 7:0 0 ro reserved (sheet 2 of 2) bit default and access description
datasheet 87 host bridge (d0:f0) 7.2.7.2 exttscs?external thermal se nsor control and status register offset: b7h attribute: ro, r/wlo default value: 00000000h size: 32 bits 7.2.7.3 tsiu[0,1,2,3,4]?thermal sensor in use register [0,1,2,3,4] offset: tsiu0 = c0h attribute: ro, rs/wc tsiu1 = c1h tsiu2 = c2h tsiu3 = c3h tsiu4 = c4h default value: 00000000h size: 32 bits. bit default and access description 31:6 0000000h ro reserved 7 0 r/wlo extts1 enable (exe1): 1 = indicates extts1 is wired and conf igured for external thermal sensor input. 6:4 0 r/wlo reserved 3 00b r/wlo extts0 enable (exe0): 1 = indicates extts0 is wired and conf igured for external thermal sensor input. 2:0 00b r/wlo reserved bit default and access description 31:1 00000000h ro reserved 0 0 rs/wc in use bit iu[0..4]: after a full intel? sch re set, a read to this bit returns a 0. after the firs t read, subsequent reads wi ll return a 1. a write of a 1 to this bit will reset the next read value to 0. writing a 0 to this bit has no effect
host bridge (d0:f0) 88 datasheet 7.2.8 miscellaneo us (port 05h) port 05h contains configuration and status registers that don?t specifically belong to other ports or interfaces. 7.2.8.1 msr?mode and status register offset: 03h attribute: ro default value: 0000000uh size: 32 bits. bit default and access description 31:4 0000000h ro reserved 3 - ro core clock frequency: this bit indicates the frequency of the core clock and the fsb and memory interface frequencies. 0 = 100-mhz core clock, 400-mt/s fsb, 400-mt/s ddr 1 = 133-mhz core clock, 533-mt/s fsb, 533-mt/s ddr 2:0 - ro graphics frequency: this bit indicates the fr equency for the graphics core clock. 100 = 200 mhz others = reserved
datasheet 89 memory controller (d0:f0) 8 memory controller (d0:f0) 8.1 functional overview 8.1.1 dram frequencies and data rates to reduce design complexity and clock ne twork power, the intel? sch maintains a fixed relationship to the fsb clock freque ncy. the fsb frequency can be 100 mhz or 133 mhz, resulting in support of the follow ing clock frequencies and data rates for dram. 8.1.2 dram command scheduling the intel? sch memory controller operates at the common core clock, which is one half the ddr2 memory clock frequency, or ? the ddr data rate. to provide efficient scheduling, the controller is capable of sched uling two operations in the controller core clock to be able to issue a command ever y memory clock (where scheduling rules for the memory devices allow). the memory controller operates on up to two requests at a time to provide pipelining for memory commands where possible. it will issue page management commands (activates and precharges) out of order for the later request, but will always service reads and writes (cas operations) in the order in which they were received by the controller. this provides efficient schedulin g while still maintaining in-order rules for compatibility with the fsb ioq. the intel? sch never uses any additive latency, which is provided for in ddr2 to create a posted cas effect and improve scheduling efficiency in some memory systems. 8.1.3 page management the memory controller is capable of closing open pages after the pages have been idle for a configurable period of time. this benefits the system for both power and performance (when properly configured). from a performance standpoint, it helps since it can reduce the number of page misses encountered. from a power perspective, it allows the memory devices to reach the precharge power management state (power down when all banks are closed), which has better power saving characteristics on most memory devices than when the pages are left open and the device is in powered down. fsb clock dram clock dram data rate dram type peak bandwidth 100 mhz 200 mhz 400 mt/s ddr2 3.2 gb/s 133 mhz 266 mhz 533 mt/s ddr2 4.2 gb/s
memory controller (d0:f0) 90 datasheet pages that close due to timeout can do so in one of two ways: ? when one or more (but not all) pages in a given rank time out, the pages that have timed out will close provided the rank is awak e and timing rules allow. if the rank is powered down, it will be powered up to service individual page closures only if configured to do so. this is not the default behavior; however, this is primarily a performance benefit and can adversely effect power consumption. ? when all of the open pages in a rank have timed out, the memory controller will power up to service page closures. note: there is generally a significant power savi ngs by entering the pre-charge powerdown state versus the active powerdown state th at is used by the memory devices when pages are still open. note: up to 16 banks can be independently trac ked by the intel? sch memory controller. 8.2 dram technologies and organization for the intel? sch, 512-mb, 1-gb and 2-gb technologies and addressing are supported for x16 devices. the dram sub-sy stem supports a single-channel, 64-bits wide, with one or two ranks. 8.2.1 dram address mapping system addresses are decoded by the memory controller to map to the rank, bank, row, and column physical address locations in the populated drams. 8.2.1.1 dram device address decode for any rank, the address range it implements is mapped into the physical address regions of the devices on that rank. this is addressable by bank (b), row (r), and column (c) addresses. once a rank is selected as described above, the range that it is implementing is mapped into the device ?s physical address as described in ta b l e 2 1 . table 20. dram attributes device size width page size banks bank addr row addr col addr 512 mb x8 1kb 4 ba0-ba1 a0-a13 a0-a9 1024 mb x8 1kb 8 ba0-ba2 a0-a13 a0-a9 2048 mb x8 1kb 8 ba0-ba2 a0-a14 a0-a9 512 mb x16 2kb 4 ba0-ba1 a0-a12 a0-a9 1024 mb x16 2kb 8 ba0-ba2 a0-a12 a0-a9 2048 mb x16 2kb 8 ba0-ba2 a0-a13 a0-a9
datasheet 91 memory controller (d0:f0) note: r = row address bit. c = column address bit. b = bank select bit (sm_bs[2:0]). table 21. dram address decoder topic device density 512 mb 512 mb 1024 mb 1024 mb 2048mb 2048mb x16 x8 x16 x8 x16 x8 rank size 256 mb 512 mb 512 mb 1024 mb 1024mb 1024mb bank bits223333 row bits 13 14 13 14 14 15 col bits 10 10 10 10 10 10 a31?????? a30?????r14 a29 ? ? ? r13 r13 r13 a28?r13b2b2b2b2 a27r12r12r12r12r12r12 a26r11r11r11r11r11r11 a25r10r10r10r10r10r10 a24r9r9r9r9r9r9 a23r8r8r8r8r8r8 a22r7r7r7r7r7r7 a21r6r6r6r6r6r6 a20r5r5r5r5r5r5 a19r4r4r4r4r4r4 a18b1b1b1b1b1b1 a17c9c9c9c9c9c9 a16r3r3r3r3r3r3 a15r2r2r2r2r2r2 a14r1r1r1r1r1r1 a13r0r0r0r0r0r0 a12b0b0b0b0b0b0 a11c8c8c8c8c8c8 a10c7c7c7c7c7c7 a9 c6 c6 c6 c6 c6 c6 a8 c5 c5 c5 c5 c5 c5 a7 c4 c4 c4 c4 c4 c4 a6 c3 c3 c3 c3 c3 c3 a5 c2 c2 c2 c2 c2 c2 a4 c1 c1 c1 c1 c1 c1 a3 c0 c0 c0 c0 c0 c0
memory controller (d0:f0) 92 datasheet 8.3 dram clock generation the intel? sch contains two differential clock pairs (sm_ck[1:0]/sm_ck[1:0]#) that are used to support as many as two ranks of memory on the system board. 8.4 ddr2 on-die termination the intel? sch memory controller interface was designed to operate properly without on-die termination. this has resulted is significant power savings, both within the system and within the intel? sch. the inte l? sch contains features to reduce power consumption in the event sstl termin ation is used within the system. 8.5 dram power management the intel? sch supports memory power ma nagement in the following conditions: ? c0?c1: cke powerdown ? c2?c6: dynamic self-refresh ? s3: self-refresh 8.5.1 cke powerdown the memory controller employs aggressi ve use of memory power management features. when a rank is not being accessed, the cke for that rank is deasserted, bringing the devices into either an active or precharge powerdown state depending on whether any pages are still open in the device. ddr2 supports slow or fast exit from active powerdown. these options must be configured in the memory devices themselves by bios before memory accesses begin. the slower exit improves power savings when in a low power state but comes at a high latency cost. due to the latency cost this can in some cases have the effect of increasing power consumption if the memory subsystem frequently has to suffer this delay and is consuming full power on the i/o interface in the process. the intel? sch will not use the slower exit, opting instead to use the active powerdown as a lighter powerdown mode, but employing page close ti mers to get to a more power efficient precharge powerdown state when the pages in the rank have been idle for the configured time. 8.5.2 interface high-impedance although the intel? sch is designed to oper ate properly with no sstl termination, it provides power saving mechanisms to reduce power consumption if sstl termination is used. to save power on an sstl-terminated ddr2 interface, any output signals that are not needed for proper memory operation at that time should be tristated (floated). this is due to the sstl termination topology which is center-terminated and thus consumes power whenever a signal is driven high or low. ? when both ranks are powered down, address and command pins are tristated. ? address and command signals are only enabled when a chip select is asserted, floating these signals at all other times. ? when a rank is powered down, the corre sponding sm_cs# pins are tristated. ? data and strobe signals are floated. this occurs whenever the data and strobe are not actively transferring write data (or issuing a preamble or postamble on the strobes). ? the sm_ck/sm_ck# signals are floated wh enever both ranks ar e in self refresh. ? static disabling is available for preventing unused signals from ever driving. this is provided for sm_bs[2:0], sm_ma[14:13], sm_ck[1:0]/sm_ck[1:0]#, sm_cke[1:0].
datasheet 93 memory controller (d0:f0) 8.5.3 refresh the intel? sch handles all dram refresh oper ations when the device is not in self- refresh. to reduce the performance impact of dram refreshes, the intel? sch waits until eight refreshes are required and then issues all of these refreshes. this provides some increase in efficiency (overall lower percentage of impact to the available bandwidth), but there will also be a longer period of time that the memory will be unavailable, roughly 8 x t rfc . 8.5.4 self-refresh self-refresh can be entered to save powe r on the memory device and intel? sch power to drive the ddr2 differential clock si gnals. when the memory is in self-refresh, the intel? sch disables all output signals, except the sm_cke signals. the intel? sch will enter self refresh as part of the suspend (s3) sequence. it stays in this the self-refresh state until a resume sequence is initiated. 8.5.5 dynamic self-refresh in addition, the intel? sch can support dyna mic self-refresh in c2?c6 states. it wakes the memory from self-refresh state whenever memory access is needed, then re-enter self-refresh state as soon as there are no more requests are needed. 8.5.6 ddr2 voltage the intel? sch supports 1.8-v and 1.5-v ddr2 memory. note: 1.5-v ddr2 support is restricted to single rank operation.
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datasheet 95 graphics, video, and display (d2:f0) 9 graphics, video, and display (d2:f0) 9.1 graphics overview 9.1.1 3-d core key features two pipe scaleable unified shader implementation. ? 3-d peak performance ? fill rate: 2 pixels per clock ? vertex rate: one triangle 15 clocks (transform only) ? vertex/triangle ratio average = 1 vtx/tri, peak 0.5 vtx/tri ? texture max size = 2048 x 2048 ? programmable 4x multi-sa mpling anti-aliasing (msaa) ?rotated grid ? isp performance related to aa mode, tsp performance unaffected by aa mode ? optimized memory efficiency using multi-level cache architecture 9.1.2 shading engine key features the unified pixel/vertex shader engine supports a broad range of instructions. ? unified programming model ? multi-threaded with four concurrently running threads ? zero-cost swapping in/out of threads ? cached program execution model ? unlimited program size ? dedicated pixel processing instructions ? dedicated vertex processing instructions ? 2048 32-bit registers ? simd pipeline supporting operations in: ? 32-bit ieee float ? 2-way, 16-bit fixed point ? 4-way, 8-bit integer ? 32-bit, bit-wise (logical only) ? static and dynamic flow control ? subroutine calls ? loops ? conditional branches ? zero-cost instruction predication ? procedural geometry ? allows generation of more primitives on output compared with input data ? effective geometry compression ? high order surface support ? external data access ? permits reads from main memory by cache (can be bypassed) ? permits writes to main memory ? data fence facility provided ? dependent texture reads
graphics, video, and display (d2:f0) 96 datasheet 9.1.3 vertex processing modern graphics processors perform two main procedures to generate 3-d graphics. first, vertex geometry information is transformed and lit to create a 2-d representation in the screen space. those transformed and lit vertices are then processed to create display lists in memory. the pixel processor then rasterizes these display lists on a regional basis to create the final image. the intel gma 500 supports dma data accesses from sdram. dma accesses are controlled by a main scheduler and data sequencer engine. this engine coordinates the data and instruction flow for the vertex processing, pixel processing, and general purpose operations. transform and lighting operations are perfor med by the vertex processing pipeline. a 3-d object is usually expressed in terms of tr iangles, each of which is made up of three vertices defined by x?y?z coordinate space. the transform and lighting process is performed by processing data through the unified shader core. the results of this process are sent to the pixel processing function. the steps to transform and light a triangle or vertex are explained below. 9.1.3.1 vertex transform stages ? local space : relative to the model itself (e.g., using the model centre at reference point). prior to being placed in to a scene with other objects. ? world space : transform local to world: this is needed to bring all objects in the scene together into a common coordinate system. ? camera space : transform world to camera (also called eye): this is required to transform the world in order to align it with camera view. in opengl the local to world and world to camera transformation matrix is combined into one, called the modelview matrix. ? clip space : transform camera to clip: the proj ection matrix defines the viewing frustum onto which the scene will be projected. projection can be orthographic, or perspective. clip is used because clipping occurs in clip space. ? perspective space : transform clip to perspective: the perspective divide is basically what enables 3-d objects to be projected onto a 2-d space. a divide is necessary to represent distant objects as smaller on the screen. coordinates in perspective space are called normalized device coordinates ([-1,1] in each axis). ? screen space : transform perspective to screen: this is where 2-d screen coordinates are finally computed, by sca ling and biasing the normalized device coordinates according to the required render resolution. 9.1.3.2 lighting stages lighting is used to generate modifications to the base color and texture of vertices; examples of different types of lighting are: ? ambient lighting is constant in all directions an d the same color to all pixels of an object. ambient lighting calculations are fast, but objects appear flat and unrealistic. ? diffuse lighting takes into account the light direction relative to the normal vector of the object?s surface. calculating diffuse lighting effects takes more time because the light changes for each object vertex , but objects appear shaded with more three-dimensional depth. ? specular lighting identifies bright reflected high lights that occur when light hits an object surface and reflects back toward the camera. it is more intense than diffuse light and falls off more rapidly across the obje ct surface. although it takes longer to calculate specular lighting than diffuse lig hting, it adds significant detail to the surface of some objects. ? emissive lighting is light that is emitted by an object, such as a light bulb.
datasheet 97 graphics, video, and display (d2:f0) 9.1.4 pixel processing after vertices are transformed and lit by the vertex processing pipeline, the pixel processor takes the vertex information and generates the final rasterized pixels to be displayed. the steps of this process include removing hidden surfaces, applying textures and shading, and converting pixels to the final display format. the vertex/pixel shader engine is described in section 9.1.5 . the pixel processing operations also have their own data scheduling function that controls image processor functions and the texture and shader routines. 9.1.4.1 hidden surface removal the image processor takes the floating-point results of the vertex processing and further converts them to polygons for rasterization and depth processing. during depth processing, the relative positions of objects in a scene, relative to the camera, are determined. the surfaces of objects hidde n behind other objects are then removed from the scene, thus preventing the proce ssing of un-seen pixels. this improves the efficiency of subsequent pixel-processing. 9.1.4.2 applying textures and shading after hidden surfaces are removed, textures and shading are applied. texture maps are fetched, mipmaps calculated, and either is applied to the polygons. complex pixel- shader functions are also applied at this stage. 9.1.4.3 final pixel formatting the pixel formatting module is the final stage of the pixel-processing pipeline and controls the format of the final pixel data sent to the memory. it supplies the unified shader with an address into the output buffer, and the shader core returns the relevant pixel data. the pixel formatting module also contains scaling functions, as well as a dithering and data format packing function. 9.1.5 unified shader the unified shader engine contains a spec ialized programmable microcontroller with capabilities specifically suited for efficien t processing of graphics geometries (vertex shading), graphics pixels (pixel shading), and general-purpose video and image processing programs. in addition to data processing operations, the unified shader engine has a rich set of program-control functions permitting complex branches, subroutine calls, tests, etc., for run-time program execution. the unified shader core also has a task an d thread manager which tries to maintain maximum performance utilization by using a 16-deep task queue to keep the 16 threads full. the unified store contains 16 banks of 128 registers. these 32-bit registers contain all temporary and output data, as well as attribute information. the store employs features which reduce data collisions such as data forwarding, pre-fetching of a source argument from the subsequent instruction. it also contains a write back queue. like the register store, the arithmetic logic unit (alu) pipelines are 32-bits wide. for floating-point instructions, these correlate to ieee floating point values. however, for integer instructions, they can be considered as one 32-bit value, two 16-bit values, or four 8-bit values. when considered as four 8-bit values, the integer unit effectively acts like a four-way simd alu, performing four operations per clock. it is expected that in legacy applications pixel processing will be done on 8-bit integers, roughly quadrupling the pixel throughput compared to processing on float formats.
graphics, video, and display (d2:f0) 98 datasheet 9.1.6 multi level cache the multi-level cache is a three-level cache sy stem consisting of two modules, the main cache module and a request management and formatting module. the request management module also provides level-0 caching for texture and unified shader core requests. the request management module can accept requests from the data scheduler, unified shaders and texture modules. arbitratio n is performed betw een the three data streams, and the cache module also performs any texture decompression that may be required. 9.2 video decode overview the video decode accelerator improves video performance/power by providing hardware-based acceleration at the macrob lock level (variable length decode stage entry point). the intel? sch supports full hardware acceleration of the following video decode standards. the video decode function is performed in four processing modules: ? entropy coding processing ? motion compensation ? deblocking ? final pixel formatting table 22. hardware-accelerated video codec support codec profile level note h.264 baseline profile l3 h.264 main profile l4.1 (1080i @ 30fps) (1080p @ 24fps) h.264 high profile l4.1 (1080i @ 30fps) (1080p @ 24fps) mpeg2 main profile high mpeg4 simple profile l3 mpeg4 advanced simple profile l5 vc1 simple profile medium vc1 main profile high vc1 advanced profile l3 up to (1080i @ 30fps) (1080p @ 24fps) wmv9 simple profile medium wmv9 main profile high
datasheet 99 graphics, video, and display (d2:f0) 9.2.1 entropy coding the entropy encoding module serves as the master controller for the video accelerator. the master data stream control and bitstream parsing functions for the macroblock level and below are performed here. required control parameters are sent to the motion compensation and deblocking modules. the macroblock bitstream parsing performs the entropy encoding functions for vlc, calvc, and cabac techniques used in video codecs. the entropy encoding module also performs the motion vector reconstruction using the motion vector predictors. after entropy encoding, the idct coefficien ts are extracted and inverse scan ordered. then inverse quantization, rescaling, and ac/dc coefficient processing is performed. the re-scaled coefficients are passed to the inverse transform engine for processing. the hadamard transform is also supp orted and performed here. the inverse- transformed data is connected to the outp ut port of entropy coding module, which provides the residual data to the motion compensation module. 9.2.2 motion compensation the entropy encoder or host can writes a se ries of commands to define the type of motion predication used. the motion predicat ed data is then combined with residual data, and the resulting reconstructed data is passed to the de-blocker. the motion compensation module is made-up of four sub-modules: ? the module control unit module controls the overall motion compensation operation. it parses the command stream to detect errors in the commands sent, and extracts control parameters for use in later parts of the processing pipeline. the module control unit also accepts residual data (either direct from vec or by a system register), and re-orders the frame/field format to match the predicted tile format. ? the reference cache module accepts the inter/intra prediction commands, along with the motion vectors and index to reference frame in the case of inter prediction. the module calculates the locati on of reference data in the frame store (including out-of-bounds processing requirements). the module includes cache memory which is checked before extern al system memory reads are requested (the cache can significantly reduce syst em memory bandwidth requirements). in h264 mode, the module also extracts and stores intra boundary data which is used in intra prediction. the output of the reference cache is passed to the 2-d filter module. ? the 2-d filter module implements up to 8-tap vertical and horizontal filters to generate predicted data for sub-pixel motion vectors (to a resolution of up-to 1/8th of a pixel). the 2-d filter module also generates h264 intra prediction tiles (based on the intra prediction mode and bound ary data extracted by the reference cache). for vc1 and wmv9, the 2-d filter module also implements range scaling and intensity compensation on inter reference data prior to sub-pixel filtering. ? the pixel reconstruction unit combines predicted data from the 2-d filter with the re-ordered residual data from the module control unit. in the case of bi-directional macroblocks with two motion vectors pe r tile, the pixel reconstruction unit combines the two tiles of predicted data pr ior to combining the result with residual data. in the case of h264, the pixel recons truction unit also implements weighted averaging. the final reconstructed data is then passed to the vdeb for de-blocking (as well as being fed-back to reference ca che so that intra boundary data can be extracted).
graphics, video, and display (d2:f0) 100 datasheet 9.2.3 deblocking the deblocking module is responsible for codec back-end video filtering. it is the last module within the high definition video decoder module pipeline. the deblocking module performs overlap filtering and in-loop deblocking of the reconstructed data generated by the motion-compensation module. the frames generated are used for display and for reference of subsequent decoded frames. the deblocking module performs the following specific codec functions: ? h.264 deblocking, including aso modes ? vc-1/wmv9 overlap filter and in-loop deblocking ? range-mapping ? pass-through of reconstructed data for codec-modes that don?t require deblocking (mpeg2, mpeg4). 9.2.4 output reference frame storage format interlaced pictures (as opposed to progressive pictures) are always stored in system memory as interlaced frames, including interlaced field pictures. 9.2.4.1 pixel format the pixel format has the name 420pl12yuv8. th is consists of a single plane of luma (y) and a second plane consisting of interleaved cr/cb (v/u) components. for 420pl12yuv8, the number of chroma samples is a quarter of the quantity of luma samples ? half as many vertically, half as many horizontally. table 23. pixel format for the luma (y) plane bit symbol description 63:56 y7[7:0] 8-bit y luma component 55:48 y6[7:0] 8-bit y luma component 47:40 y5[7:0] 8-bit y luma component 39:32 y4[7:0] 8-bit y luma component 31:24 y3[7:0] 8-bit y luma component 23:16 y2[7:0] 8-bit y luma component 15:8 y1[7:0] 8-bit y luma component table 24. pixel formats for the cr/cb (v/u) plane (sheet 1 of 2) bit symbol description format 1 7:0 y0[7:0] 8-bit y luma component 63:56 u3[7:0] 8-bit u/cb chroma component 55:48 v3[7:0] 8-bit v/cr chroma component 47:40 u2[7:0] 8-bit u/cb chroma component 39:32 v2[7:0] 8-bit v/cr chroma component 31:24 u1[7:0] 8-bit u/cb chroma component 23:16 v1[7:0] 8-bit v/cr chroma component 15:8 u0[7:0] 8-bit u/cb chroma component 7:0 v0[7:0] 8-bit v/cr chroma component
datasheet 101 graphics, video, and display (d2:f0) 9.3 display overview the intel? sch display output ca n be divided into three stages: ?planes ? request/receive data from memory ? format memory data into pixels ? handle fragmentation, tiling, physical address mapping ?pipes ? generate display timing ? scaling, lut ?ports ? format pixels for output (sdvo, lvds) ? interface to physical layer 9.3.1 planes the intel? sch contains a variety of planes (such as, display and cursor). a plane consists of rectangular shaped image that has characteristics (such as, source, size, position, method, and format). these planes get attached to source surfaces, which are rectangular areas in memory with a similar set of characteristics. they are also associated with a particular destination pipe. ? display plane - the primary and second ary display plane works in an indexed mode, hi-color mode or a true color mode. the true color mode allows for an 8-bit alpha channel. one of the primary operations of the display plane is the set mode operation. the set-mode operation occurs when it is desired to enable a display, change the display timing, or source fo rmat. the secondary display plane can be used as a primary surface on the secondary display or as a sprite planes on either the primary or secondary display. ? cursor plane - the cursor plane is one of the simplest display planes. with a few exceptions, the cursor plane supports sizes of 64 x 64, 128 x 128 and 256 x 256 fixed z-order (top). in legacy modes, cursor can cause the display data below it to be inverted. ? vga plane - vga mode provides compatibility for pre-existing software that set the display mode using the vga crtc registers. vga timings are generated based on the vga register values (the hi-resolution timing generator registers are not used). note: the intel? sch has limited support for a vga plane. the vga plane is suitable for usages such as bios boot screens, pre-os splash screens, etc. other usages of the vga plane (like dos-based games, for example) are not supported. format 2 (cr and cb are reversed relative to format 1) 63:56 v3[7:0] 8-bit u/cr chroma component 55:48 u3[7:0] 8-bit v/cb chroma component 47:40 v2[7:0] 8-bit u/cr chroma component 39:32 u2[7:0] 8-bit v/cb chroma component 31:24 v1[7:0] 8-bit u/cr chroma component 23:16 u1[7:0] 8-bit v/cb chroma component 15:8 v0[7:0] 8-bit u/cr chroma component 7:0 u0[7:0] 8-bit v/cb chroma component table 24. pixel formats for the cr/cb (v/u) plane (sheet 2 of 2) bit symbol description
graphics, video, and display (d2:f0) 102 datasheet 9.3.2 display pipes the display consists of two pipes: ? display pipe a ? display pipe b a pipe consists of a set of combined pl anes and a timing generator. the timing generators provide timing information for ea ch of the display pipes. the intel? sch has two independent display pipes, allowing for support of two independent display streams. a port is the destination for the result of the pipe. pipe a can operate in a single-wide mode. the clock generator units (dplla and dpllb ) provide a stable frequency for driving display devices. it operates by converting an input reference frequency into an output frequency. the timing generators take their input from internal dpll devices that are programmable to generate pixel clocks in the range of 20 mhz?180 mhz. 9.3.3 display ports display ports are the destination for the display pipe. these are the places where the display data finally appears to devices outs ide the graphics device. the intel? sch has one dedicated lvds port and one sdvo port. since the intel? sch has two display ports available for its two pipes, it can support up to two different images on two different di splay devices. timings and resolutions for these two images may be different. 9.3.3.1 lvds port display pipe b supports output to the lvds display port. the lvds port is programmed with the panel timing parameters that are de termined by installed panel specifications or read from an onboard edid rom. the programmed timing values are then locked into the registers to prevent unwanted corruption of the values. from that point on, the display modes are changed by selecting a different source size for that pipe, programming the vga registers, or selectin g a source size and enabling the vga. the timing signals will remain stable and active through mode changes. these mode changes include vga to vga, vga to hires, hires to vga, and hires to hires. the transmitter can operate in a variety of modes and supports several data formats. the serializer supports 6-bit or 8-bit color per lane (for 18-bit and 24-bit color respectively) and single-channel operating mo des. the display stream from the display pipe is sent to the lvds transmitter port at the dot clock frequency, which is determined by the panel timing requirements. the output of lvds is running at a fixed multiple of the dot clock frequency. the single lvds channel can take 18 or 24 bi ts of rgb pixel data plus 3 bits of timing control (hsync/vsync/de) and output them on four differential data pair outputs. this display port is normally used in conj unction with the pipe functions of panel up- scaling and 6-to 8-bit dither. this display port is also used in conjunction with the panel power sequencing and additional associated functions. when enabled, the lvds constant current drivers consume significant power. individual pairs or sets of pairs can be selected to be powered down when not being used. when disabled, individual or sets of pairs will enter a low power state. when the port is disabled, all pairs enters a low power mode. the panel power sequencing can be set to override the selected power state of the drivers during power sequencing. a maximum pixel clock of 112 mhz is supported for the lvds interface.
datasheet 103 graphics, video, and display (d2:f0) 9.3.3.2 sdvo digital display port display pipe a is configured to use the sdvo port. the sdvo port can support a variety of display types (vga, lvds, dvi, tv-out, etc.) by an external sdvo device. sdvo devices translate sdvo protocol and timings to the desired display format and timings. a maximum pixel clock of 160 mhz is supported on the sdvo interface. 9.3.3.2.1 sdvo dvi/hdmi dvi (and hdmi), a 3.3-v interface standard supporting the tmds protocol, is a prime candidate for sdvo. the intel? sch provides an unscaled mode where the display data is centered within the attached display area. monitor hot plug functionality is supported. 9.3.3.2.2 sdvo lvds the intel? sch can use the sdvo port to drive an lvds transmitter. flat panel is a fixed resolution display. the intel? sch supports panel fitting in the transmitter, receiver or an external device, but has no native panel fitting capabilities. the intel? sch provides an unscaled mode where the disp lay data is centered within the attached display area. scaling in the lvds transmitter through the sdvo stall input pair is also supported. 9.3.3.2.3 sdvo tv-out the sdvo port supports both standard and hi gh-definition tv displays in a variety of formats. the sdvo port generates the proper blank and sync timing, but the external encoder is responsible for generation of the proper format signal and output timings. the intel? sch will support ntsc/pal/secam standard definition formats. the intel? sch will generate the proper timing for the external encoder. the external encoder is responsible for generation of the proper format signal. the tv-out interface on the intel? sch is addressable as a master device. this allows an external tv encoder device to drive a pixel clock signal on sdvo_tvclkin[+/-] that the intel? sch uses as a reference frequency. the frequency of this clock is dependent on the output resolution required. 9.3.3.2.4 flicker filter and overscan compensation the overscan compensation scaling and the flicker filter is done in the external tv encoder chip. care must be taken to allow for support of tv sets with high performance de-interlacers and progressive scan displays connected to by way of a non-interlaced signal. timing will be generated with pixel granularity to allow more overscan ratios to be supported. 9.3.3.2.5 control bus the sdvo port defines a two-wire (sdvo_ctrlclk and sdvo_ctrldata) communication path between the sdvo device and intel? sch. traffic destined for the prom or ddc will travel across the control bu s, and will then require the sdvo device to act as a switch and direct traffic from the control bus to the appropriate receiver. the control bus is able to operate at up to 1 mhz.
graphics, video, and display (d2:f0) 104 datasheet 9.4 configuration registers note: address locations that are not shown should be treated as reserved. table 25. graphics and video pci co nfiguration regist er address map offset mnemonic register name default type 00h?01h vid vendor identification 8086h ro 02h?03h did device identification 8108h ro 04h?05h pcicmd pci command 0000h r/w, ro 06h?07h pcists pci status 0000h ro 08h rid revision identification see description ro 09h?0bh cc class codes 03u000h ro 0eh headtyp header type 00h ro 10h?13h mem_base memory mapped base address 00000000h ro, r/w 14h?17h io_base i/o base address 00000000h ro, r/w 18h?1bh gmem_base graphics memory base address 00000000h ro, r/w, r/ wlor/wlo 1ch?1fh gtt_base graphics translation table range address 00000000h ro, r/w 2ch?2fh ss subsystem identifiers see description ro 34h cap_ptr capabilities pointer d0h ro 3ch int_ln interrupt line 00h ro 3dh int_pn interrupt pi n see description ro 52h?53h gc graphics control 0030h ro, r/w 58h?5bh ssrw software scratch read write 00000000h r/w 5ch?5fh bsm base of stolen memory 00000000h ro, r/w 90h msi_capid msi capability id 05h ro 91h nxt_ptr3 next item pointer 3 00h ro 92h?93h msi_ctl msi message control 0000h ro, r/w 94h?97h msi_adr msi message address 00000000h ro, r/w 98h?99h msi_data msi message data 0000h ro, r/w b0h vend_capid vendor capability id 09h ro b1h nxt_ptr2 next item poin ter 2 see description ro c4h fd function disable 00000000h ro, r/w d0h pm_capid power management capabilities id 01h ro d1h nxt_ptr1 next item pointer 1 b0h ro d2h?d3h pm_cap power management capabilities 0022h ro d4h?d5h pm_ctl_sts power management control/status 0000h ro, r/w e0h?e1h swscismi software sci/smi 0000h r/w, r/wo e4h?e7h asle system display event register see description r/w f0h gcr graphics clock ra tio see description r/w f4h?f7h lbb legacy backlight brightness see description r/w fch?ffh asls asl storage 00000000h r/w
datasheet 105 graphics, video, and display (d2:f0) 9.4.1 vid?vendor identification register register address: 00?01h attribute: ro default value: 8086h size: 16 bits 9.4.2 did?device identification register register address: 02h attribute: ro default value: 810xh size: 16 bits 9.4.3 pcicmd?pci command register register address: 04?05h attribute: ro, r/w default value: 0000h size: 16 bits bit default and access description 15:0 8086h ro vendor identification number (vid): pci standard identification for intel. bit default and access description 15:0 8108- 810fh ro device identification number (did): this is a 16-bit value assigned to the graphics controller. refer to the intel? sch specific ation update for the did for various product sku. bit default and access description 15:11 00h ro reserved 10 0 r/w interrupt disable (id): this bit disabl es the device from asserting intx#. 0 = enables the assertion of th is device?s intx# signal. 1 = disables the assertion of this device?s intx# signal. 9:3 0 ro reserved 2 0 r/w bus master enable (bme): enables the intel graphi cs media adapter to function as a pci compliant master. 1 0 r/w memory space enable (mse): when set, accesses to this device?s memory space is enabled. 0 0 r/w i/o space enable (iose): when set, accesses to this device?s i/o space is enabled.
graphics, video, and display (d2:f0) 106 datasheet 9.4.4 pcists?pci status register register address: 06-07h attribute: ro, r/w default value: 00000000h size: 16 bits 9.4.5 rid?revision identification register address: 08h attribute: ro default value: see description size: 8 bits 9.4.6 cc?class codes register register address: 09?0bh attribute: ro default value: 030000h size: 24 bits bit default and access description 15:5 0 ro reserved 4 1 ro capability list (cap): this bit indicates that the register at 34h provides an offset into pci configuration space containing a pointer to the location of the first item in the list. 3 0 ro interrupt status (is): this bit reflects the stat e of the interrupt in the device in the graphics device. 2:0 000b ro reserved bit default and access description 7:0 00h ro refer to the intel ? system controller hub (intel ? sch) specification update for the value of the revision id register. bit default and access description 23:16 03h ro base class code (bcc): indicates a display controller. 15:8 00h ro sub-class code (scc): when gc.vd is cleared, this value is 00h. when gc.vd is set, this value is 80h. 7:0 00h ro programming interface (pi): indicates a display controller.
datasheet 107 graphics, video, and display (d2:f0) 9.4.7 headtyp?header type register register address: 0eh attribute: ro default value: 00h size: 8 bits 9.4.8 mem_base?memory mapp ed base address register register address: 10h?13h attribute: ro, r/w default value: 00000000h size: 32 bits this register requests allocation for th e intel graphics media adapter registers and instruction ports. the allocation is for 512 kb. 9.4.9 io_base?i/o ba se address register register address: 14h?17h attribute: ro, r/w default value: 00000000h size: 32 bits this register provides the base offset of 8 bytes of i/o registers within this device. access to i/o space is allowed in the d0 state and cmd.iose is set. access is disallowed in states d1?d3 or if cmd.iose is cleared or if this device is disabled. access to this space is independent of vga functionality. bit default and access description 7 0 ro multi function status (mfunc): integrated graphics is a single function. 6:0 0000000b ro header code (hdr): indicates a type 0 header format. bit default and access description 31:19 0000h r/w base address (ba): set by the os, these bits correspond to address signals 31:19. 18:1 0000h ro reserved 0:0 0 ro resource type (rte): indicates a request for memory space. bit default and access description 31:16 0000h ro reserved 15:3 0000h r/w base address (ba): set by the os, these bits correspond to address signals 15:3. 2:1 00b ro reserved 0:0 1 ro resource type (rte): indicates a reques t for i/o space.
graphics, video, and display (d2:f0) 108 datasheet 9.4.10 gmem_base?graphics me mory base address register register address: 18h?1bh attribute: ro, r/w default value: 00000000h size: 32 bits this register provides the base address of the graphics aperture within this device. accesses to the graphics aperture use the address translation logic of the memory management unit within the graphics core. note: accesses to the graphics aperture are only pe rmitted if the internal memory requesters of the graphics core are not enabled. 9.4.11 gtt_base?graphics tran slation table base address register register address: 1ch?1fh attribute: ro, r/w default value: 00000000h size: 32 bits bit default and access description 31:29 000b r/w base address (ba): set by the os, these bits correspond to address signals 31:29. 28 0b ro reserved 27 0b r/wlo 256-mb address mask (m256): this bit is either part of the memory base address (rw) or part of the address mask (ro), depending on the value of msac.uas. 26:1 0s ro reserved 0 0 ro resource type (rte): indicates a request for memory space. bit default and access description 31:19 0000h r/w base address (ba): set by the os, these bits correspond to address signals 31:19. 18 0b r/wlo reserved 17 0b r/wlo 256-kb address mask (m256): this bit is either part of the gtt base address (rw) or part of the addres s mask (ro), depending on the value of msac.uas 16:1 0s ro reserved 0 0 ro resource type (rte): indicates a request for memory space.
datasheet 109 graphics, video, and display (d2:f0) 9.4.12 ss?subsystem identifiers this register matches the value written to the lpc bridge. 9.4.13 cap_ptr?capabilities pointer register register address: 34h attribute: ro, r/w default value: 00d0h size: 8 bits 9.4.14 int_ln?interrupt line register register address: 3ch attribute: ro, r/w default value: 00h size: 8 bits 9.4.15 int_pn?interrupt pin register register address: 3dh attribute: ro default value: see description size: 16 bits bit default and access description 7:0 d0h ro pointer (ptr): this field contains an offs et into the function's pci configuration space for the first item in the new capabilities linked list. bit default and access description 7:0 00h r/w interrupt line (ilin): software written valu e to indicate which interrupt line (vector) th e interrupt is connected to . no hardware action is taken on this bit. bit default and access description 7:0 desc ro interrupt pin (ipin): this value reflects the va lue of d02ip.gp in the lpc configuration space.
graphics, video, and display (d2:f0) 110 datasheet 9.4.16 gc?graphics control register register address: 52h?53h attribute: ro, r/w default value: 0030h size: 16 bits 9.4.17 ssrw?software scra tch read/write register register address: 58h?5bh attribute: r/w default value: 00000000h size: 32 bits bit default and access description 15:7 0 ro reserved 6:4 011b r/w graphics mode select (gms): this field is used to select the amount of memory pre-allocated to support the gr aphics device in vga (non-linear) and native (linear) modes. if graphi cs is disabled, this value must be programmed to 000h. this register is locked and becomes read only when the d_lck bit in the smram register is set. hardware do es not clear or set any of these bits automatically based on the intel grap hics media adapte r being disabled/ enabled. 3:2 00b ro reserved 1 0 ro vga disable (vd) 0 = vga memory and i/o cycles are enabled, and cc.scc is set to 00h. 1 = vga memory or i/o cycles are no t claimed, and cc.scc is set to 80h. 0 0 ro reserved bits 6:4 description 000 no memory pre-allocated. graphics does not claim vga cycles (mem and i/o), and cc.scc is 80h. 001 1 mb of memory pre- allocated for frame buffer. 010 4 mb of memory pre- allocated for frame buffer. 011 8 mb of memory pre- allocated for frame buffer. others reserved bit default and access description 31:0 0 r/w scratch (s): scratchpad bits
datasheet 111 graphics, video, and display (d2:f0) 9.4.18 bsm?base of stolen memory register register address: 5ch?5fh attribute: ro, r/w default value: 07800000h size: 32 bits 9.4.19 msac?multi size aperture control register address: 62h attribute: ro, r/w default value: 02hh size: 8 bits this register determines the size of the graphics memory aperture. by default, the aperture size is 256 mb. only bios writes this register based on address allocation efforts. drivers may read this register to determine the correct aperture size. bios must restore this data upon s3 resume. bit default and access description 31:20 078h r/w base of stolen memory (bsm): this field contains bits 31:20 of the base address of stolen dram memory. 19:0 00000h ro reserved bit default and access description 7:4 0h r/w scratch bits (scratch): these bits have no physical effect on hardware. 3:2 00b ro reserved 1:0 10b rw untrusted aperture size (uas): indicates the size of the untrusted aperture space. bits 1:0 description 11 128 mb. bits 28 and 27 of gtt_base are read-write limiting the address space to 128mb. 10 256 mb. bit 28 is read-write and bit 27 of gtt_base is read-only limiting the a ddress space to 256mb. 01 reserved 00 reserved
graphics, video, and display (d2:f0) 112 datasheet 9.4.20 msi_capid?msi capability register register address: 90h attribute: ro default value: 05h size: 8 bits 9.4.21 nxt_ptr3?next item pointer #3 register register address: 91h attribute: ro default value: 00h size: 8 bits 9.4.22 msi_ctl?message control register register address: 92h attribute: ro, r/w default value: 0000h size: 16 bits bit default and access description 7:0 05h ro capability id (id): indicates a messaged sign al interrupt capability. bit default and access description 7:0 00h ro pointer to next capability (next): 00h indicates this is the last capability in the list. bit default and access description 15:8 00h ro reserved 7:7 0 ro 64-bit address capable (c64): 32-bit capable only 6:4 000b r/w multiple message enable (mme): this field is r/w for software compatibility, but only a single message is ever generated. 3:1 000b ro multiple message capable (mmc): this device is only single message capable. 0 0 r/w msi enable (msie): if set, msi is enabled and traditional interrupts are not used to generate interrupts. cmd. bme must be set for an msi to be generated.
datasheet 113 graphics, video, and display (d2:f0) 9.4.23 msi_adr?message address register register address: 94-97h attribute: ro, r/w default value: 00000000h size: 32 bits a read from this register produces undefined results. 9.4.24 msi_data?message data register register address: 98-99h attribute: ro, r/w default value: 0000h size: 16 bits 9.4.25 vend_capid?vendor capability register register address: b0h attribute: ro default value: 09h size: 8 bits 9.4.26 nxt_ptr2?next item pointer #2 register register address: b1h attribute: ro default value: 90h/00h size: 8 bits bit default and access description 31:2 0 r/w address (addr): lower 32-bits of the system specified message address, always dword aligned. 1:0 00b ro reserved bit default and access description 15:0 0000h r/w data (data): this 16-bit field is programmed by system software and is driven onto the lower word of data du ring the data phase of the msi write transaction. bit default and access description 7:0 09h ro capability id (id): 09h indicates a vendor-specific capability. bit default and access description 7:0 90h/00h ro pointer to next capability (next): 90h indicates the address of the next capability. however, if the fd.md bit is set, the msi capability will be disabled and this register will report 00h indicati ng the power management capability is the last capability in the list.
graphics, video, and display (d2:f0) 114 datasheet 9.4.27 fd?function disable register register address: c4h?c7h attribute: ro, r/w default value: 00000000h size: 32 bits 9.4.28 pm_capid?power manageme nt capabilities id register register address: d0h attribute: ro default value: 01h size: 8 bits 9.4.29 nxt_ptr1?next item pointer #1 register register address: d1h attribute: ro default value: b0h size: 8 bits bit default and access description 31:2 0s ro reserved 1 0 r/w msi disable (md): when set, the msi capability pointer is not available. the item which points to the msi capability (nxt_ptr2) will, instead, indicate that this is the last item in the list. 0 0 r/w disable (d) 1 = d2:f0 is disabled. bit default and access description 7:0 01h ro capabilities id (capid): this id is 01h fo r power management. bit default and access description 7:0 b0h ro pointer to next capability (next): b0h indicates the address of the next capability.
datasheet 115 graphics, video, and display (d2:f0) 9.4.30 pm_cap?power manageme nt capabilities register register address: d2h?d3h attribute: ro, r/w default value: 0022h size: 16 bits 9.4.31 pm_ctl_sts?power management control/status register register address: d4h?d5h attribute: ro, r/w default value: 0000h size: 16 bits bit default and access description 15:11 00h ro pme support (pmes): the intel graphics me dia adapter does not generate pme#. 10 0 ro d2 support (d2s): the d2 power management state is not supported. 9 0 ro d1 support (d1s): the d1 power management state is not supported. 8:6 000b ro reserved 5 1 ro device specific initialization (dsi): hardwired to 1 to indicate that special initialization of the intel graphics media adapter is required before generic class device driver is to use it. 4:3 00b ro reserved 2:0 010b ro version (vs): indicates compliance with pci power management specification, revision 1.1 . bit default and access description 15:2 0000h ro reserved 1:0 00b r/w power state (ps): this field indicates the current power state of graphics and can be used to set graphics into a new power state. if software attempts to writ e an unsupported state to this field, the data is discarded and no st ate change occurs. 00 = d0 (default) 01 = d1 (not supported) 10 = d2 (not supported) 11 = d3
graphics, video, and display (d2:f0) 116 datasheet 9.4.32 swscismi?software sci/smi register register address: e0h?e1h attribute: r/w, r/wo default value: 0000h size: 16 bits 9.4.33 asle?system display event register register address: e4h?e7h attribute: r/w default value: 00000000h size: 32 bits bit default and access description 15 0 r/wo smi or sc event select (mcs): 0 = smi is selected. 1 = sci is selected. 14:1 0s r/w software scratch bits (ss): used by software. no hardware functionality. 0 0 r/w software sci event (swsci): if mcs is set, setting this bit causes an sci. bit default and access description 31:24 00h r/w asle scratch trigger 3 (ast3): when written, this scratch byte triggers an interrupt when ief-bit 0 is enabled and imr-bit 0 is unmasked. if written as part of a 16-bit or 32-bit write, only one interrupt is generated in common. 23:16 00h r/w asle scratch trigger 2 (ast2): same definition as ast3. 15:8 00h r/w asle scratch trigger 1 (ast1): same definition as ast3. 7:0 00h r/w asle scratch trigger 0 (ast0): same definition as ast3.
datasheet 117 graphics, video, and display (d2:f0) 9.4.34 gcr?graphics clock ratio register register address: f0h?f3h attribute: ro, r/w default value: 00000002h size: 32 bits c 9.4.35 lbb?legacy backli ght brightness register register address: f4h?f7h attribute: ro, r/w default value: 00000000h size: 32 bits bit default and access description 31:2 ro reserved 3:2 10b r/w graphics 2x clock to graphics clock ratio: the field is used to configure the graphics 2-d processing engine. 01 = ratio is 2:1 all other encodings are reserved. 1:0 10b r/w graphics clock to core clock ratio (gccr) : set by bios to correctly configure the graphics clock frequency as a function of the intel sch core clock frequency. 01 = ratio is 2:1 for: 200 mhz graphics at 100 mhz fsb operation 266 mhz graphics at 133 mhz fsb operation 10 = ratio is 3:2 for: 200 mhz graphics at 133-mhz fsb operation all other encodings are reserved. bit default and access description 31:24 00h r/w lbpc scratch trigger 3 (lst3): when enabled by inte rnal register bits, a write to this range triggers an display event interrupt. if written as part of a 16-bit or 32-bit write, only on e interrupt is generated in common. 23:16 00h r/w lbpc scratch trigger 2 (lst2): same definition as lst3 15:8 00h r/w lbpc scratch trigger 1 (lst1): same definition as lst3 7:0 00h r/w legacy backlight brightness (lbes): the value of zero is the lowest brightness setting and 255 is the brightest. if field lbes is written as part of a 16-bit (word) or 32-bit (dword) writ e to lbb, this will cause a flag to be set (lbes) in the pi pebstatus register and cause an interrupt if backlight event in the pipebstatus register and cause an interrupt if backlight event (lbee) and display b event is enabled by software. (if field lbes is written as a (one) by te write to lbb (i.e., if only least significant byte of lbb is written), no flag or interrupt will be generated.)
graphics, video, and display (d2:f0) 118 datasheet 9.4.36 asls?asl storage register register address: fch attribute: ro, r/w default value: 00000000h size: 32 bits bit default and access description 31:0 0s r/w scratchpad (sp): this definition of this scratch register is worked out in common between system bios and driver software. storage for up to six devices is possible. for each device, the asl control method requires two bits for _dod (bios detectable ye s or no, vga/non vga), one bit for _dgs (enable/disable requested), an d two bits for dcs (enabled now/ disabled now, connected or not).
datasheet 119 intel? hd audio (d27:f0) 10 intel? hd audio (d27:f0) 10.1 functional overview the controller consists of a set of dma engines that are used to move samples of digitally encoded data between system memo ry and an external codec(s). the intel? sch controller communicates with the external codec(s) over the intel hd audio serial link. the intel? sch implements two output dma engines and two input dma engines. the output dma engines move digital data from system memory to a d-a converter in a codec. the intel? sch implements a single serial data output signal (hda_sdout) that is connected to all external codecs. the input dma engines move digital data from the a-d converter in the codec to system memory. the intel? sch supports up to two external codecs by implementing two seri al digital input signals (hda_sdi[1:0]). audio software renders outbound and processes inbound data to/from buffers in system memory. the location of individual buffers is described by a buffer descriptor list (bdl) that is fetched and processed by the controller. the data in the buffers is arranged in a predefined format. the output dma engines fetch the digital data from memory and reformat it based on the programmed sample rate, bit/sample and number of channels. the data from the ou tput dma engines is then combined and serially sent to the external codecs over th e intel hd audio link. the input dma engines receive data from the codecs over the intel hd audio link and format the data based on the programmable attributes for that stream. the data is then written to memory in the predefined format for software to process. each dma engine moves one stream of data. a single codec can accept or generate multiple streams of data, one for each a-d or d- a converter in the codec. multiple codecs can accept the same output stream processed by a single dma engine. codec commands and responses are also tran sported to and from the codecs by dma engines. the dma engine dedicated to transporting commands from the command output ring buffer (corb) in memory to the codec(s) is called the corb engine. the dma engine dedicated to transporting responses from the codec(s) to the response input ring buffer in memory is called the ribr engine. every command sent to a codec yields a response from that codec. some commands are ?broadcast? type commands in which case a response will be generated from each codec. a codec may also be programmed to generate unsolicited responses, which the robr engine also processes. the intel? sch also supports programmed i/o-based immediate command/response transport mechanism that can be used by bios for memory initialization. 10.1.1 docking the intel? sch controls an external switch that is used to isolate a codec in the docking station. when docking occurs, softwa re is notified by acp, and initiates the docking sequence. the intel? sch manages the switch such that the electrical connection between the dock codec and the in tel hd audio interface occurs during the proper time within the frame sequence and when the signals are not transitioning. the intel? sch drives a dedicated reset signal to dock codec(s). it sequences the switch control and dedicated signal such that the dock codec experiences a ?normal? reset as specified in the intel hd audio specification. the user normally requests undocking. software halts streams to the codecs in the docking station and initiates the undocking sequence. the intel? sch asserts dock reset and manages the external switch to elec trically isolate the dock codec. electrical isolation during surprise undocking is handle d external to the intel? sch, and software invokes the undocking sequence as part of the clean-up process to prepare for a subsequent docking event.
intel? hd audio (d27:f0) 120 datasheet 10.1.1.1 dock sequence this sequence is followed when the system is running and a docking event occurs as well as when resuming from s3 (reset# a sserted) and intel hd audio controller d3. ? ecap.ds defaults to set. bios may clear th is bit to effectively turn off the docking feature. ? after reset, gctl.da and gsts.dm are cleared, hda_dock_en# deasserted and hda_dockrst# asserted. h_clkin, hda_sync hda_sdo may or may not be running. ? a docking event is signaled to software through acpi control methods. how this is done is outside the scope the spec. ? software first checks that the docking is supported (ecap.ds set) and that gsts.dm is cleared and in itiates the docking sequen ce by setting gctl.da. ? the intel? sch asserts hda_dock_en# synchronously to h_clkin and timed such that h_clkin is low, hda_sync is low, and hda_sdo is low. in the intel? sch, the first 8 bits of the command field are ?reserved? and driven to 0s, creating a predictable point in time to assert hda_dock_en#. ? after it asserts hda_dock_en#, it waits for a minimum of 2400 fsb clocks and deasserts hda_dockrst#, synchronous to h_clkin and timed such that there are least 4 h_clkin clock periods from th e deassertion of hda_dockrst# to the first frame hda_sync assertion. ? the connect/turnaround/address frame hardwa re initialization sequence occurs on dock codecs' sdi line. a dock codec is detected when sdi is high on the last h_clkin cycle of the frame hda_sync of a connect frame. the appropriate bit(s) in the state change status (statests) register are set. the turnaround and address frame initialization sequence then occurs on the dock codecs? sdi(s). ? after the sequence is complete, the inte l? sch sets gsts.dm indicating the dock is mated and that software can begin codec discovery, enumeration, and configuration. software discovers dock co decs by comparing the bits now set in the statsts register with the bits that were set prior to docking. 10.1.1.2 undock sequence there are two possible undocking scenarios. the first is the one that is initiated by the user that invokes software and gracefully shuts down the dock codecs before they are undocked. the second is referred to as th e ?surprise undock? where the user undocks while the dock codec is running. both of these situations appear the same to the controller as it is not cognizant of the ?surprise removal? ? in the docked quiescent state, gctl.da and gsts.dm are asserted. hda_dock_en# is asserted and hda_dockrst# is deasserted. ? user initiates an undock event through a mechanism outside the scope of this document. ? software halts the stream to the dock codec and clears gctl.da. ? the intel? sch asserts hda_dock rst# synchronous to h_clkin. hda_dockrst# assertion will occur a mini mum of four h_clkin ticks after the completion of the current frame. the hd audio link reset specification requirement that the last frame sync be skipped will not be met. ? a minimum of four h_clkin periods afte r hda_dockrst#, assertion, the intel? sch deasserts hda_dock_en# to isolat e the dock codec. hda_dock_en# is deasserted synchronously to h_clkin an d timed such that h_clkin, hda_sync, and hda_sdo are low. ? hardware clears gsts.dm. an interrupt can be enabled (dmis status and dmie enable bits) to notify software. ? the intel? sch is now ready for a subsequent docking event.
datasheet 121 intel? hd audio (d27:f0) 10.1.1.3 relationship between hda_dockrst# and hda_rst# hda_rst# is asserted when reset# occurs or when the crst# bit is 0. in both of these cases gctl.da and gsts.dm bits are cleared, hda_dock_e n# is deasserted, and hda_dockrst# is asserted. after reset, software is responsible for initiating the electrical connection, discovery, and enumeration process just as it would for a normal docking event. 10.1.1.4 external pull-ups/pull-downs the following table shows the resistors that should be mounted on the dock side of the isolation switch. note: 1. weak pull-down resistor is about 10 k . 10.1.2 low voltage (lv) mode the intel? sch does not implement an automatic voltage detection circuit to dynamically select the i/o voltage of intel hd audio i/o pins. bit zero of the hd control register (offset 40h) is used to select either high-voltage (3.3 v) or low-voltage (1.5 v) i/o operation. the default mode is 3.3 v. signal intel? sch resistors 1 external resistors hda_clk weak pull-down weak pull-down hda_sync none weak pull-down hda_sdo none weak pull-down hda_sdi (from docked codec(s))s weak pull-down none hda_rst# none na hda_dock_en# none na hda_dockrst# none weak pull-down
intel? hd audio (d27:f0) 122 datasheet 10.2 pci configuration register space the intel hd audio controller resides in pci device 27, function 0 on bus 0. this function contains a set of dma engines that are used to move samples of digitally encoded data between system memory and external codecs. all registers in this function (including me mory-mapped registers) must be addressable in byte, word, and dword quantities. the software must always make register accesses on natural boundaries (i.e., dword accesses must be on dword boundaries; word accesses on word boundaries, etc.) in a ddition, the memory-mapped register space must not be accessed with the lock semantic exclusive-access mechanism. if software attempts exclusive-access mechanisms to the intel hd audio memory-mapped space, the results are undefined. table 26. intel hd audio pci config uration registers (sheet 1 of 2) offset mnemonic register name default access 00h?01h vid vendor identification 8086h ro 02h?03h did device identification 811bh ro 04h?05h pcicmd pci command 0000h r/w, ro 06h?07h pcists pci status 0010h ro 08h rid revision identification see description ro 09?0bh cc class codes 040300h ro 0dh cls cache line size 00h r/w 0dh lt latency timer 00h ro 0eh headtyp header type 00h ro 10h?13h lbar lower base address 00000004h r/w, ro 14h?17h ubar upper base address 00000000h r/w 2ch?2fh ss subsystem identifiers see description r/wo 34h cap_ptr capabilities pointer 50h ro 3ch intln interrupt line 00h r/w 3dh intpn interrupt pin see description ro 40h hdctl hd control 00h r/w, ro 44h tcsel traffic class select 00h r/w 4ch dckctl docking control 00h r/w, ro 4dh dcksts docking status 80h r/wo, ro 50h pm_capid pci power management capability id 01h ro 51h nxt_ptr1 next capability pointer #1 70h ro 52h?53h pm_cap power management capabilities c842 ro 54h?57h pm_ctl_sts power management control and status 00000000h r/w, ro, r/wc 60h msi_capid msi capability id 05h ro 61h nxt_ptr3 next capability pointer #3 70h ro
datasheet 123 intel? hd audio (d27:f0) note: address locations that are not shown should be treated as reserved. 62h?63h msi_ctl msi message control 0080h r/w, ro 64h?67h msi_adr msi message address 00000000h r/w, ro 68h?69h msi_data msi message data 0000h r/w 70h pcie_capid pci express capability id 10h ro 71h nxt_ptr2 next capability pointer #2 60h or 00h ro 72h?73h pciecap pci express capabilities 0091h ro 74h?77h devcap device capabilities 00000000h ro 78h?79h devc device control 0800h r/w, ro 7ah?7bh devs device status 0000h ro, r/w fch?ffh fd function disable register 00000000h ro, r/w 100h?103h vccap virtual channel enhanced capability header 13010002h ro 104h?107h pvccap1 port vc capability register 1 00000001h ro 108h?10bh pvccap2 port vc capability register 2 00000000h ro 10ch?10dh pvcctl port vc control 0000h ro 10eh?10fh pvcsts port vc status 0000h ro 110h?103h vc0cap vc0 resource capability 00000000h ro 114h?117h vc0ctl vc0 resource control 800000ffh r/w, ro 11ah?11bh vc0sts vc0 resource status 0000h ro 11ch?11fh vc1cap vc1 resource capability 00000000h ro 120h?123h vc1ctl vc1 resource control 00000000h r/w, ro 126h?127h vc1sts vc1 resource status 0000h ro 130h?133h rccap root complex link declaration enhanced capability header 00010005h ro 134h?137h esd element self description 0f000100h ro, r/w 140h?143h l1desc link 1 description see description ro 148h?14bh l1add link 1 address see description ro, r/w table 26. intel hd audio pci config uration registers (sheet 2 of 2) offset mnemonic register name default access
intel? hd audio (d27:f0) 124 datasheet 10.2.1 vid?vendor iden tification register offset: 00h-01h attribute: ro default value: 8086h size: 16 bits 10.2.2 did?device iden tification register offset address: 02h ? 03h attribute: ro default value: 811bh size: 16 bits 10.2.3 pcicmd?pci command register offset address: 04h ? 05h attribute: r/w, ro default value: 0000h size: 16 bits bit default and access description 15:0 ro vendor id this is a 16-bit value assigned to intel. intel vid = 8086h bit default and access description 15:0 811bh ro device id: this is a 16-bit value assigned to the intel hd audio controller. bit default and access description 15:11 0h ro reserved 10 0 r/w interrupt disable (id) 0 = the intx# signals may be asserted. 1 = the intel? hd audio controller intx# signal wi ll be deasserted note : this bit does not effect the generation of msi(s). 9:3 00h ro reserved 2 0 r/w bus master enable (bme) : controls standard pci express bus mastering capabilities for memory and i/o, reads and writes. note that this bit also controls msi generation since msis are essentially memory writes. 0 = disable 1 = enable 1 0 r/w memory space enable (mse): enables memory space addresses to the intel hd audio controller. 0 = disable 1 = enable 0 0 ro reserved
datasheet 125 intel? hd audio (d27:f0) 10.2.4 pcists?pci status register offset address: 06h ? 07h attribute: ro default value: 0010h size: 16 bits 10.2.5 rid?revision identification register offset: 08h attribute: ro default value: see description size: 8 bits 10.2.6 cc?class code register offset: 09h?0bh attribute: ro default value: 040300h size: 24 bits bit default and access description 15:5 000h ro reserved 4 1 ro capabilities list (cap_list) : indicates that the co ntroller contains a capabilities pointer list. the first item is pointed to by looking at configuration offset 34h. 3 0 ro interrupt status (is) 0 = this bit is 0 after th e interrupt is cleared. 1 = this bit is 1 when the intx# is asserted. note: this bit is not set by an msi. 2:0 000b ro reserved bit default and access description 7:0 see description ro revision id (rid). refer to the intel ? system controller hub (intel ? sch) specification update for the value of the revision id register bit default and access description 23:16 04h ro base class code (bcc) : 04h = multimedia device 8:15 03h ro sub-class code (scc) : 03h = audio device 7:0 00h ro programming interface (pi): indicates intel? hd audio programming interface.
intel? hd audio (d27:f0) 126 datasheet 10.2.7 cls?cache line size register address offset: 0ch attribute: r/w default value: 00h size: 8 bits 10.2.8 lt?latency timer register address offset: 0dh attribute: ro default value: 00h size: 8 bits 10.2.9 headtyp?header type register address offset: 0eh attribute: ro default value: 00h size: 8 bits bit default and access description 7:0 00h r/w cache line size (cls): does not apply to pci express. the pci express specification requires this to be impl emented as a r/w register but has no functional impact on the intel? sch. bit default and access description 7:0 00h ro latency timer: hardwired to 00 bit default and access description 7:0 00h ro header type: hardwired to 00.
datasheet 127 intel? hd audio (d27:f0) 10.2.10 lbar?lower base address register address offset: 10h-13h attribute: r/w, ro default value: 00000004h size: 32 bits 10.2.11 ubar?upper ba se address register address offset: 14h-17h attribute: r/w default value: 00000000h size: 32 bits this register matches the value written to the lpc bridge. 10.2.12 ss?sub system identifiers register offset: 2ch ? 2fh attribute: r/wo default value: 00000000h size: 32 bits this register is initialized to logic 0 by th e assertion of reset#. this register can be written only once afte r reset# deassertion. bit default and access description 31:14 0000h r/w lower base address (lba): this field provides the base address for the intel hd audio controller?s memory mapped configuration registers. 16 kb are requested by hardwiring bits 13:4 to 0?s. 13:4 000h ro reserved: hardwired to 0s 3 0 ro prefetchable (pref): hardwired to 0 to indicate that this bar is not prefetchable 2:1 10b ro address range (addrng): this field indicates that this bar can be located anywhere in 64-bit address space. 0 0 ro resource type (rte): indicates this bar is lo cated in memory space. bit default and access description 31:0 0 r/w upper base address (uba): this field provides th e upper 32 bits of the base address for the intel? hd audio controller memory mapped configuration registers. bit default and access description 31:16 0000h r/wo subsystem id (ssid): this field is written by bios. no hardware action taken on this value. 15:0 0000h r/wo subsystem vendor id (ssvid): this field is written by bios. no hardware action ta ken on this value.
intel? hd audio (d27:f0) 128 datasheet 10.2.13 cap_ptr?capabili ties pointer register address offset: 34h attribute: ro default value: 50h size: 8 bits this register indicates the offset for the capability pointer. 10.2.14 intln?interrupt line register address offset: 3ch attribute: r/w default value: 00h size: 8 bits 10.2.15 intpn?interrupt pin register address offset: 3dh attribute: ro default value: see description size: 8 bits 10.2.16 hdctl?hd control register address offset: 40h attribute: r/w, ro default value: 00h size: 8 bits bit default and access description 7:0 50h ro pointer (ptr): this field indicates that the first capability pointer offset is offset 50h (power management capability). bit default and access description 7:0 00h r/w interrupt line: this data is not used by th e intel? sch. it is used to communicate to software the interrupt line that the interrupt pin is connected to. bit default and access description 7:4 0h ro reserved 3:0 0h ro interrupt pin: this reflects the value of d27ip.zip (chipset config registers:offset 3110h:bits 3:0). bit default and access description 7:1 00h ro reserved 0 0 r/w low voltage mode enable (lmve) 0 = (default) the in tel hd audio controller operates in high voltage mode. 1 = the intel hd audio controller's afe operates in low voltage mode.
datasheet 129 intel? hd audio (d27:f0) 10.2.17 dckctl?docking control register address offset: 4ch attribute: r/w, ro default value: 00h size: 8 bits 10.2.18 dcksts?docking status register address offset: 4dh attribute: r/wo, ro default value: 80h size: 8 bits bit default and access description 7:1 00h ro reserved 0 0 r/w, ro dock attach (da): software writes a 1 to this bit to initiate the docking sequence on the hda_dock_en# and hda_dockrst# signals. when the docking sequence is complete, hardware will set the dock mated (gsts.dm) status bit to a 1. software writes a 0 to this bit to in itiate the undocking sequence on the hda_dock_en# and hda_dockrst# signals. when the undocking sequence is complete hardware will set the dock mated (gsts.dm) status bit to a 0. notes: ? software must check the state of the dock mated (gsts.dm) bit prior to writing to the dock attach bit. software shall only change the da bit from a 0 to a 1 when dm=0. likewise , software shall only change the da bit from 1 to 0 when dm=1. if these rules are violated, the results are undefined. ? this bit is read only when the dcksts.ds bit = 0. bit default and access description 7 1 r/wo docking supported (ds): when set, indicates intel? sch supports docking. dkctl.da is only writeable when this bit is 1. this bit is reset on reset#, but not on crst# 6:1 00h ro reserved 0 0 ro dock mated (dm): this bit indicates that codec is physically and electrically docked.
intel? hd audio (d27:f0) 130 datasheet 10.2.19 pm_capid?pci power ma nagement capability id register address offset: 50h attribute: ro default value: 01h size: 8 bits 10.2.20 pm_cap?power manage ment capabilities register address offset: 52h?53h attribute: ro default value: 4802h size: 16 bits bit default and access description 15:8 70h ro next capability (next ) : hardwired to 70h. points to the next capability structure (pci express). 7:0 01h ro cap id (cap): hardwired to 01h to indicate that this pointer is a pci power management capability. bit default and access description 15:11 01001b ro pme support: hardwired to 01001b to indicate pme# can be generated from d3 hot and d0 states. 10:3 0s ro reserved 2:0 010b ro version (vs): hardwired to 010b to indicate support for pci power management specification, revision 1.1 .
datasheet 131 intel? hd audio (d27:f0) 10.2.21 pm_ctl_sts?power mana gement control and status register address offset: 54h-57h attribute: ro, r/w, r/wc default value: 00000000h size: 32 bits 10.2.22 msi_capid?msi ca pability id register address offset: 60h attribute: ro default value: 0005h size: 16 bits bit default and access description 31:16 0000h ro reserved 15 0 r/wc pme status (pmes) 0 = software clears the bit by writing a 1 to it. 1 = when the intel hd audio controller would normally assert the pme# signal independent of the state of the pmee (bit 8 in this register). 14:9 00h ro reserved 8 0 r/w pme enable (pmee) 0 = disable 1 = when set, and pmes is set, the au dio controller gene rates an internal power management event (pme). 7:2 00h ro reserved 1:0 00b r/w power state (ps): this field is used both to determine the current power state of the intel hd audio controller and to set a new power state. 00 = d0 state 11 = d3 hot state others = reserved notes : ? if software attempts to write a value of 01b or 10b in to this field, the write operation must complete normal ly; however, the data is discarded and no state change occurs. ? when in the d3 hot states, the intel hd audio controller configuration space is available, but the i/o and memory space are not. additionally, interrupts are blocked. ? when software changes this value from d3 hot state to the d0 state, an internal warm (soft) rese t is generated, and soft ware must re-initialize the function. bit default and access description 15:8 00h ro next capability (next ) : points to the next item in the capability list. wired to 00h to indicate this is the last capability in the list. 7:0 05h ro cap id (cap) hardwired to 05h: indicates that this pointer is a msi capability.
intel? hd audio (d27:f0) 132 datasheet 10.2.23 msi_ctl?msi message control register address offset: 62h?63h attribute: ro, r/w default value: 0000h size: 16 bits 10.2.24 msi_adr?msi mess age address register address offset: 64h?67h attribute: ro, r/w default value: 00000000h size: 32 bits 10.2.25 msi_data?msi message data register address offset: 68h?69h attribute: r/w default value: 0000h size: 16 bits bit default and access description 15:1 0000h ro reserved 0 0 r/w msi enable (me) 0 = an msi may not be generated 1 = an msi will be generated instead of an intx signal. bit default and access description 31:2 0s r/w message lower address (mla): address used for msi message. 1:0 00b ro reserved bit default and access description 15:0 0000h r/w message data (md): data used for msi message.
datasheet 133 intel? hd audio (d27:f0) 10.2.26 pcie_capid?pci expres s capability id register address offset: 70h attribute: ro default value: 60/00 10h size: 8 bits 10.2.27 pciecap?pci expres s capabilities register address offset: 72h?73h attribute: ro default value: 0091h size: 16 bits 10.2.28 devcap?device ca pabilities register address offset: 74h?77h attribute: ro default value: 00000000h size: 32 bits bit default and access description 7:0 60h/00h ro next capability (next ) : defaults to 60h, the address of the next capability structure in the list. however, if the fd.md bit is set, the ms i capability will be disabled and this register will report 00h indi cating this capability is the last capability in the list. 7:0 10h ro cap id (cap) : hardwired to 10h. indicates that this pointer is a pci express capability structure. bit default and access description 15:8 00h ro reserved 7:4 9h ro device/port type (dpt): hardwired to 1001b. indicates that this is a root complex integrat ed endpoint device. 3:0 1h ro capability version (cv): hardwired to 0001b. indicates version #1 pci express capability. bit default and access description 31:0 0 ro reserved
intel? hd audio (d27:f0) 134 datasheet 10.2.29 devc?device control register address offset: 78h?79h attribute: r/w, ro default value: 0800h size: 16 bits 10.2.30 devs?device status register address offset: 7ah?7bh attribute: ro, r/w default value: 0000h size: 16 bits bit default and access description 15 0 ro reserved 14:12 000b ro max read request size (mrrs): hardwired to 000 enabling 128 b maximum read request size. 11 1 r/w no snoop enable (nsnpen): 0 = the intel hd audio controller will not se t the no-snoop bit. in this case, isochronous transfers will not use vc1 (vci) even if it is enabled since vc1 is never snooped. isochronous transfers will use vc0. 1 = the intel hd audio controller is permitted to set th e no-snoop bit in the requester attributes of a bus master transaction. in this case, vc0 or vc1 may be used fo r isochronous transfers. note: this bit is not reset on d3 hot to d0 transition. 10:4 0 ro reserved 3:0 0 r/w error reporting bits (erb): r/w to pass pci express compliance test. no functionality. bit default and access description 15:6 0000h ro reserved 5 0 ro transactions pending (txp): 0 = completions for all non-posted requests have been received. 1 = the intel hd audio controller ha s issued non-posted requests which have not been completed. 4:0 00000b r/w reserved
datasheet 135 intel? hd audio (d27:f0) 10.2.31 fd?function disable register address offset: fch?ffh attribute: ro, r/w default value: 00000000h size: 32 bits 10.2.32 vccap?virtual channel e nhanced capability header register address offset: 100h?103h attribute: ro default value: 13010002h size: 32 bits 10.2.33 pvccap1?port vc capability register 1 address offset: 104h?107h attribute: ro default value: 00000001h size: 32 bits bit default and access description 31:3 0 ro reserved 2 0 r/w clock gating disable (gcd) 0 = dynamic clock gating within the function is enabled (default) 1 = dynamic clock gating within the function is disabled. 1 0 r/w msi disable (md) 1 = when set, the msi capa bility pointer is hidden. 0 0 r/w disable (d) 1 = intel? hd audio functi on (d27:f0) is disabled. bit default and access description 31:20 130h ro next capability offset (nxtap): points to the next capability header, which is the root complex link decl aration enhanced capability header. 19:16 1h ro capability version 15:0 0002h ro pci express extended capability bit default and access description 31:3 0 ro reserved 2:0 001b ro extended vc count (vccnt): hardwired to 001b. indicates that 1 extended vc (in addition to vc0) is supported by the intel? hd audio controller.
intel? hd audio (d27:f0) 136 datasheet 10.2.34 pvcc2?port vc ca pability register 2 address offset: 108h-10bh attribute: ro default value: 00000000h size: 32 bits 10.2.35 pcctl?port vc control address offset: 10ch-10dh attribute: ro default value: 0000h size: 16 bits 10.2.36 pvcsts?port vc status address offset: 10eh-10fh attribute: ro default value: 0000h size: 16 bits 10.2.37 vc0cap?vc0 resour ce capability register address offset: 110h-113h attribute: ro default value: 00000000h size: 32 bits bit default and access description 31:0 0 ro reserved bit default and access description 15:0 0 ro reserved bit default and access description 15:0 0 ro reserved bit default and access description 31:0 0 ro reserved
datasheet 137 intel? hd audio (d27:f0) 10.2.38 vc0ctl?vc0 reso urce control register address offset: 114h?117h attribute: r/w, ro default value: 800000ffh size: 32 bits 10.2.39 vcsts?vc0 resource status register address offset: 11ah-10bh attribute: ro default value: 0000h size: 16 bits 10.2.40 vc0cap?vc0 resour ce capability register address offset: 11ch-10fh attribute: ro default value: 00000000h size: 32 bits bit default and access description 31 1 ro vc0 enable: hardwired to 1 for vc0. 30:8 0 ro reserved 7:0 ffh r/w, ro tc/vc0 map: bit 0 is hardwired to 1 since tc0 is always mapped vc0. bits [7:1] are implemented as r/w bits. bit default and access description 16:0 0 ro reserved bit default and access description 31:0 0 ro reserved
intel? hd audio (d27:f0) 138 datasheet 10.2.41 vc1ctl?vc1 resource control register address offset: 120h?123h attribute: r/w, ro default value: 00000000h size: 32 bits 10.2.42 vc1sts?vc1 resource status register address offset: 126h-127h attribute: ro default value: 0000h size: 16 bits bit default and access description 31 0 r/w vc1 enable 0 = vc1 is disabled 1 = vc1 is enabled note: this bit is not reset on d3 hot to d0 transition. 30:27 0h ro reserved 26:24 000b r/w vc1 id: this field assigns a vc id to th e vc1 resource. this field is not used by the intel? sch hardware, but it is r/w to avoid confusing software. 23:8 0h ro reserved 7:0 00h r/w, ro tc/vc map: this field indicates the tc s that are mapped to the vc1 resource. bit 0 is hardwired to 0 indi cating that it cannot be mapped to vc1. bits [7:1] are implemented as r/w bits. this field is not used by the intel? sch, but it is r/w to avoid confusing software. bit default and access description 15:0 0 ro reserved
datasheet 139 intel? hd audio (d27:f0) 10.2.43 rccap?root complex link declaration enhanced capability header register address offset: 130h?133h attribute: ro default value: 00010005h size: 32 bits 10.2.44 esd?element self description register address offset: 134h?137h attribute: ro, r/w default value: 0f000100h size: 32 bits bit default and access description 31:20 000h ro next capability offset: indicates this is the last capability. 19:16 1h ro capability version 15:0 0005h ro pci express extended capability id bit default and access description 31:24 0fh ro port number (pn): hardwired to 0fh indicating that the intel? hd audio controller is assigned as port #15d. 23:16 00h r/w component id (compid): set by bios to match the value of esd.cid of the chip configuration section. 15:8 01h ro number of link entries (nle): the hd audio controller only connects to the intel? sch egress port. 7:4 0h ro reserved 3:0 0h ro element type (eltyp): the intel hd audio controller is an integrated root complex device. therefore, the field reports a value of 0h.
intel? hd audio (d27:f0) 140 datasheet 10.2.45 l1desc?link 1 description register address offset: 140h?143h attribute: ro default value: 00000001h size: 32 bits 10.2.46 l1add?link 1 address register address offset: 148h?14bh attribute: ro, r/w default value: see description size: 32 bits bit default and access description 31:24 ro target port number: the intel? hd audio controller targets the intel? sch?s rcrb egress port, port 0. 23:16 see description ro target component id: returns the value of esd.compid. 15:2 ro reserved 1 0 ro link type (lnktyp): indicates type 0. 0 1 ro link valid (lnkvld) bit default and access description 31:14 rcba r/w base (base): hardwired to match the rcba register value in the pci-lpc bridge (d31:f0h). 13:0 0000h ro reserved
datasheet 141 intel? hd audio (d27:f0) 10.3 memory mapped configuration registers the base memory location for these memory mapped configuration registers is specified in the lbar and ubar registers (d27:f0:offset 10h and d27:f0:offset 14h). the individual registers are then accessible at lbar + offset as indicated in ta b l e 2 7 . these memory mapped registers must be accessed in byte, word, or dword quantities. table 27. intel hd audio memory mapped configuration regist ers (sheet 1 of 3) lbar + offset mnemonic register name default access 00h?01h gcap global capabilities 4401h ro 02h vmin minor version 00h ro 03h vmaj major version 01h ro 04h?05h outpay output payload capability 003ch ro 06h?07h inpay input payload capability 001dh ro 08h?0bh gctl global control 00000000h r/w 0ch wakeen wake enable 0000h r/w, ro 0eh statests state change status 0000h r/w, ro 10h?11h gsts global status 0000h r/wc 18h?19h outstrmpay output stream payload capability 0030h ro 1ah?1bh instrmpay input stream payload capability 0018h ro 20h?23h intctl interrupt control 00000000h r/w, ro 24h?27h intsts interrupt status 00000000h ro 30h?33h walclk wall clock counter 00000000h ro 38h?3bh ssync stream synchronization 00000000h r/w, ro 40h?43h corbbase corb base address 00000000h r/w, ro 48h?49h corbwp corb write pointer 0000h r/w, ro 4ah?4bh corbrp corb read pointer 0000h r/w, ro 4ch corbctl corb control 00h r/w, ro 4dh corbst corb status 00h r/wc 4eh corbsize corb size 42h ro 50h?53h rirbbase rirb base address 00000000h r/w, ro 58h?59h rirbwp rirb write pointer 0000h wo, ro 5ah?5bh rintcnt response in terrupt count 0000h r/w, ro 5ch rirbctl rirb control 00h r/w, ro 5dh rirbsts rirb status 00h r/wc, ro 5eh rirbsize rirb size 40h ro 60h?63h ic immediate command 00000000h r/w 64h?67h ir immediate response 00000000h ro 68h?69h irs immediate command status 0000h r/w, r/ wc, ro
intel? hd audio (d27:f0) 142 datasheet 70h?73h dpbase dma position base address 00000000h r/w, ro 80-82h isd0ctl input stream descriptor 0 (isd0) control 040000h r/w, ro 83h isd0sts isd0 status 00h r/wc, ro 84h?87h isd0lpib isd0 link position in buffer 00000000h ro 88h?8bh isd0cbl isd0 cyclic buffer length 00000000h r/w 8ch?8dh isd0lvi isd0 last valid index 0000h r/w, ro 8eh?8fh isd0fifow isd0 fifo watermark 0004h r/w, ro 90h?91h isd0fifos isd0 fifo size 0077h ro 92h?93h isd0fmt isd0 format 0000h r/w, ro 98h?9bh isd0bdpl isd0 buffer descriptor list pointer 00000000h r/w, ro, wo a0h?a2h isd1ctl input stream desc riptor 1(isd01) control 040000h r/w, ro a3h isd1sts isd1 status 00h r/wc, ro a4h?a7h isd1lpib isd1 link position in buffer 00000000h ro a8h?abh isd1cbl isd1 cyclic buffer length 00000000h r/w ach?adh isd1lvi isd1 last valid index 0000h r/w, ro aeh?afh isd1fifow isd1 fifo watermark 0004h r/w, ro b0h?b1h isd1fifos isd1 fifo size 0077h ro b2-b3h isd1fmt isd1 format 0000h r/w, ro b8-bbh isd1bdpl isd1 buffer descriptor list pointer 00000000h r/w, ro, wo c0h?c2h osd0ctl output stream descriptor 0 (osd0) control 040000h r/w, ro c3h osd0sts osd0 status 00h r/wc, ro c4h?c7h osd0lpib osd0 link position in buffer 00000000h ro c8h?cbh osd0cbl osd0 cyclic buffer length 00000000h r/w cch?cdh osd0lvi osd0 last valid index 0000h r/w, ro ceh?cfh osd0fifow osd0 fifo watermark 0004h r/w, ro d0h?d1h osd0fifos osd0 fifo size 00bfh r/w, ro d2h-d3h osd0fmt osd0 format 0000h r/w, ro d8h?dbh osd0bdpl osd0 buffer descriptor list pointer 00000000h r/w, ro, wo e0h?e2h osd1ctl output stream descriptor 1 (osd1) control 040000h r/w, ro 123h osd1sts osd1 status 00h r/wc, ro table 27. intel hd audio memory mapped configuration registers (sheet 2 of 3) lbar + offset mnemonic register name default access
datasheet 143 intel? hd audio (d27:f0) notes: 1. the 4-kb memory-mapped range starting at lbar + 4 kb is reserved in the intel hd audio specification for vendor-specific registers. 2. address locations that are not shown should be treated as reserved. e4h?e7h osd1lpib osd1 link position in buffer 00000000h ro e8h?ebh osd1cbl osd1 cyclic buffer length 00000000h r/w ech?edh osd1lvi osd1 last valid index 0000h r/w, ro eeh?efh osd1fifow osd1 fifo watermark 0004h r/w, ro f0h?f1h osd1fifos osd1 fifo size 00bfh r/w, ro f2h?f3h osd1fmt osd1 format 0000h r/w, ro f8h?fbh osd1bdpl osd1 buffer descriptor list pointer 00000000h r/w, ro vendor-specific memory mapped registers 1 1030h?1033h em1 extended mode 1 0c00000h r/w, ro 1004h?1007h inrc input stream repeat count 00000000h ro 1008h?100bh outrc output stream repeat count 00000000h ro 100ch?100fh fifotrk fifo tracking 000ff800h ro, r/w 1010h?1013h i0dpib input stream 0 dma position in buffer 00000000h ro 1014h?1017h i1dpib input stream 1 dma position in buffer 00000000h ro 1020h?1023h o0dpib output stream 0 dma position in buffer 00000000h ro 1024h?1027h o1dpib output stream 1 dma position in buffer 00000000h ro 1030h?1033h em2 extended mode 2 00000000h r/w, ro 2030h?2033h wlclka wall clock counter alias 00000000h ro 2084h?2087h isd0lpiba isd0 link position in buffer alias 00000000h ro 20a4h?20a7h isd1lpiba isd1 link po sition in buffer alias 00000000h ro 2104h?2107h osd0lpiba osd0 link position in buffer alias 00000000h ro 2124h?2127h osd1lpiba osd1 link position in buffer alias 00000000h ro table 27. intel hd audio memory mapped configuration regist ers (sheet 3 of 3) lbar + offset mnemonic register name default access
intel? hd audio (d27:f0) 144 datasheet 10.3.1 gcap?global capabilities register memory address: lbar + 00h attribute: ro default value: 4401h size: 16 bits 10.3.2 vmin?minor version register memory address: lbar + 02h attribute: ro default value: 00h size: 8 bits 10.3.3 vmaj?major version register memory address: lbar + 03h attribute: ro default value: 01h size: 8 bits bit default and access description 15:12 0010b ro output stream supported (oss): indicates that the intel? hd audio controller supports 2 output streams. 11:8 0010b ro input stream supported (iss): indicates that the intel hd audio controller supports 2 input streams. 7:3 00000b ro bidirectional stream supported: indicates that the intel hd audio controller supports 0 bidirectional stream. 2 ro reserved 1 0b ro serial data out signals (nsdo): indicates that the intel hd audio controller supports 1 serial data output signal. 0 0b ro 64-bit address supported (64ok): 64-bit addressing is not supported. bit default and access description 7:0 00h ro minor version (maj): indicates that the intel? sch supports minor revision number 00h of the intel? hd audio specification. bit default and access description 7:0 01h ro major version (maj): indicating that the in tel? sch supports major revision number 01h of the in tel? hd audio specification.
datasheet 145 intel? hd audio (d27:f0) 10.3.4 outpay?output payl oad capability register memory address: lbar + 04h attribute: ro default value: 003ch size: 16 bits 10.3.5 inpay?input payloa d capability register memory address: lbar + 06h attribute: ro default value: 001dh size: 16 bits bit default and access description 15:7 0 ro reserved 6:0 3ch ro output payload capability (out): indicates the total output payload available on the link as 60 words (120 bytes). this field indicates the total output pa yload available on the link. this does not include bandwidth used for command and control. this measurement is in 16-bit word quantities per 48-mhz frame. the default link clock of 24.000 mhz (t he data is double pumped) provides 1000 bits per frame, or 62.5 words in total. 40 bits are used for command and control, leaving 60 word s available for data payload. 00h = 0 word 01h = 1 word payload ..... ffh = 256 word payload bit default and access description 15:7 0 ro reserved 6:0 1dh ro input payload capability (in): hardwired to 1dh indicating 29 word payload. this field indicates the total output pa yload available on the link. this does not include bandwidth used for respon se. this measurement is in 16-bit word quantities per 48-mhz frame. the default link clock of 24.000 mhz provides 500 bits per frame, or 31.25 words in total. 36 bits are used for response, leaving 29 words available for data payload. 00h = 0 word 01h = 1 word payload ..... ffh = 256 word payload
intel? hd audio (d27:f0) 146 datasheet 10.3.6 gctl?global control register memory address: lbar + 08h attribute: r/w, ro default value: 00000000h size: 32 bits (sheet 1 of 2) bit default and access description 31:9 0 ro reserved 8 0 r/w accept unsolicited response enable (aure) 0 = unsolicited responses from the codecs are not accepted. 1 = unsolicited response from the code cs are accepted by the controller and placed into the resp onse input ring buffer. 7:2 000000b ro reserved 1 0 r/w flush control (flush) : writing a 1 to this bit initiates a flush. when the flush completion is received by the controller, hardware sets the flush status bit and clears this flush control bit. before a flush cycle is initiated, the dma position buffer must be programm ed with a valid memory address by software, but th e dma position buffer bit 0 needs not be set to enable the position re porting mechanism. also, all streams must be stopped (the associ ated run bit must be a 0. when the flush is initiated, the controller will flush the pipelines to memory to ensure that the hardware is ready to transition to a d3 state. setting this bit is not a critical step in the power state transition if the content of the fifios is not critical.
datasheet 147 intel? hd audio (d27:f0) 10.3.7 statests - state change status memory address: lbar + 0eh attribute: ro default value: 001dh size: 16 bits 0 0 r/w controller reset # 0 = writing a 0 to this bit causes the intel hd audio controller to be reset. all state machines, fifos and non-resume well memory mapped configuration registers (not pci configuration registers) in the controller will be reset. the intel hd audio link reset# signal will be asserted, and all other lin k signals will be driven to their default values. after the hardware has completed sequencing into the reset state, it will report a 0 in this bit. software must read a 0 from this bit to verify the controller is in reset. 1 = writing a 1 to this bit causes the controller to exit its reset state and deassert the intel hd audio link reset# signal. software is responsible for setting/clearing this bit such that the minimum intel hd audio link reset# signal assertion pulse width specification is met. when the controller hardware is ready to begin operation, it will report a 1 in this bit. software must read a 1 from this bit before accessing any controller registers. this bit defaults to a 0 after hardware reset, therefor e, software needs to write a 1 to this bit to begin operation. notes: ? the corb/rirb run bits and all st ream run bits must be verified cleared to 0 before writing a 0 to th is bit in order to assure a clean re-start. ? when setting or clearing this bi t, software must ensure that minimum link timing requirements (minimum reset# assertion time, etc.) are met. ? when this bit is 0 indicating that the controller is in reset, writes to all intel hd audio memory mapped registers are ignored as if the device is not present. the only exception is this register itself. the global control register is writ e-able as a dword, word, or byte even when crst# (this bit) is 0 if the byte enable for the byte containing the crst# bit (byte enable 0) is active. if byte enable 0 is not active, writes to the global control register will be ignored when crst# is 0. when crst# is 0, reads to intel hd audio memory mapped registers will return their default value exce pt for registers that are not reset with reset# or on a d3 hot to d0 transition. (sheet 2 of 2) bit default and access description
intel? hd audio (d27:f0) 148 datasheet bit default and access description 15:3 0 ro reserved 1:0 00b rwc sdin state change status flags (sdiwake): flag bits that indicate which sdi signal(s) received a "state change" event. the bits are cleared by writing a 1 to them. bit 0 is for sdi0, bit 1 is for sdi1 bit 2 is for sdi2. these bits are in the suspend well an d only cleared on a power-on reset. software must not make assumptions about the reset state of these bits and must set them appropriately.
datasheet 149 intel? hd audio (d27:f0) 10.3.8 gsts?global status register memory address: lbar + 10h attribute: r/wc, ro default value: 0000h size: 16 bits bit default and access description 15:4 000h ro reserved 3 0 r/wc dock mated interrupt status (dmis): a 1 indicates that the dock mating or unmating process has comp leted. for the docking process it indicates that dock is electrically co nnected and that software may detect and enumerate the docked codecs. for the undocking process it indicates that the dock is electrically isolated and that software may report to the user that physical undocking may comm ence. this bit gets set to a 1 by hardware when the dm bit transitions from a 0 to a 1 (docking) or from a 1 to a 0 (undocking). note that this bit is set regardless of the state of the dmie bit. software clears this bit by writing a 1 to it. writing a 0 to this bit has no effect. 2 0 ro dock mated (dm): this bit effectively communic ates to software that an intel hd audio docked codec is phys ically and electr ically attached. controller hardware sets this bit to 1 after the docking sequence triggered by writing a 1 to the dock atta ch (gctl.da) bit is completed (hda_dockrst# deassertion). this bi t indicates to software that the docked codec(s) may be discovered by the statests register and then enumerated. controller hardware sets this bit to 0 after the undocking sequence triggered by writing a 0 to the dock attach (gctl.da) bit is completed (dock_en# deasserted). this bit indicates to software that the docked codec(s) may be ph ysically undocked. this bit is read only. writes to this bit have no effect. 1 0 r/wc flush status: this bit is set to 1 by hardwa re to indicate that the flush cycle initiated when the flush control bit (lbar + 08h, bit 1) was set has completed. software must write a 1 to clear this bit before the next time the flush control bit is set to clear the bit. 0 0 ro reserved
intel? hd audio (d27:f0) 150 datasheet 10.3.9 ecap?extended capabilities memory address: lbar + 14h attribute: ro default value: 00000001h size: 32 bits 10.3.10 strmpay?stream payload capability memory address: lbar + 18h attribute: ro default value: 00180030h size: 32 bits bit default and access description 31:1 0 ro reserved 1 000b r/wo docking supported (ds): a 1 indicates that intel? sch supports intel hd audio docking. the gctl.da bit is only writable when this bit is 1. this bit is reset to its default value only on reset#, but not on a crst# or d3hot-to-d0 transition. bit default and access description 31:24 00h ro reserved 23:16 18h ro input (in): indicates the number of words per frame for the input streams is 24 words. this measuremen t is in 16-bit word quantities per 48-khz frame. 15:8 00h ro reserved 7:0 30h ro output (out): indicates the number of words per frame for output streams is 48 words. this measuremen t is in 16-bit word quantities per 48-khz frame.
datasheet 151 intel? hd audio (d27:f0) 10.3.11 intctl?interrupt control register memory address: lbar + 20h attribute: r/w, ro default value: 00000000h size: 32 bits bit default and access description 31 0 r/w global interrupt enable (gie): global bit to enable device interrupt generation. 1 = intel? hd audio function is enabled to generate an interrupt. this control is in addition to any bits in the bus specific address space, such as the interrupt enable bit in the pci configuration space. note: this bit is not affected by the d3 hot to d0 transition. 30 0 r/w controller interrupt enable (cie): enables the general interrupt for controller functions. 1 = controller generates an interrupt when the co rresponding status bit gets set due to a response interru pt, a response buffer overrun, and state change events. note: this bit is not affected by the d3 hot to d0 transition. 29:4 0 ro reserved 3 0 r/w output stream 2 (os2): this bit set and ge set enables intsts.os2 to generate an interrupt. 2 0 r/w output stream 1 (os1): this bit set and ge set enables intsts.os1 to generate an interrupt. 1 0 r/w input stream 2 (is2): this bit set and ge set enables intsts.is2 to generate an interrupt. 0 0 r/w input stream 1 (is1): this bit set and ge set enables intsts.is1 to generate an interrupt.
intel? hd audio (d27:f0) 152 datasheet 10.3.12 intsts?interrupt status register memory address: lbar + 24h attribute: ro default value: 00000000h size: 32 bits bit default and access description 31 0 ro global interrupt status (gis): this bit is an or of all the interrupt status bits in this register. note: this bit is not affected by the d3 hot to d0 transition. 30 0 ro controller interrupt status (cis): status of general controller interrupt. 1 = indicates that an interrupt co ndition occurred due to a response interrupt, a response buffer over run interrupt, or a sdin state change event. the exact cause can be determined by interrogating other registers. this bit is an or of all of the stated interrupt status bits for this register. notes: 1. this bit is set regardless of the state of the corresponding interrupt enable bit, but a hardware interrupt will not be generated unless the corresponding enable bit is set. 2. this bit is not affected by the d3 hot to d0 transition. 29:4 0 ro reserved 3 0 ro output stream 2 (os2): 1 = interrupt occurred on output stream 2. 2 0 ro output stream 1 (os1): 1 = interrupt occurred on output stream 1. 1 0 ro input stream 2 (is2): 1 = interrupt occurred on input stream 2. 0 0 ro input stream 1 (is1): 1 = interrupt occurred on input stream 1.
datasheet 153 intel? hd audio (d27:f0) 10.3.13 walclk?wall cl ock counter register memory address: lbar + 30h attribute: ro default value: 00000000h size: 32 bits 10.3.14 ssync?stream synchronization register memory address: lbar + 38h attribute: r/w, ro default value: 00000000h size: 32 bits 10.3.15 corbbase?corb ba se address register memory address: lbar + 40h attribute: r/w, ro default value: 00000000h size: 32 bits bit default and access description 31:0 0s ro wall clock counter: this field is a 32-bit coun ter that is in cremented on each link h_clkin period and rolls over from ffff ffffh to 0000 0000h. this counter will roll over to 0 with a period of approximately 179 seconds. this counter is enabled while the h_cl kin bit is set to 1. software uses this counter to synchronize between mult iple controllers. will be reset on controller reset. bits default and access description 31:4 0 ro reserved 3 0 r/w output stream 2 sync (os2): when set, this bit blocks data from being sent for output stream 2. 2 0 r/w output stream 1 sync (os1): when set, this bit blocks data from being sent for output stream 1. 1 0 r/w input stream 2 sync (is2): when set, this bit blocks data from being received from input stream 2. 0 0 r/w input stream 1 sync (is1): when set, this bit blocks data from being received from input stream 1. bit default and access description 31:7 0 r/w corb base address: this field is the lowe r address of the command output ring buffer, allowing the corb base address to be assigned on any 128-b boundary. this register field must not be written when the dma engine is running or the dma transfer may be corrupted. 6:0 0 ro reserved
intel? hd audio (d27:f0) 154 datasheet 10.3.16 corbwp?corb write pointer register memory address: lbar + 48h attribute: r/w, ro default value: 0000h size: 16 bits 10.3.17 corbrp?corb read pointer register memory address: lbar + 4ah attribute: r/w, ro default value: 0000h size: 16 bits bit default and access description 15:8 00h ro reserved 7:0 00h r/w corb write pointer: software writes the last va lid corb entry offset into this field in dword granularity. th e dma engine fetches commands from the corb until the read pointer ma tches the write pointer. supports 256 corb entries (256 x 4 byte = 1 kb). this register field may be written when the dma engine is running. bit default and access description 15 0 r/w corb read pointer reset: software writes a 1 to this bit to reset the corb read pointer to 0 and clear any residual prefetched commands in the corb hardware buffer within the intel hd audio controller. the hardware will physically update this bit to 1 when the corb pointer reset is complete. software must read a 1 to verify that the reset completed correctly. software must clear this bit back to 0 and read back the 0 to verify that the clear completed correctly. the corb dm a engine must be stopped prior to resetting the read pointer or else dma transfer may be corrupted. 14:8 00h ro reserved 7:0 00h ro corb read pointer (corbrp): software reads this field to determine how many commands it can write to the corb without over-running. the value read indicates the corb read poin ter offset in dword granularity. the offset entry read from this field has been successfully fetched by the dma controller and may be over-written by software. supports 256 corb entries (256 x 4 byte =1 kb). this field ma y be read while the dma engine is running.
datasheet 155 intel? hd audio (d27:f0) 10.3.18 corbctl?corb control register memory address: lbar + 4ch attribute: r/w, ro default value: 00h size: 8 bits 10.3.19 corbst?corb status register memory address: lbar + 4dh attribute: ro default value: 00h size: 8 bits 10.3.20 corbsize?corb size register memory address: lbar + 4eh attribute: ro default value: 42h size: 8 bits bit default and access description 7:2 00h ro reserved 1 0 r/w enable corb dma engine: 0 = dma stop 1 = dma run after software writes a 0 to this bit, the hardware may not stop immediately. the hardware will physic ally update the bit to 0 when the dma engine is truly stoppe d. software must read a 0 from this bit to verify that the dma engine is truly stopped. 0 0 r/w corb memory error interrupt enable: if this bit is set, the controller will generate an interrupt if the cmei status bit (lbar + 4dh: bit 0) is set. bit default and access description 7:0 00h reserved bit default and access description 7:4 0100b ro corb size capability: hardwired to 0100b indicating that the intel? sch only supports a corb size of 256 corb entries (1024b). 3:2 00b ro reserved 1:0 10b ro corb size: hardwired to 10b which sets the corb size to 256 entries (1024 b).
intel? hd audio (d27:f0) 156 datasheet 10.3.21 rirbbase?rirb ba se address register memory address: lbar + 50h attribute: r/w, ro default value: 00000000h size: 32 bits 10.3.22 rirbwp?rirb wr ite pointer register memory address: lbar + 58h attribute: wo, ro default value: 0000h size: 16 bits bit default and access description 31:7 0s r/w corb lower base address: this field is the lower address of the response input ring buffer, allowing th e rirb base address to be assigned on any 128-b boundary. this register field must not be written when the dma engine is running or the dma transfer may be corrupted. 6:0 00h ro reserved bit default and access description 15 0 wo rirb write pointer reset: software writes a 1 to this bit to reset the rirb write pointer to 0. the rirb dm a engine must be stopped prior to resetting the write pointer or else dma transfer may be corrupted. this bit is always read as 0. 14:8 00h ro reserved 7:0 00h ro rirb write pointer (rirbwp): this field is the indicates the last valid rirb entry written by the dma controller. software reads this field to determine how many responses it can read from the rirb. the value read indicates the rirb write pointer offset in 2-dword rirb entry units (since each rirb entry is 2 dwords long). supports up to 256 rirb entries (256 x 8 bytes = 2kb). this register field may be written when the dma engine is running.
datasheet 157 intel? hd audio (d27:f0) 10.3.23 rintcnt?response interrupt count register memory address: lbar + 5ah attribute: r/w, ro default value: 0000h size: 16 bits 10.3.24 rirbctl?rirb control register memory address: lbar + 5ch attribute: r/w, ro default value: 00h size: 8 bits bit default and access description 15:8 00h ro reserved 7:0 00h r/w n response interrupt count 0000 0001b = 1 response sent to rirb ........... 1111 1111b = 255 responses sent to rirb 0000 0000b = 256 responses sent to rirb the dma engine should be stopped when changing this field or else an interrupt may be lost. note that each response occu pies 2 dwords in the rirb. this is compared to the total numb er of responses that have been returned, as opposed to the number of frames in which there were responses. if more than one codecs responds in one frame, then the count is increased by the number of responses received in the frame. bit default and access description 7:3 0h ro reserved 2 0 r/w response overrun interrupt control: if this bit is set, the hardware will generate an interrupt when the response overrun interrupt status bit (lbar + 5dh: bit 2) is set. 1 0 r/w enable rirb dma engine: 0 = dma stop 1 = dma run after software writes a 0 to this bit, the hardware may not stop immediately. the hardware will physic ally update the bit to 0 when the dma engine is truly sto pped. software must read a 0 from this bit to verify that the dma engine is truly stopped. 0 0 r/w response interrupt control : 0 = disable interrupt 1 = generate an interrupt after n numb er of responses are sent to the rirb buffer or when an empty resp onse slot is encountered on all sdi[x] inputs (whichever occurs fi rst). the n counter is reset when the interrupt is generated.
intel? hd audio (d27:f0) 158 datasheet 10.3.25 rirbsts?rirb status register memory address: lbar + 5dh attribute: r/wc, ro default value: 00h size: 8 bits 10.3.26 rirbsize?rirb size register memory address: lbar + 5eh attribute: ro default value: 40h size: 8 bits bit default and access description 7:3 0h ro reserved 2 0 r/wc response overrun interrupt status: software sets th is bit to 1 when the rirb dma engine is not able to write the incoming responses to memory before additional incoming responses overrun the internal fifo. when the overrun occurs, the hardwa re will drop the responses which overrun the buffer. an interrupt may be generated if the response overrun interrupt control bit is se t. note that this status bit is set even if an interrupt is not enabled for this event. software clears this bit by writing a 1 to it. 1 0 ro reserved 0 0 r/wc response interrupt: hardware sets this bit to 1 when an interrupt has been generated after n number of resp onses are sent to the rirb buffer or when an empty response slot is encountered on all sdi[x] inputs (whichever occurs first). note that this status bit is set even if an interrupt is not enabled for this event. software clears this bit by writing a 1 to it. bit default and access description 7:4 0100b ro rirb size capability: hardwired to 0100b indicating that the intel? sch only supports a rirb size of 256 rirb entries (2048 b). 3:2 00b ro reserved 1:0 00b ro rirb size: hardwired to 10b which sets the corb size to 256 entries (2048 b).
datasheet 159 intel? hd audio (d27:f0) 10.3.27 ic?immediate command register memory address: lbar + 60h attribute: r/w default value: 00000000h size: 32 bits 10.3.28 ir?immediate response register memory address: lbar + 64h attribute: ro default value: 00000000h size: 32 bits bit default and access description 31:0 0 r/w immediate command write: the command to be sent to the codec by the immediate command mechanism is written to this register. the command stored in this register is se nt out over the link during the next available frame after a 1 is written to the icb bit (lbar + 68h: bit 0). bit default and access description 31:0 0 ro immediate response read (irr): this register cont ains the response received from a codec resulting from a command sent by the immediate command mechanism. if multiple codecs responded in the same time, there is no assurance as to which response will be latched. ther efore, broadcast-type commands must not be issued by the im mediate command mechanism.
intel? hd audio (d27:f0) 160 datasheet 10.3.29 irs?immediate co mmand status register memory address: lbar + 68h attribute: r/w, r/wc, ro default value: 0000h size: 16 bits 10.3.30 dpbase?dma position base address register memory address: lbar + 70h attribute: r/w, ro default value: 00000000h size: 32 bits bit default and access description 15:2 0 ro reserved 1 0 r/wc immediate result valid (irv): this bit is set to 1 by hardware when a new response is latched into the immediate response register (lbar + 64). this is a status flag indicating that software may read the response from the immediate response register. software must clear this bit by writ ing a 1 to it before issuing a new command so that the so ftware may determine wh en a new response has arrived. 0 0 r/w immediate command busy (icb): when this bit is read as 0, it indicates that a new command may be issued usin g the immediate command mechanism. when this bit transitions from a 0 to a 1 (by software writing a 1), th e controller issues the command currently stored in the immediate command register to the codec over the link. when the corresponding response is latched in to the immediate response register, the controller hardware sets the irv fl ag and clears the icb bit back to 0. note: an immediate command must not be issued while the corb/rirb mechanism is operating, otherwise the responses conflict. this must be enforced by software. bit default and access description 31:7 0 r/w dma position base address: this field is the lowe r 32 bits of the dma position buffer base address. this re gister field must no t be written when any dma engine is running or the dma transfer may be corrupted. this same address is used by the flush co ntrol and must be programmed with a valid value before the flush contro l bit (lbar+08h:bit 1) is set. 6:1 00000b ro reserved 0 0 r/w dma position buffer enable: when this bit is set to 1, the controller will write the dma positions of each of the dma engines to the buffer in the main memory periodically (typically on ce per frame). soft ware can use this value to know what data in memory is valid data.
datasheet 161 intel? hd audio (d27:f0) 10.3.31 sdctl?stream desc riptor control register memory address: input stream[0]: lbar + 80h attribute: r/w, ro input stream[1]: lbar + a0h output stream[0]: lbar + c0h output stream[1]: lbar + e0h default value: 040000h size: 24 bits bit default and access description 23:20 0h r/w stream number: this value reflect the tag associated with the data being transferred on the link. when data controlled by this descriptor is sent out over the link, it will have its stream number encoded on the hda_sync signal. when an input stream is detected on any of the sdi signals that match this value, the data samples are loaded into fifo associated with this descriptor. note that while a single sdi input may contain data from more than one stream number, two differe nt sdi inputs may not be configured with the same stream number. 0000 = reserved 0001 = stream 1 ........ 1110 = stream 14 1111 = stream 15 19 0 ro bidirectional direction control: this bit is only meaningful for bidirectional streams; therefore, this bit is hardwired to 0. 18 1 ro traffic priority: hardwired to 1 indicating that all streams will use vc1 if it is enabled through the pci express registers. 17:16 00 ro stripe control: this bit is only meaningful for input stream s; therefore, this bit is hardwired to 0. 15:5 0 ro reserved 4 0 r/w descriptor error interrupt enable 0 = disable 1 = an interrupt is generated when the descriptor error status bit is set. 3 0 r/w fifo error interrupt enable: this bit controls whether the occurrence of a fifo error (overrun for input or underrun for output) will cause an interrupt or not. if this bit is not set, bit 3 in the status register will be set, but the interrupt will not occur. either way, the samples will be dropped. 2 0 r/w interrupt on completion enable: this bit controls whether or not an interrupt occurs when a buffer comp letes with the ioc bit set in its descriptor. if this bit is not set, bit 2 in the status register will be set, but the interrupt will not occur.
intel? hd audio (d27:f0) 162 datasheet 1 0 r/w stream run (run): 0 = the dma engine associated with this input stream will be disabled. the hardware will report a 0 in this bi t when the dma engine is actually stopped. software must read a 0 fro m this bit before modifying related control registers or restarting the dma engine. 1 = the dma engine associated with th is input stream will be enabled to transfer data from the fifo to the main memory. the ssync bit must also be cleared in order for the dma engine to r un. for output streams, the cadence generator is reset whenever the run bit is set. 0 0 r/w stream reset (srst): 0 = writing a 0 causes the corresponding stream to exit reset. when the stream hardware is ready to begin oper ation, it will report a 0 in this bit. software must read a 0 from th is bit before accessing any of the stream registers. 1 = writing a 1 causes the corresponding stream to be re set. the stream descriptor registers (except the sr st bit itself) an d fifos for the corresponding stream are reset. after the stream hardware has completed sequencing into the reset state, it will report a 1 in this bit. software must read a 1 from this bit to verify that the stream is in reset. the run bit must be clea red before srst is asserted. bit default and access description
datasheet 163 intel? hd audio (d27:f0) 10.3.32 sdsts?stream desc riptor status register memory address: input stream[0]: lbar + 83h attribute: r/wc, ro input stream[1]: lbar + a3h output stream[0]: lbar + c3h output stream[1]: lbar + e3h default value: 00h size: 8 bits bit default and access description 7:6 00b ro reserved 5 0 ro fifo ready (fifordy): for output streams, the controller hardware will set this bit to 1 while the output dma fifo contains enough data to maintain the stream on the link. this bit defaults to 0 on reset because the fifo is cleared on a reset. for input streams, the controller hardware will set this bit to 1 when a valid descriptor is loaded and the engine is ready for the run bit to be set. 4 0 r/wc descriptor error: when set, this bit indi cates that a serious error occurred during the fetch of a descriptor . this could be a result of a master abort, a parity or ecc error on the bus, or any other error which renders the current buffer descriptor or buffer de scriptor list useles s. this error is treated as a fatal stream error, as th e stream cannot continue running. the run bit will be cl eared and the stream will stopped. software may attempt to restart the stream engine after addressing the cause of the error and writing a 1 to this bit to clear it. 3 0 r/wc fifo error: this bit is set when a fifo error occurs. this bit is set even if an interrupt is not enabled. the bi t is cleared by writing a 1 to it. for an input stream, this indicates a fifo overrun occurring while the run bit is set. when this happens, the fi fo pointers do not increment and the incoming data is not written into the fifo, thereby being lost. for an output stream, this indicates a fifo underrun when there are still buffers to send. the hardware should no t transmit anything on the link for the associated stream if ther e is not valid data to send. 2 0 r/wc buffer completion interrupt status: this bit is set to 1 by the hardware after the last sample of a buffer has been processed, an d if the interrupt on completion bit is set in the comma nd byte of the buffer descriptor. it remains active until so ftware clears it by writing a 1 to it. 1:0 00 ro reserved
intel? hd audio (d27:f0) 164 datasheet 10.3.33 sdlpib?stream descriptor link position in buffer register memory address: input stream[0]: lbar + 84h attribute: ro input stream[1]: lbar + a4h output stream[0]: lbar + c4h output stream[1]: lbar + e4h default value: 00000000h size: 32 bits 10.3.34 sdcbl?stream descriptor cyclic buffer length register memory address: input stream[0]: lbar + 88h attribute: r/w input stream[1]: lbar + a8h output stream[0]: lbar + c8h output stream[1]: lbar + e8h default value: 00000000h size: 32 bits bit default and access description 31:0 0 ro link position in buffer: this field indicates th e number of bytes that have been received off the link. this register will count from 0 to the value in the cyclic buffer length re gister and then wrap to 0. bit default and access description 31:0 0 r/w cyclic buffer length: indicates the number of bytes in the complete cyclic buffer. this register represents an integer number of samples. link position in buffer will be rese t when it reaches this value. software may only write to this regi ster after global reset, controller reset, or stream reset has occurred. this value should be only modified when the run bit is 0. once the run bit has been set to enable the engine, software must not write to this register until after the next reset is asserted, or transfer may be corrupted.
datasheet 165 intel? hd audio (d27:f0) 10.3.35 sdlvi?stream descriptor last valid index register memory address: input stream[0]: lbar + 8ch attribute: r/w, ro input stream[1]: lbar + ach output stream[0]: lbar + cch output stream[1]: lbar + ech default value: 0000h size: 16 bits 10.3.36 sdfifow?stream descript or fifo watermark register memory address: input stream[0]: lbar + 8eh attribute: r/w, ro input stream[1]: lbar + aeh output stream[0]: lbar + ceh output stream[1]: lbar + eeh default value: 0004h size: 16 bits bit default and access description 15:8 00h ro reserved 7:0 00h r/w last valid index: the value written to this register indicates the index for the last valid buffer descriptor in bd l. after the controller has processed this descriptor, it will wrap back to the first descripto r in the list and continue processing. this field must be at leas t 1 (i.e., there must be at least 2 valid entries in the buffer descriptor list before dma operations can begin). this value should only modified when the run bit is 0. bit default and access description 15:3 0 ro reserved 2:0 100b r/w fifo watermark (fifow). indicates the minimum number of bytes accumulated/free in the fifo before the controller will start a fetch/ eviction of data. 010 = 8 b 011 = 16 b 100 = 32 b (default) others = unsupported note: when the bit field is programmed to an unsupported size, the hardware sets itself to the default value. so ftware must read the bit field to test if the value is supported after setting the bit field.
intel? hd audio (d27:f0) 166 datasheet 10.3.37 sdfifos?stream descri ptor fifo size register memory address: input stream[0]: lbar + 90h attribute: input: ro input stream[1]: lbar + b0h output: r/w, ro output stream[0]: lbar + d0h output stream[1]: lbar + f0h default value: input stream: 0077h size: 16 bits output stream: 00bfh bit default and access description 15:8 00h ro reserved 7:0 77h ro (input) bfh r/w (output) fifo size ? ro (input stream), r/w (output stream): indicates the maximum number of bytes that could be fetched by the controller at one time. this is the maximum number of bytes that may have been dma?d into memory but not yet transmitted on the link, and is also the maximum possible value that the picb coun t will increase by at one time. the value in this field is different for input and output streams. it is also dependent on the bits per samples se tting for the corresponding stream. following are the values read/written from/to this register for input and output streams, and for non- padded and padded bit formats: output stream r/w value : notes: 1. all other values not listed are not supported. 2. when the output stre am is programmed to an unsupported size, the hardware sets itself to the default value (bfh). 3. software must read th e bit field to test if the value is supported after setting the bit field. input stream ro value : note: the default value is different fo r input and output streams, and reflects the default state of the bits fields (in stream descriptor format registers) for th e corresponding stream. value output streams 0fh = 16b 8, 16, 20, 24, or 32 bit output streams 1fh = 32b 8, 16, 20, 24, or 32 bit output streams 3fh = 64b 8, 16, 20, 24, or 32 bit output streams 7fh = 128b 8, 16, 20, 24, or 32 bit output streams bfh = 192b 8, 16, or 32 bit output streams ffh = 256b 20, 24 bit output streams value input streams 77h = 120b 8, 16, 32 bit input streams 9fh = 160b 20, 24 bit input streams
datasheet 167 intel? hd audio (d27:f0) 10.3.38 sdfmt?stream descriptor format register memory address: input stream[0]: lbar + 92h attribute: r/w, ro input stream[1]: lbar + b2h output stream[0]: lbar + d2h output stream[1]: lbar + f2h default value: 0000h size: 16 bits bit default and access description 15 0 ro reserved 14 0 r/w sample base rate: r/w 0 = 48 khz 1 = 44.1 khz 13:11 000b r/w sample base rate multiple: r/w 000 = 48 khz, 44.1 khz or less 001 = x2 (96 khz, 88.2 khz, 32 khz) 010 = x3 (144 khz) 011 = x4 (192 khz, 176.4 khz) others = reserved. 10:8 000b r/w sample base rate divisor: 000 = divide by 1(48 khz, 44.1 khz) 001 = divide by 2 (24 khz, 22.05 khz) 010 = divide by 3 (16 khz, 32 khz) 011 = divide by 4 (11.025 khz) 100 = divide by 5 (9.6 khz) 101 = divide by 6 (8 khz) 110 = divide by 7 111 = divide by 8 (6 khz) 7 0 ro reserved 6:4 000b r/w bits per sample (bits): 000 = 8 bits. the data will be packed in memory in 8- bit containers on 16-bit boundaries 001 = 16 bits. the data will be packed in memory in 16-bit containers on 16-bit boundaries 010 = 20 bits. the data will be packed in memory in 32-bit containers on 32-bit boundaries 011 = 24 bits. the data will be packed in memory in 32-bit containers on 32-bit boundaries 100 = 32 bits. the data will be packed in memory in 32-bit containers on 32-bit boundaries others = reserved. 3:0 0h r/w number of channels (chan): indicates number of channels in each frame of the stream. 0000 =1 0001 =2 ........ 1111 =16
intel? hd audio (d27:f0) 168 datasheet 10.3.39 sdbdpl?stream descriptor buffer descriptor pointer list base register memory address: input stream[0]: lbar + 98h attribute: r/w, ro, wo input stream[1]: lbar + b8h output stream[0]: lbar + d8h output stream[1]: lbar + f8h default value: 00000000h size: 32 bits bit default and access description 31:7 0 r/w buffer descriptor list po inter lower base address: lower address of the buffer descriptor list . this value should only be modified when the run bit is 0, or dma transfer may be corrupted. 6:1 00h ro reserved 0 0 rw/wo protect (prot): when set, all bits of this register are wo and return 0 when read. when cleared, bits are rw. tis bit can only be changed when all four bytes of this register are written in a single write operation. if less than four bytes are written this bit retains its previous value.
datasheet 169 intel? hd audio (d27:f0) 10.4 vendor specific memory mapped registers 10.4.1 em1?extended mode 1 register memory address: 1000h attribute: ro default value: 00000000h size: 32 bits bit default and access description 31:24 0 ro reserved 28:28 00b rw loopback enable (lpbken): when set, output data is rerouted to the input. each input has its own loopback enable. 27:26 00 rw free count request (freecntreq): this field determ ines the clock in which freecnt will be requ ested from the xfr layer. bios or software must set freecntreq to ?11? any other selection will cause rirb failures. 25 0b rw phase select (psel): sets the input data sample point within phyclk. 1 = phase c, 0 = phase d 24 1b rw boundary break (128_4k): sets the break boundary for reads. 0 = 4kb 1 = 128b 23:21 000b rw corb pace (corbpace): determines the rate at which corb commands are issued on the link. 000 = every frame 001 = every 2 frames ...... 111 = every 8 frames 20 0b rw fifo ready select (frs): when cleared, sds.frdy is asserted when there are 2 or more packets available in the fifo. when set, sds.frdy is asserted when there are one or more packets available in the fifo. 19:15 00000b ro reserved 14 0b rw 48 khz enable: when set, intel? sch adds one extra bitclk to every twelfth frame. when cleared, it will use the normal func tionality and send 500 bitclks per frame. 13 0b rw dock enable signal tran sition select (dets): when set, dock_en# transitions off the falling edge of bclk (phase c). when cleared, dock_en# transitions 1/4 bclk after th e falling edge of bclk (phase d). 12:6 0s ro reserved 5:4 00b wo input repeat count resets (ircr): software writes a 1 to clear the respective repeat count to 00h. reads from these bits return 0. bit 5 = input stream 1 repeat count reset bit 4 = input stream 0 repeat count reset 3:2 00b ro reserved 1:0 00b wo output repeat count resets (orcr): software writes a 1 to clear the respective repeat count to 00h. reads from these bits return 0. bit 1 = output stream 1 repeat count reset bit 0 = output stream 0 repeat count reset
intel? hd audio (d27:f0) 170 datasheet 10.4.2 inrc?input stream repeat count register memory address: 1004h attribute: ro default value: 00000000h size: 32 bits 10.4.3 outrc?output stream repeat count register memory address: 1008h attribute: ro default value: 00000000h size: 32 bits bit default and access description 31:24 0 ro reserved 15:8 00h ro stream 1 (s1): reports the number of times a buffer descriptor list has been repeated. 7:0 00h ro stream 0 (s0): reports the number of times a buffer descriptor list has been repeated. bit default and access description 31:16 0 ro reserved 15:8 00h ro stream 1 (s1): reports the number of times a buffer descriptor list has been repeated. 7:0 00h ro stream 0 (s0): reports the number of times a buffer descriptor list has been repeated.
datasheet 171 intel? hd audio (d27:f0) 10.4.4 fifotrk ? fifo tracking register memory address: 100ch attribute: r/w, ro default value: 000ff800h size: 32 bits 10.4.5 sdpib?stream dma posi tion in buffer register memory address: input stream 0: 1010h attribute: ro input stream 1: 1014h output stream 0: 1020h output stream 2: 1024h default value: 00000000h size: 32 bits bit default and access description 31:20 000h ro reserved 19:11 1ffh ro minimum status (msts): tracks the minimum fifo free count for inbound engines, and the minimum avai l count for outbound engines when en is set and r is deasserted. the fi fo of the dma selected by sel is tracked. 10:5 000h ro error count (ec): increments each time a fifo error occurs in the fifo which the dma select is pointing to when the enable bit is set and r is deasserted. when ec reaches a ma x count of 1ffh (63), the count saturates and holds the max count until it is reset. 4:2 000b r/w select (sel): msts and ec track the fifo for the dma select by this register, as follows: 000 = output dma 0 001 = output dma 1 010 = reserved 011 = reserved 100 = input dma 0 101 = input dma 1 110 = reserved 111 = reserved 1 0 r/w enable (en): when set, msts and ec track the minimum fifo status or error count. when cleared, msts and ec hold its previous value. 0 0 r/w reset (r): when set, msts and ec are reset to their default value. bit default and access description 31:0 0 ro position (pos): indicates the number of by tes processed by the dma engine from the beginning of the bd l. for output st reams, it is incremented when data is loaded into the fifo.
intel? hd audio (d27:f0) 172 datasheet 10.4.6 em2?extended mode 2 register memory address: 1030h attribute: r/w, ro default value: 00000000h size: 32 bits 10.4.7 wlclka?wall clock counter alias register memory address: 2030h attribute: ro default value: 00000000h size: 32 bits 10.4.8 slpib?stream link posi tion in buffer register memory address: input stream 0: 2084h attribute: ro input stream 1: 20a4h output stream 0: 2104h output stream 2: 2124h default value: 00000000h size: 32 bits bit default and access description 31:9 0 ro reserved 8 0 r/w corb reset pointer change disable (corprpdis): when cleared, corbrp.rpr works as described. when th is bit is set, the corb fifo is not reset and corbrp.rpr is wo and always read as 0. 7:0 0h ro reserved bit default and access description 31:0 0 ro wall clock counter alias (countera): alias of walck. 32-bit counter that is incremented on each link h_clkin period and rolls over from ffff_ffffh to 0000_0000h. this counter will roll over to zero with a period of approximately 179 seconds. this counter is enabled while the h_cl kin bit is set to 1. software uses this counter to synchronize between mult iple controllers. will be reset on controller reset. bit default and access description 31:0 0 ro position (pos): alias of the corresponding lpib. indicates the number of bytes that have been received off the link. it counts from 0 to the value in the cyclic buffer length register and wraps.
datasheet 173 pci express* (d28:f0, f1) 11 pci express* (d28:f0, f1) 11.1 functional description there are two pci express root ports available in the intel? sch. they reside in device 28 and take function 0 and 1. port 1 is function 0 and port 2 is function 1. 11.1.1 interrupt generation if enabled to do so, the intel? sch pci ex press root port generates interrupts as a result of power management events. these interrupts can be communicated either by legacy interrupt pins (internal to the intel? sch), or as message signal interrupt messages to the fsb. for the legacy pin be havior, the d28ip (base address + 310ch) and d28ir (base address + 3146h) registers ca n be configured to drive a particular internal interrupt signal. the following table summarizes interrupt be havior for msi and wire modes. in the table, ?bits? refers to the pme interrupt bits. 11.1.2 power management 11.1.2.1 sleep state support software initiates the transition to s3/s4/s5 by performing an i/o write to the power management control register. after the i/o write completion has been returned to the processor, each root port will send a pme_turn_off tlp (transaction layer packet) message on it's downstream link. the devi ce attached to the link will eventually respond with a pme_to_ack tlp message followed by sending a pm_enter_l23 dllp (data link layer packet) request to enter the l2/l3 ready state. when all of the intel? sch root ports links are in the l2/l3 read y state, the intel? sch power management control logic will proceed with the entry into s3/s4/s5. prior to entering s3, software is required to put each device into d3hot. when a device is put into d3hot it will initiate entry into a l1 link state by sending a pm_enter_l1 dllp. thus under normal operating cond itions when the root ports sends the pme_turn_off message the link will be in state l1. however, when the root port is instructed to send the pme_turn_off message, it will send it whether or not the link was in l1. endpoints attached to ich can make no assumptions about the state of the link prior to receiving a pme_turn_off message. table 28. msi vs. pci irq actions interrupt register wire-mode action msi action all bits are 0 wire inactive no action one or more bits set to 1 wire active send message one or more bits set to 1, new bit gets set to 1 wire active send message one or more bits set to 1, so ftware clears some (but not all) bits wire active send message one or more bits set to 1, software clears all bits wire inactive no action software clears one or more bits, and one or more bits are set on the same clock wire active send message
pci express* (d28:f0, f1) 174 datasheet 11.1.2.2 resuming from suspended state the root port can detect a wake event through the wake# signal and wake the system. when the root port detects a wake# assertion, an internal signal is sent to the power management controller of the intel? sch to cause the system to wake up. this internal message is not logged in any register, nor is an interrupt/gpe generated. 11.1.2.3 device initiated pm_pme message when the system has returned to a working state from a previous low power state, a device requesting service will send a pm_p me message continuously, until acknowledge by the root port. the root port will take di fferent actions depending upon whether this is the first pm_pme has been received, or whether a previous message has been received but not yet serviced by the operating system. if this is the first message received (rsts.ps - d28:f0/f1:offset 60h:bit 16 is cleared), the root port will set rsts.ps, an d log the pme requester id into rsts.rid (d28:f0/f1:offset 60h:bits 15:0). if an interrupt is enabled by rctl.pie (d28:f0/ f1:offset 5ch:bit 3), an interrupt will be ge nerated. this interrupt can be either a pin or an msi if msi is enabled by msi_ctl.msie (d28:f0/f1:offset 82h:bit 0). see section 11.1.2.4 for smi/sci generation. if this is a subsequent message received (rsts.ps is already set), the root port will set rsts.pp (d28:f0/f1:offset 60h:bit 17) and log the pme requester id from the message in a hidden register. no other action will be taken. when the first pme event is cleared by softwa re clearing rsts.ps, the root port will set rsts.ps, clear rsts.pp, and move the requ ester id from the hidden register into rsts.rid. if rctl.pie is set, generate an interrupt. if rctl.pie is not set, send over to the power management controller so that a gpe can be set. if messages have been logged (rsts.ps is set), and rctl.pie is later written from a 0 to a 1, and interrupt must be generated. this last condition handles the case where the message was received prior to the operating system re-enabling interru pts after resuming from a low power state. 11.1.2.4 smi/sci generation interrupts for power management events are not supported on legacy operating systems. to support power management on non-pci express aware operating systems, pm events can be routed to generate sci. to generate sci, mpc.pmce must be set. when set, a power management event w ill cause smscs.pmcs (d28:f0/f1:offset dch:bit 31) to be set. additionally, bios workarounds for power management can be supported by setting mpc.pmme (d28:f0/f1:offset d8h:bit 0). when this bit is set, power management events will set smscs.pmms (d28:f0/f1 :offset dch:bit 0), and smi # will be generated. this bit will be set regardless of whether interrupts or sci is enabled. the smi# may occur concurrently with an interrupt or sci. 11.1.3 hot-plug the intel? sch does not support pci express hot-plug.
datasheet 175 pci express* (d28:f0, f1) 11.1.4 additional clarifications 11.1.4.1 non-snoop cycles are not supported the intel? sch does not support no snoop cycles on pcie. dctl.ens can never be set. platform bios must disable generation of these cycles in all installed pcie devices. generation of a no snoop request by a pcie device may result in a protocol violation and lead to errors. for example, a no-snoop read by a device may be returned by a snooped completion, and this attribute difference, a violation of the specification, will cause the device to ignore the completion. 11.2 pci express* configuration registers table 29. pci express* register address map (sheet 1 of 2) offset mnemonic register name default type 00h?01h vid vendor identification 8086h ro 02h?03h did device identification see description ro 04h?05h pcicmd pci command 0000h r/w, ro 06h?07h pcists pci status 0010h r/wc, ro 08h rid revision identification see description ro 09h?0bh cc class codes 060400h ro 0ch cls cache line size 00h r/w 0dh plt primary latency timer 00h ro 0eh headtyp header type 81h ro 18h?1ah bnum bus number 000000h r/w 1bh slt secondary latency timer 0h ro 1ch?1dh iobl i/o base and limit 0000h r/w, ro 1eh?1fh ssts secondary status 0000h r/wc, ro 20h?23h mbl memory base and limit 00000000h r/w, ro 24h?27h pmbl prefetchable memory base and limit 00010001h r/w, ro 34h cap_ptr capabilities pointer 40h ro 3ch int_ln interrupt line 00h r/w 3dh int_pn interrupt pin see description ro 3eh?3fh bctrl bridge control 0000h r/w, ro 40h pcie_capid pci express capability id 10 ro 41h nxt_ptr1 next item pointer #1 90h ro 42h?43h pciecap pci express capabilities 0041 r/wo, ro 44h?47h dcap device capabilities 00000fe0h ro
pci express* (d28:f0, f1) 176 datasheet note: address locations that are not shown should be treated as reserved. 48h?49h dctl device control 0000h r/w, ro 4ah?4bh dsts device status 0010h r/wc, ro 4ch?4fh lcap link capabilities 00054c11h ro, r/wo 50h?51h lctl link control 0000h r/w, wo, ro 52h?53h lsts link status see description ro 54h?57h slcap slot capabilities 00000060h r/wo, ro 58h?59h slctl slot control 0000h r/w, ro 5ah?5bh slsts slot status see description r/wc, ro 5ch?5dh rctl root control 0000h r/w, ro 5eh rcap root capabilities xxxxh ro 60h?63h rsts root status 00000000h r/wc, ro 90h sv_capid subsystem vendor capability id 0dh ro 91h nxt_ptr3 next item pointer #3 a0h ro 94h?97h svid subsystem vendor identification 00h r/wo a0h pm_capid power management capability id 01h ro a1h nxt_ptr4 next item pointer #4 00h ro a2h?a3h pm_cap power management capabilities c802h ro a4?a7h pm_cntl_sts power management control/ status 00000000h r/w, ro d8?dbh mpc miscellaneous port configuration 00110000h r/w, ro dc?dfh smscs smi/sci status 00000000h r/wc, ro fch?ffh fd function disable 00000000h r/w, ro table 29. pci express* register address map (sheet 2 of 2) offset mnemonic register name default type
datasheet 177 pci express* (d28:f0, f1) 11.2.1 vid?vendor iden tification register address offset: 00h ? 01h attribute: ro default value: 8086h size: 16 bits 11.2.2 did?device identification register address offset: 02h?03h attribute: ro default value: see description size: 16 bits bit default and access description 15:0 8086h ro vendor id (vid): this is a 16-bit value assigned to intel. bit default and access description 15:0 see description ro device id (did) : this is a 16-bit value assigned to the intel? sch pci express controller. port 1 = 8110h port 2 = 8112h
pci express* (d28:f0, f1) 178 datasheet 11.2.3 pcicmd?pci command register address offset: 04h?05h attribute: r/w, ro default value: 0000h size: 16 bits bit default and access description 15:11 0h ro reserved 10 0 r/w interrupt disable (id) : this bit disables pin- based intx# interrupts on enabled hot-plug and power management events. 0 = internal intx# messages are genera ted if there is an interrupt for hot-plug or power management. 1 = internal intx# messages will not be generated. this bit does not effect interrupt forwarding from devices connected to the root port. assert_intx and deassert_intx messages will still be forwarded to the internal interrup t controllers if this bit is set. 9 0 ro reserved 8 0 r/w serr# enable (see) : hardwired to 0 to indi cate this port cannot generate serr# messages. 7:3 0h ro reserved 2 0 r/w bus master enable (bme) 0 = disable. all cycles from the device are master aborted 1 = enable. allows the root port to forward cycles onto the backbone from a pci express device. 1 0 r/w memory space enable (mse) 0 = disable. memory cycles within the range specified by the memory base and limit registers are ma ster aborted on the backbone. 1 = enable. allows memory cycles within the range specified by the memory base and limit registers ca n be forwarded to the pci express device. 0 0 r/w i/o space enable (iose) : this bit controls access to the i/o space registers. 0 = disable. i/o cycles within the range specified by the i/o base and limit registers are master aborted on the backbone. 1 = enable. allows i/o cycles within the range specified by the i/o base and limit registers can be forwar ded to the pci express device.
datasheet 179 pci express* (d28:f0, f1) 11.2.4 pcists?pci status register address offset: 06h ? 07h attribute: r/wc, ro default value: 0010h size: 16 bits note: there is a secondary status register (ssts) located at offset 1eh. 11.2.5 rid?revision identification register offset address: 08h attribute: ro default value: see description size: 8 bits bit default and access description 15 0 ro reserved 14 0 r/wc signaled system error (sse) 0 = no system error signaled. 1 = set when the root port signals a system error to the internal serr# logic. 13:5 000h ro reserved 4 1 ro capabilities list (clist) : hardwired to 1 indicating the presence of a capabilities list (at offset 34h) 3 0 ro interrupt status (is): indicates status of hot-plug and power management interrupts on the root po rt that result in intx# message generation. 0 = interrupt is deasserted. 1 = interrupt is asserted. this bit is set regardless of the st ate of pcicmd.inte rrupt disable bit (d28:f0/f1:04h:bit 10). 2:0 000b ro reserved bit default and access description 7:0 see description ro revision id (rid): refer to the intel ? system controller hub (intel ? sch) specification update for the value of the revision id register.
pci express* (d28:f0, f1) 180 datasheet 11.2.6 cc?class codes register address offset: 09h?0bh attribute: ro default value: 060400h size: 24 bits 11.2.7 cls?cache line size register address offset: 0ch attribute: r/w default value: 00h size: 8 bits 11.2.8 plt?primary latency timer register address offset: 0dh attribute: ro default value: 00h size: 8 bits bit default and access description 23:16 06h ro base class code (bcc) : 06h indicates the device is a bridge device. 15:8 04h ro sub class code (scc) : 04h indicates this is a pci-to-pci bridge. 7:0 00h ro programming interface (pi) : no specific register level programming interface defined. bit default and access description 7:0 00h r/w cache line size (cls) : this is read/write but contains no functionality, per the pci express base specification . bit default and access description 7:3 0h ro latency count (ct) : reserved per the pci express base specification. 2:0 000b ro reserved
datasheet 181 pci express* (d28:f0, f1) 11.2.9 headtyp?heade r type register address offset: 0eh attribute: ro default value: 81h size: 8 bits 11.2.10 bnum?bus number register address offset: 18?1ah attribute: r/w default value: 000000h size: 24 bits 11.2.11 slt?secondar y latency timer address offset: 1bh attribute: ro default value: 00h size: 8 bits bit default and access description 7 1 ro multi-function device (mfd) 0 = single-function device. 1 = multi-function device. 6:0 01h ro configuration layout (cl): indicates the header layout of the configuration space, which is a pci-to-p ci bridge, indicated by 1h in this field. bit default and access description 23:16 00h r/w subordinate bus number (sbbn) : indicates the highest pci bus number below the bridge. 15:8 00h r/w secondary bus number (scbn) : indicates the bus number the port. 7:0 00h r/w primary bus number (pbn) : indicates the bus number of the backbone. bit default and access description 7:0 00h ro secondary latency timer (slt) : reserved for a root port per the pci express base specification.
pci express* (d28:f0, f1) 182 datasheet 11.2.12 iobl?i/o base and limit register address offset: 1ch?1dh attribute: r/w, ro default value: 0000h size: 16 bits 11.2.13 ssts?secondary status register address offset: 1eh?1fh attribute: r/wc, ro default value: 0000h size: 16 bits bit default and access description 15:12 0h r/w i/o limit address (iola) : i/o base bits corresponding to address lines 15:12 for 4 kb alignment. bits 11:0 are assumed to be padded to fffh. 11:8 0h ro i/o limit address capability (iolc) : indicates that the bridge does not support 32-bit i/o addressing. 7:4 0h r/w i/o base address (ioba) : i/o base bits correspon ding to address lines 15:12 for 4 kb alignment. bits 11:0 are assumed to be padded to 000h. 3:0 0h ro i/o base address capability (iobc) : indicates that the bridge does not support 32-bit i/o addressing. bit default and access description 15 0 r/wc detected parity error (dpe) 0 = no error. 1 = the port received a poisoned tlp. 14 0 r/wc received system error (rse) 0 = no error. 1 = the port received an err_fa tal or err_nonfatal message from the device. 13 0 r/wc received master abort (rma) 0 = unsupported request not received. 1 = the port received a completion with ?unsupported request? status from the device. 12 0 r/wc received target abort (rta) 0 = completion abort not received. 1 = the port received a completion with ?completion abort? status from the device. 11 0 ro signaled target abort (sta) : reserved. the intel? sch cannot generate a target abort. 10:9 00 ro secondary devsel# timing status (sdts) : reserved per pci express base specification . 8 0 r/wc data parity error detected (dpd) 0 = conditions below did not occur. 1 = set when the bctrl.pere (d28:f0/f13e: bit 0) is set, and either of the following two conditions occurs: ? port receives completion marked poisoned. ? port poisons a write request to the secondary side. 7:0 00h ro reserved
datasheet 183 pci express* (d28:f0, f1) 11.2.14 mbl?memory base and limit register address offset: 20h?23h attribute: r/w, ro default value: 00000000h size: 32 bits accesses that are within the ranges specified in this register will be sent to the attached device if the memory space enable bit of pcicmd is set. accesses from the attached device that are outside the ranges specified will be forwarded to the internal intel? sch message network if the bus mast er enable bit of pcicmd is set. 11.2.15 pmbl?prefetchable memo ry base and limit register address offset: 24h?27h attribute: r/w, ro default value: 00000000h size: 32 bits accesses that are within the ranges specified in this register will be sent to the device if the memory space enable bit of pcicmd is set. the comparison performed is: pmbu32.pmb ad[63:32]:ad[31:20] pmlu32.pml. accesses from the device that are outside th e ranges specified will be forwarded to the backbone if the bus master enable bit of pcicmd is set. bit default and access description 31:20 000h r/w memory limit (ml): these bits are compared with bits 31:20 of the incoming address to determine the upper 1 mb aligned value of the range. 19:16 0h ro reserved 15:4 000h r/w memory base (mb) : these bits are compared with bits 31:20 of the incoming address to determine the lower 1 mb aligned value of the range. 3:0 0h ro reserved bit default and access description 31:20 000h r/w prefetchable memory limit (pml) : these bits are compared with bits 31:20 of the incoming address to determine the upper 1 mb aligned value of the range. 19:16 0h ro 64-bit indicator (i64l) : indicates support for 64-bit addressing 15:4 000h r/w prefetchable memory base (pmb) : these bits are compared with bits 31:20 of the incoming address to determine the lower 1 mb aligned value of the range. 3:0 0h ro 64-bit indicator (i64b) : indicates support for 64-bit addressing
pci express* (d28:f0, f1) 184 datasheet 11.2.16 cap_ptr?capabili ties pointer register address offset: 34h attribute: r0 default value: 40h size: 8 bits 11.2.17 int_ln?interrupt line register address offset: 3ch attribute: r/w default value: 00h size: 8 bits 11.2.18 int_pn?interrupt pin register address offset: 3dh attribute: ro default value: see bit description size: 8 bits bit default and access description 7:0 40h ro pointer (ptr) : indicates that the pointer for the first entry in the capabilities list is at offset 40h in configuration space. bit default and access description 7:0 00h r/w interrupt line (int_ln) : this data is not used by the intel? sch. it is used as a scratchpad register to co mmunicate to softwa re the interrupt line that the interrupt pin is connected to. bit default and access description 7:0 0xh ro interrupt pin (ipin) : this value tells the software which interrupt pin each pci express port uses. the upper 4 bits are hardwire d to 0000b; bits 3:0 are determined by th e interrupt pin default values programmed in the memory-mapped configurat ion space as follows: port 1 d28ip.p1ip (offset 310ch, bits 3:0) port 2 d28ip.p2ip (offset 310ch, bits 7:4) note: this does not determine the mapping to the pirq pins.
datasheet 185 pci express* (d28:f0, f1) 11.2.19 bctrl?bridge control register address offset: 3eh?3fh attribute: ro, r/w default value: 0000h size: 16 bits bit default and access description 15:12 0h ro reserved 11 0 ro discard timer serr# enable (dtse) : reserved per pci express base specification, revision 1.0a 10 0 ro discard timer status (dts) : reserved per pci express base specification, revision 1.0a. 9 0 ro secondary discard timer (sdt) . reserved per pci express base specification, revision 1.0a. 8 0 ro primary discard timer (pdt) : reserved per pci express base specification, revision 1.0a. 7 0 ro fast back to back enable (fbe) : reserved per pci express base specification, revision 1.0a. 6 0 r/w secondary bus reset (sbr) : triggers a hot reset on the pci express port. 5 0 ro master abort mode (mam) : reserved per express specification. 4 0 r/w vga 16-bit decode (v16) 0 = vga range is enabled. 1 = the i/o aliases of the vga range (s ee bctrl:ve definition in bit 3) are not enabled, and only the ba se i/o ranges can be decoded. 3 0 r/w vga enable (ve) 0 = the ranges below will not be cl aimed off the backbone by the root port. 1 = the following ranges will be claime d off the backbone by the root port: ? memory ranges a0000h?bffffh ? i/o ranges 3b0h ? 3bbh and 3c0h ? 3dfh, and all aliases of bits 15:10 in any combination of 1s 2 0 r/w isa enable (ie) : this bit only applies to i/ o addresses that are enabled by the i/o base and i/o limit register s and are in the first 64 kb of pci i/o space. 0 = the root port will not block any forwarding from the backbone as described below. 1 = the root port will block any fo rwarding from the backbone to the device of i/o transactions addressing the last 768 bytes in each 1 kb block (offsets 100h to 3ffh). 1 0 r/w serr# enable (se) 0 = the messages described below ar e not forwarded to the backbone. 1 = err_cor, err_nonfatal, and err_fatal messages received are forwarded to the backbone. 0 0 r/w parity error response enable (pere) 0 = poisoned write tlps and completions indicating poisoned tlps will not set the ssts.dpd (d28:f0/f1:1eh, bit 8). 1 = poisoned write tlps and completions indicating poisoned tlps will set the ssts.dpd (d28:f0/f1:1eh, bit 8).
pci express* (d28:f0, f1) 186 datasheet 11.2.20 pcie_capid?pci expres s capability id register address offset: 40h attribute: ro default value: 10h size: 8 bits 11.2.21 nxt_ptr1?next item pointer #1 register address offset: 41h attribute: ro default value: 90h size: 8 bits 11.2.22 pciecap?pci expres s capabilities register address offset: 42h?43h attribute: ro, r/wo default value: 0041h size: 16 bits bit default and access description 7:0 10h ro capability id (cid) : this field indicates this is a pci express capability. bit default and access description 7:0 90h ro next capability (next): this field indicates the location of the next capability. bit default and access description 15:14 00b ro reserved 13:9 00h ro interrupt message number (imn) : the intel? sch does not have multiple msi interrupt numbers. 8 0 r/wo slot implemented (si) : indicates whether the root port is connected to a slot. slot support is platform specific . bios programs this field, and it is maintained until a platform reset. 7:4 4h ro device/port type (dt) : this field indicates this is a pci express root port. 3:0 1h ro capability version (cv) : this field indicates pci express 1.0.
datasheet 187 pci express* (d28:f0, f1) 11.2.23 dcap?device ca pabilities register address offset: 44h?47h attribute: ro default value: 00008fc0h size: 32 bits bit default and access description 31:28 0h ro reserved 27:26 00b ro captured slot power limit scale (csps) : not supported. 25:18 00h ro captured slot power limit value (cspv): not supported. 17:16 00b ro reserved 15 1 ro role based error reporting (rber): indicates that this device implements the functionality define d in the error reporting ecn as required by the pci express 1.1 specification. 14 0 ro power indicator present (pip) : this bit indicates no power indicator is present on the root port. 13 0 ro attention indicator present (aip) : this bit indicates no attention indicator is present on the root port. 12 0 ro attention button present (abp) : this bit indicates no attention button is present on the root port. 11:9 111b ro endpoint l1 acceptable latency (e1al) : this field indicates more than 4 s. this field essentially has no me aning for root port s since root ports are not endpoints. 8:6 111b ro endpoint l0 acceptable latency (e0al) : this field indicates more than 64 s. this field essentially has no me aning for root ports since root ports are not endpoints. 5 0 ro extended tag field supported (etfs) : this bit indicates that 8-bit tag fields are supported. 4:3 00b ro phantom functions supported (pfs) : no phantom functions supported. 2:0 000b ro max payload size supported (mps) : this field indicates the maximum payload size supported is 128 bytes.
pci express* (d28:f0, f1) 188 datasheet 11.2.24 dctl?device control register address offset: 48h?49h attribute: r/w, ro default value: 0000h size: 16 bits bit default and access description 15 0 ro reserved 14:12 000b ro max read request size (mrrs) : hardwired to 0. 11 0 ro enable no snoop (ens) : not supported. the root port will never issue non-snoop requests. 10 0 r/w aux power pm enable (apme) : the os will set this bit to 1 if the device connected has detected aux power. it has no effect on the root port otherwise. 9 0 ro phantom functions enable (pfe) : not supported. 8 0 ro extended tag field enable (etfe) : not supported. 7:5 000b r/w max payload size (mps) : the root port only supports 128-b payloads, regardless of the programming of this field. 4 0 ro enable relaxed ordering (ero) : not supported. 3 0 r/w unsupported request reporting enable (ure) : 0 = the root port will ignore unsupported request errors. 1 = allows signaling err_nonfatal, err_fatal, or err_cor to the root control register when dete cting an unmasked unsupported request (ur). an err_cor is signaled when a unmasked advisory non-fatal ur is received. an err_fatal, err_or nonfatal, is sent to the root control register when an uncorrectable non-advisory ur is received with the se verity set by the uncorrectable error severity register. 2 0 r/w fatal error reporting enable (fee) : 0 = the root port will ignore fatal errors. 1 = enables signaling of err_fatal to the root control register due to internally detected erro rs or error messages re ceived across the link. other bits also control the full scope of related error reporting. 1 0 r/w non-fatal error reporting enable (nfe) : 0 = the root port will ignore non-fatal errors. 1 = enables signaling of err_nonfatal to the root control register due to internally detected errors or error messages re ceived across the link. other bits also control the fu ll scope of related error reporting. 0 0 r/w correctable error reporting enable (cee) : 0 = the root port will ig nore correctable errors. 1 = enables signaling of err_corr to the root control register due to internally detected erro rs or error messages re ceived across the link. other bits also control the full scope of related error reporting.
datasheet 189 pci express* (d28:f0, f1) 11.2.25 dsts?device status register address offset: 4ah?4bh attribute: r/wc, ro default value: 0010h size: 16 bits bit default and access description 15:6 00h ro reserved 5 0 ro transactions pending (tdp) : this bit has no meaning for the root port since only one transaction may be pendin g to the intel? sch, so a read of this bit cannot occur until it has already returned to 0. 4 1 ro aux power detected (apd): the root port contains aux power for wake up. 3 0 r/wc unsupported request detected (urd) : this bit indicates an unsupported request was detected. 2 0 r/wc fatal error detected (fed) : this bit indicates a fatal error was detected. 0 = no fatal errors have occurred. 1 = a fatal error occurred from a data link protocol error, link training error, buffer overflow, or malformed tlp. 1 0 r/wc non-fatal error detected (nfed) : this bit indicates a non-fatal error was detected. 0 = non-fatal has not occurred. 1 = a non-fatal error occurred from a poisoned tlp, unexpected completions, unsupported requests , completer abort, or completer timeout. 0 0 r/wc correctable error detected (ced) : this bit indicates a correctable error was detected. 0 = correctable has not occurred. 1 = the port received an internal co rrectable error from receiver errors/ framing errors, tlp crc error, dllp crc error, replay num rollover, replay timeout.
pci express* (d28:f0, f1) 190 datasheet 11.2.26 lcap?link capa bilities register address offset: 4ch ? 4fh attribute: r/wo, ro default value: 00054c11h size: 32 bits bit default and access description 31:24 00h ro port number (pn) : indicates the port number for the root port. this value is different for each implemen ted port. port 1 = 01h. port 2 = 02h. 23:21 00b ro reserved 20 1b ro link active reporting capable (larc) : hardwired to 1 to indicate that this port supports the optional capability of reporting the dl_active state of the data link control and management state machine. 19 0b ro reserved 18 1 ro clock power management (cpm): indicates clock power management is supported. 17:15 010b ro l1 exit latency (el1) : set to 010b to indicate an exit latency of 2 s to 4 s. 14:12 100b ro l0s exit latency (el0) : indicates an exit latency based upon common-clock configuration. 0 = use mpc.ucel. 1 = use mpc.ccel 11:10 11b r/wo active state link pm support (apms) : indicates what level of active state link power management is supported on the root port. 11b = both l0s and l1 entry are supported. 9:4 01h ro maximum link width (mlw) : single lane only 3:0 1h ro maximum link speed (mls) . set to 1h to indicate the link speed is 2.5 gb/s.
datasheet 191 pci express* (d28:f0, f1) 11.2.27 lctl?link control register address offset: 50h-51h attribute: r/w, wo, ro default value: 0000h size: 16 bits bit default and access description 15:9 00h ro reserved 8 0 r/w clockreq# enable (ce) this bit must always be cleared to 0. 7 0 r/w extended synch (es) 0 = extended sy nch disabled. 1 = forces extended transmission of fts ordered sets in fts and extra ts2 at exit from l1 prior to entering l0. 6 0 r/w common clock conf iguration (ccc) 1 = the intel? sch and device are op erating with a distributed common reference clock. 5 0 r0/wo retrain link (rl) : when set, the root port wi ll train its downstream link. this bit always returns '0' when read . software uses lsts.lt and lsts.lte to check the status of training. 4 0 r/w link disable (ld) 0 = link enabled. 1 = the root port will disable the link. 3 0 ro read completion bo undary control (rcbc) : indicates the read completion boundary is 64 bytes. 2 0 ro reserved 1:0 00b r/w active state link pm control (apmc) : indicates whethe r the root port should enter l0s or l1 or both. bits definition 00b disabled 01b l0s entry is enabled 10b l1 entry is enabled 11b l0s and l1 entry enabled
pci express* (d28:f0, f1) 192 datasheet 11.2.28 lsts?link status register address offset: 52h?53h attribute: ro default value: see bit description size: 16 bits bit default and access description 15:14 00b ro reserved 13 0 ro data link layer active (dlla) 0 = data link control and management state machine is not in the dl active state 1 = data link control and management state machine is in the dl active state 12 1 ro slot clock conf iguration (scc) 1 = indicate that the intel? sch uses the same reference clock as on the platform and does not generate its own clock. 11 0 ro link training (lt) : not supported. hardwired to 0. 10 0 ro link training error (lte) : the root port sets this bit whenever link training is occurring. it clears the bi t upon completion of link training. 9:4 00h ro negotiated link width (nlw) : may only take the value of a single link (01h). the value of this register is undefined if the link has not successfully trained. 3:0 1h ro link speed (ls) : this field indicates the ne gotiated link speed of the given pci express link. 01h = link speed is 2.5 gb/s.
datasheet 193 pci express* (d28:f0, f1) 11.2.29 slcap?slot ca pabilities register address offset: 54h ? 57h attribute: r/wo, ro default value: 00000060h size: 32 bits bit default and access description 31:19 0000h r/wo physical slot number (psn) : this is a value that is unique to the slot number. bios sets this field and it remains set until a platform reset. 18:17 00b ro reserved 16:15 00b r/wo slot power limit scale (sls) : specifies the scale used for the slot power limit value. bios se ts this field and it remains set until a platform reset. 14:7 00h r/wo slot power limit value (slv) : these bits, in conjunction with sls, specify the upper limit on power su pplied by the slot. the two values together, slv and sls indicate the am ount of power in watts allowed for the slot. bios sets this field and it remains set until a platform reset. 6 1 ro hot plug capable (hpc) 1 = indicates that hot-plug is supported. 5 1 ro hot plug surprise (hps) 1 = indicates the device may be removed from the slot without prior notification. 4 0 ro power indicator present (pip) 0 = indicates that a power indicator led is not present for this slot. 3 0 ro attention indicator present (aip) 0 = indicates that an atte ntion indicator led is not present for this slot. 2 0 ro mrl sensor present (msp) 0 = indicates that an mr l sensor is not supported 1 0 ro power controller present (pcp) 0 = indicates that a power controller is not supported for this slot. 0 0 ro attention button present (abp) 0 = indicates that an at tention button is not supported for this slot.
pci express* (d28:f0, f1) 194 datasheet 11.2.30 slctl?slot control register address offset: 58h ? 59h attribute: r/w, ro default value: 0000h size: 16 bits bit default and access description 15:13 000b ro reserved 12 0 r/w link active changed enable (lace): when set, this field enables generation of a hot plug interrupt wh en the data link layer link active field (d28:f0/f1:52h:bit 13) is changed. 11 0 ro reserved 10 0 ro power controller control (pcc) : this bit has no meaning for module based hot-plug. 9:8 00b r/w power indicator control (pic) : when read, the current state of the power indicator is returned. wh en written, the appropriate power_indicator_* messages are sent. defined encodings are: 7:6 00b r/w attention indicator control (aic) : when read, the current state of the attention indicator is returned. when written, the appropriate attention_indicator_* messages ar e sent. defined encodings are the same as the pic bits above. 5 0 r/w hot plug interrupt enable (hpe) 0 = hot plug interrupts based on hot-plug events is disabled. 1 = enables generation of a hot-plug interrupt on enabled hot-plug events. 4 0 r/w command completed interrupt enable (cce) 0 = hot plug interrupts based on command completions is disabled. 1 = enables the generation of a hot- plug interrupt when a command is completed by the ho t-plug controller. 3 0 r/w presence detect changed enable (pde) 0 = hot plug interrupts based on presence detect logic changes is disabled. 1 = enables the generation of a hot-plug interrupt or wake message when the presence detect logic changes state. 2 0 r/w mrl sensor changed enable (mse) 0 = indicates that an mrl sensor is not supported. 1 0 r/w power fault detected enable (pfe) 0 = pfe not supported. 0 0 r/w attention button pressed enable (abe) : abe is not supported, but is read/write for ease of im plementation and to easily draft off of the pci- express specification. bits definition 00b reserved 01b on 10b blink 11b off
datasheet 195 pci express* (d28:f0, f1) 11.2.31 slsts?slot status register address offset: 5ah ? 5bh attribute: r/wc, ro default value: 0000h size: 16 bits bit default and access description 15:9 00h reserved 8 0 r/wc link active state changed (lasc) : this bit is set when the value reported in data link layer link acti ve field of the link status register (d28:f0/f1:52h:bit 13) is changed. in response to a data link layer state changed event, softwa re must read data link layer link active field of the link status register to determine if the link is active before initiating configuration cycles to the hot plugged device. 7 0 ro reserved 6 see description ro presence detect state (pds) : if xcap.si (d28:f0/f1:42h:bit 8) is set (indicating that this root port spawns a sl ot), then this bit: 0 = indicates the slot is empty. 1 = indicates the slot has a device connected. otherwise, if xcap.si is cleared, this bit is always set (1). 5 0 ro mrl sensor state (ms): reserved as the mrl sensor is not implemented. 4 0 ro command completed (cc) : hardcoded to 0. these messages are not supported. 3 0 r/wc presence detect changed (pdc) 0 = no change in the pds bit. 1 = the pds bit changed states. 2 0 ro mrl sensor changed (msc) : reserved as the mrl sensor is not implemented. 1 0 ro power fault detected (pfd) : reserved as a power controller is not implemented. 0 0 ro attention button pressed (abp) : hardcoded to 0. attention button messages are not supported.
pci express* (d28:f0, f1) 196 datasheet 11.2.32 rctl?root control register address offset: 5ch ? 5dh attribute: ro, r/w default value: 0000h size: 16 bits bit default and access description 15:4 000h ro reserved 3 0 r/w power management event interrupt enable (pie) 0 = interrupt generation disabled. 1 = interrupt generation enabled when pcists.is is in a set state (either due to a 0 to 1 transition, or due to this bit being set with rsts.is already set). 2 0 r/w system error on fatal error enable (sfe) 0 = an serr# will not be generated. 1 0 r/w system error on non-fatal error enable (sne) 0 = an serr# will not be generated. 0 0 r/w system error on correctable error enable (sce) 0 = an serr# will not be generated.
datasheet 197 pci express* (d28:f0, f1) 11.2.33 rcap?root capabilities address offset: 5eh attribute: ro default value: 0000h size: 16 bits 11.2.34 rsts?root status register address offset: 60h ? 63h attribute: r/wc, ro default value: 00000000h size: 32 bits bit default and access description 15:1 000h ro reserved 0 0b ro crs software visibility (csv): this bit is not supported by the intel? sch. this bit, when set, indicates that the root port is capable of returning configuration request retry status (c rs) completion status to software. bit default and access description 31:18 0000h ro reserved 17 0 ro pme pending (pp) : hardcoded to 0. 16 0 r/wc pme status (ps) 0 = pme was not asserted. 1 = pme was asserted by the requestor id in rid. subsequent pmes are kept pending until this bit is cleared. 15:0 0 ro pme requestor id (rid) : indicates the pci requestor id of the last pme requestor. valid only when ps is set.
pci express* (d28:f0, f1) 198 datasheet 11.2.35 rcap?root capa bilities register address offset: 5eh attribute: ro default value: 0000h size: 16 bits 11.2.36 sv_capid?subsystem vend or capability id register address offset: 90h attribute: ro default value: 0dh size: 8 bits 11.2.37 nxt_ptr3?next item pointer #3 register address offset: 91h attribute: ro default value: a0h size: 8 bits 11.2.38 svid?subsystem vendor identification register address offset: 94h ? 97h attribute: r/wo default value: 0000h size: 32 bits bit default and access description 15:1 0000h ro reserved 0 0 ro software visibility of configuration retry (svcr) : maintained for compatibility bit default and access description 7:0 0dh ro capability identifier (cid) : value of 0dh indicates this is a pci bridge subsystem vendor capability. bit default and access description 7:0 a0h ro next capability (next): this field indicates the location of the next capability. bit default and access description 31:16 00h r/wo subsystem identifier (sid) : this field indicate s the subsystem as identified by the vendor. this field is write once and is locked down until a bridge reset occurs. 15:0 00h r/wo subsystem vendor identifier (svid) : this field indicates the manufacturer of the subsyste m. this field is write once and is locked down until a bridge reset occurs.
datasheet 199 pci express* (d28:f0, f1) 11.2.39 pci?power management capability id register address offset: a0h attribute: ro default value: 01h size: 8 bits 11.2.40 nxt_ptr4?next item pointer #4 register address offset: a1h attribute: ro default value: 00h size: 8 bits 11.2.41 pm_cap?power manageme nt capabilities register address offset: a2h ? a3h attribute: ro default value: c802h size: 16 bits bit default and access description 7:0 01h ro capability identifier (cid) : value of 01h indicates this is a pci power management capability. bit default and access description 7:0 00h ro next capability (next): this field indicates this is the last capability in the list. bit default and access description 15:11 11001b ro pme_support (pmes) : this field indicates pme# is supported for states d0, d3 hot and d3 cold . the root port does not generate pme#, but reporting that it does is necessary for some legacy operating systems to enable pme# in devices connec ted behind this root port. 10 0 ro d2_support (d2s) : the d2 state is not supported. 9 0 ro d1_support (d1s): the d1 state is not supported. 8:6 000b ro aux_current (ac) : reports 375 ma maximum suspend well current required when in the d3 cold state. 5 0 ro device specific initialization (dsi) : this bit indicates that no device- specific initialization is required. 4 0 ro reserved 3 0 ro pme clock (pmec) : this bit indicates that pci clock is not required to generate pme#. 2:0 010b ro version (vs) : this field indicates support for revision 1.1 of the pci power management specification .
pci express* (d28:f0, f1) 200 datasheet 11.2.42 pm_cntl_sts?power mana gement control and status register address offset: a4h ? a7h attribute: r/w, ro default value: 00000000h size: 32 bits bit default and access description 31:16 00h ro reserved 15 0 ro pme status (pmes) : this bit indicates a pme was received on the downstream link. 14:9 00h ro reserved 8 0 r/w pme enable (pmee) : this bit indicates pme is enabled. the root port takes no action on this bit, but it must be r/w for some legacy operating systems to enable pme# on device s connected to this root port. this bit is sticky and resides in the re sume well. the rese t for this bit is rsmrst# which is not assert ed during a warm reset. 7:2 00h ro reserved 1:0 00b r/w power state (ps) : this field is used both to determine the current power state of the root port and to set a new power state. the values are: 00 = d0 state 11 = d3 hot state note: when in the d3 hot state, the controller?s configuration space is available, but the i/o and memo ry spaces are not. type 1 configuration cycles are also not accepted. interrupts are not required to be blocked as software will disable interrupts prior to placing the port into d3 hot . if software attempts to write a 10 or 01 to these bits, the write will be ignored.
datasheet 201 pci express* (d28:f0, f1) 11.2.43 mpc?miscellaneous po rt configuration register address offset: d8h ? dbh attribute: r/w, ro default value: 00110000h size: 32 bits bit default and access description 31 0 r/w power management sci enable (pmce) 0 = sci generation based on a powe r management event is disabled. 1 = enables the root port to generate sci whenever a power management event is detected. 30 0 r/w hot plug sci enable (hpce) 0 = sci generation based on a hot-plug event is disabled. 1 = enables the root port to generate sci whenever a hot-plug event is detected. 29 0 r/w link hold off (lho): when set, the port will not take any tlp. this is used during loopback mode to fi ll up the downstream queue. 28 0 r/w address translator enable (ate): used to enable address translation by the at bits in this regist er during loopback mode. 27:21 0h ro reserved 20:18 100b r/w unique clock exit latency (ucel) : l0s exit latency when lcap.ccc is cleared. 17:15 010b r/w common clock exit latency (ccel) : l0s exit latency lcap.ccc is set. 14:12 000b r/w reserved 11:8 0 r/w address translator (at) : during loopback, these bi ts are xor'd with bits [31:28] of the receive address, if the ate bit in this register is enabled. 7:2 0 ro reserved 1 0 r/w hot plug smi enable (hpme) 0 = smi generation based on a hot-plug event is disabled. 1 = enables the root port to generate smi whenever a hot-plug event is detected. 0 0 r/w power management smi enable (pmme) 0 = smi generation based on a powe r management event is disabled. 1 = enables the root port to genera te smi whenever a power management event is detected.
pci express* (d28:f0, f1) 202 datasheet 11.2.44 smscs?smi/sci status register address offset: dch ? dfh attribute: r/wc, ro default value: 00000000h size: 32 bits 11.2.45 fd?function disable register address offset: fch ? ffh attribute: r/w, r0 default value: 00000000h size: 32 bits bit default and access description 31 0 r/wc power management sci status (pmcs) : this bit is set if the pme control logic needs to ge nerate an interrupt, and this interrupt has been routed to generate an sci. 30 0 r/wc hot plug sci status (hpcs) : this bit is set if the hot-plug controller needs to generate an interrupt, and has this interrupt been routed to generate an sci. 29:5 000000h r/wc reserved 4 0 r/wc hot plug link active state changed smi status (hplas) : this bit is set when slsts.lasc (d28:f0/f1:5a, bi t 8) transitions from 0 to 1, and mpc.hpme (d28:f0/f1:d8h, bit 1) is set. when this bit is set, an smi# will be generated. 3:2 00b ro reserved 1 0 r/wc hot plug presence detect smi status (hppdm) : this bit is set when slsts.pdc (d28:f0/f1:5a, bit 3) tran sitions from 0 to 1, and mpc.hpme (d28:f0/f1:d8h, bit 1) is set. when this bit is set, an smi# will be generated. 0 0 r/wc power management smi status (pmms) : this bit is set when rsts.ps (d28:f0/f1:60h, bit 16) transitions from 0 to 1, and mpc.pmme (d28:f0/ f1:d8, bit 1) is set. bit default and access description 31:3 0 ro reserved 2 0 r/w clock gating disable (cgd) 0 = clock gating within this function is enabled. 1 = clock gating within this function is disabled. 1 0 ro reserved 0 0 r/w disable (d) 0 = this function is enabled. 1 = this function is disabled.
datasheet 203 uhci host controller (d29:f0, f1, f2) 12 uhci host controller (d29:f0, f1, f2) 12.1 functional description the intel? sch contains three controllers supporting the universal host controller interface (uhci). each universal host cont roller (uhc) includes a root hub with two separate usb 1.1 ports, for a total of 6 usb ports. ? overcurrent detection on all six usb ports is supported. the overcurrent inputs are not 5-v tolerant, and can be used as gpis if not needed. ? the uhcs are arbitrated differently than standard pci devices to improve arbitration latency. ? the uhcs use the analog front end (afe ) embedded cell that allows support for usb full-speed signaling rates, instead of usb i/o buffers. 12.1.1 bus protocol refer to the universal serial bus specification, revision 1.1 , chapter 8 for full details on the usb bus protocol. 12.1.2 usb interrupts there are two general groups of usb interrupt sources: those resulting from execution of transactions in the schedule, and those resulting from an intel? sch operation error. for more information on transaction-based and operational error-based interrupts, refer to chapter 4 of universal host controller interface specification, revision 1.1. when the intel? sch drives an interrupt for us b, it internally drives one of the virtual pirq# pins as configured by the interrupt pin and interrupt route registers defined for that device in the intel? sch root register complex. 12.1.3 usb power management the uhc can be put into a suspended state and its power can be removed. this requires that certain bits of information be retained in the resume power plane of the intel? sch so that a device on a port may wake the system. such a device may be a fax-modem, which will wake up the machine to receive a fax or take a voice message. the settings of the following bits in i/o sp ace will be maintained when the intel? sch enters the s3, s4, or s5 states.
uhci host controller (d29:f0, f1, f2) 204 datasheet when the intel? sch detects a resume event on any of its ports, it sets the corresponding usb_sts bit in acpi space. if usb is enabled as a wake/break event, the system wakes up and an sci generated. table 30. bits maintained in low power states register offset bit description command 00h 3 enter global suspend mode (egsm) status 02h 2 resume detect port status and control 10h and 12h 2 port enabled/disabled 6 resume detect 8low-speed device attached 12 suspend
datasheet 205 uhci host controller (d29:f0, f1, f2) 12.2 pci configuration registers note: address locations that are not shown should be treated as reserved. table 31. uhci controller pci regi ster address map (d29:f0/f1/f2) offset mnemonic register name default type 00h?01h vid vendor identification 8086h ro 02h?03h did device identification see description ro 04h?05h pcicmd pci command 0000h r/w, ro 06h?07h pcists pci status 0000h r/wc, ro 08h rid revision identification reserved ro 09h?0bh cc class codes 0c0300h ro 0dh mlt master latency timer 00h ro 0eh headtyp header type see description ro 20h?23h base base address 00000001h r/w, ro 2ch?2fh ssid subsystem identifiers see description r/wo 34h cap_ptr capabilities pointer 00h ro 3ch int_ln interrupt line 00h ro 3dh int_pn interrupt pi n see description ro 60h usb_relnum serial bus release number 10h ro c4h usb_res usb resume enable 00h r/w, ro fch fd function disable 00000000h ro. r/w
uhci host controller (d29:f0, f1, f2) 206 datasheet 12.2.1 vid?vendor iden tification register address offset: 00h ? 01h attribute: ro default value: 8086h size: 16 bits 12.2.2 did?device iden tification register address offset: 02h ? 03h attribute: ro default value: see bit description size: 16 bits 12.2.3 pcicmd?pci command register address offset: 04h ? 05h attribute: r/w, ro default value: 0000h size: 16 bits bit default and access description 15:0 8086 ro vendor id (vid) : this is a 16-bit value assigned to intel. bit default and access description 15:0 see description ro device id (did) : this is a 16-bit value assigned to the uhc. uhci #1 (d29:f0): 8114h uhci #2 (d29:f1): 8115h uhci #3 (d29:f2): 8116h bit default and access description 15:11 0 ro reserved 10 0 r/w interrupt disable 0 = enable. the function is able to ge nerate its interrupt to the interrupt controller. 1 = disable. the function is not ca pable of generati ng interrupts. pcists.is is not affected by the interrupt enable. 9:3 00h ro reserved 2 0 r/w bus master enable (bme) 0 = disable 1 = enable. the intel? sch can act as a master on the pci bus for usb transfers. 1 0 ro reserved 0 0 r/w i/o space enable (iose) : this bit controls access to the i/o space registers. 0 = disable 1 = enable accesses to the usb i/o re gisters. the base address register for usb should be programme d before this bit is set.
datasheet 207 uhci host controller (d29:f0, f1, f2) 12.2.4 pcists?pci status register address offset: 06h ? 07h attribute: ro default value: 0000h size: 16 bits 12.2.5 rid?revision identification register offset address: 08h attribute: ro default value: see description size: 8 bits 12.2.6 cc?class code register address offset: 09h?0bh attribute: ro default value: 0c0300h size: 24 bits bit default and access description 15:4 000h ro reserved 3 0 ro interrupt status : this bit reflects th e state of this func tion?s interrupt at the input of the enable/disable logic. 0 = interrupt is deasserted. 1 = interrupt is asserted. the value reported in this bit is inde pendent of the value in the interrupt enable bit. 2:0 000b ro reserved bit default and access description 7:0 see description ro revision id : refer to the intel ? system controller hub (intel ? sch) specification update for the value of the revision id register. bit default and access description 23:16 0ch ro base class code (bcc) : 0ch = serial bus controller. 8:15 03h ro sub class code (scc) : 03h = usb host controller. 7:0 00h ro programming interface (pi) : 00h = no specific register level programming interface defined.
uhci host controller (d29:f0, f1, f2) 208 datasheet 12.2.7 mlt?master latency timer register address offset: 0dh attribute: ro default value: 00h size: 8 bits 12.2.8 headtyp?header type register address offset: 0eh attribute: ro default value: see bit description size: 8 bits 12.2.9 base?base address register address offset: 20h ? 23h attribute: r/w, ro default value: 00000001h size: 32 bits 12.2.10 ssid?subsystem identifiers register this register matches the value written to the lpc bridge. bit default and access description 7:0 ro master latency timer (mlt) : hardwired to 00h. the usb controller is implemented internal to the intel? sc h and not arbitrated as a pci device. bit default and access description 7 see desc. ro multi-function device 0 = single-function device. 1 = multi-function device. (default) for uhci #2 and #3 (d29:f1 and f2 respectively) this register is hardwired to 00h. for uhci #1 (d 29:f0), bit 7 always reports 1. 6:0 00h ro configuration layout : hardwired to 00h, which indicates the standard pci configuration layout. bit default and access description 31:16 0000h ro reserved 15:5 000h r/w base address : bits 15:5 correspond to i/o address signals ad[15:5], respectively. this gives 32 bytes of relocatable i/o space. 4:1 000b ro reserved 0 1 ro resource type indicator (rte) : hardwired to 1 to indicate that the base address field in this register maps to i/o space.
datasheet 209 uhci host controller (d29:f0, f1, f2) 12.2.11 sid?subsystem id entification register address offset: 2eh ? 2fh attribute: r/wo default value: 0000h size: 16 bits 12.2.12 cap_ptr?capabilities pointer register address offset: 34h attribute: ro default value: 00h size: 8 bits 12.2.13 int_ln?interrupt line register address offset: 3ch attribute: ro default value: 00h size: 8 bits bit default and access description 15:0 r/wo subsystem id (sid) : bios sets the value in this register to identify the subsystem id. the sid register, in combination with the svid register (d29:f0/f1/f2:2c), enables the operating system to distinguish each subsystem from other(s). th e value read in this re gister is the same as what was written to the lpc?s ssid register. note: the software can write to this regist er only once per core well reset. writes should be done as a single, 16-bit cycle. bit default and access description 7:0 00h ro pointer (ptr): 00h indicates this device has no additional capabilities. bit default and access description 7:0 ro interrupt line (int_ln) : this data is not used by the intel? sch. it is to communicate to software the interr upt line that the interrupt pin is connected to.
uhci host controller (d29:f0, f1, f2) 210 datasheet 12.2.14 int_pn?interrupt pin register address offset: 3dh attribute: ro default value: see description size: 8 bits 12.2.15 usb_relnum?serial bus release number register address offset: 60h attribute: ro default value: 10h size: 8 bits 12.2.16 usb_res?usb resu me enable register address offset: c4h attribute: r/w, ro default value: 00h size: 8 bits this register is in the resume well. bit default and access description 7:0 see description ro interrupt line (int_ln) : this value tells the so ftware which interrupt pin each usb host controller uses. the upper 4 bits are hardwired to 0000b; the lower 4 bits are determine by the interrupt pin default values that are programmed in the memory -mapped configur ation space as follows: uhci #1 ? d29ip.u0p (chipset config registers:offset 3108h:bits 3:0) uhci #2 ? d29ip.u1p (chipset config registers:offset 3108h:bits 7:4) uhci #3 ? d29ip.u2p (chipset config registers:offset 3108h:bits 11:8) note: this does not determine the mapping to the pirq pins. bit default and access description 7:0 10h ro serial bus release number 10h = usb controller supports the usb specification , release 1.0. bit default and access description 7:2 0h ro reserved 1 0 r/w port0en : enable port 0 of the usb controller to respond to wakeup events. 0 = the usb controller will not look at this port for a wakeup event. 1 = the usb controller will monitor this port for remote wakeup and connect/disconnect events. 0 0 r/w port1en : enable port 1 of the usb controller to respond to wakeup events. 0 = the usb controller will not look at this port for a wakeup event. 1 = the usb controller will monitor this port for remote wakeup and connect/disconnect events.
datasheet 211 uhci host controller (d29:f0, f1, f2) 12.2.17 fd?function disable register address offset: fch attribute: r/w, ro default value: 00000000h size: 32 bits 12.3 i/o registers some of the read/write register bits that deal with changing the state of the usb hub ports function such that on read back they reflect the current state of the port, and not necessarily the state of the last write to the register. this allows the software to poll the state of the port and wait until it is in the proper state before proceeding. a host controller reset, global reset, or port rese t will immediately terminate a transfer on the affected ports and disable the port. this affects the usbcmd register, bit 4 and the port[7:0]sc registers, bits [12,6,2]. see individual bit descriptions for more detail. notes: 1. register offsets are with respect to base. 2. registers that are writable are word writab le only. byte writes to these registers. bit default and access description 31:3 0 ro reserved 2 0 r/w clock gating disable (cgd) 0 = clock gating within this function is enabled 1 = clock gating within this function is disabled 1 0 ro reserved 0 0 r/w disable (d) 0 = this function is enabled 1 = this function is disabled and the configuration space is not accessible. table 32. usb i/o registers offset 1 mnemonic register name default type 2 00h?01h usbcmd usb command 0000h r/w, ro 02h?03h usbsts usb status 0020h r/wc 04h?05h usbintr usb interrupt enable 0000h r/w 06h?07h frnum frame number 0000h r/w (see note ) 08h?0bh frbaseadd frame list base address undefined r/w 0ch sofmod start of frame modify 40h r/w 10h?11h portsc0 port 0 status/control 0080h r/wc, ro, r/w (see note ) 12h?13h portsc1 port 1 status/control 0080h r/wc, ro, r/w (see note )
uhci host controller (d29:f0, f1, f2) 212 datasheet 12.3.1 usbcmd?usb command register i/o offset: base + (00h ? 01h) attribute: r/w, ro default value: 0000h size: 16 bits the usb command register indicates the command to be executed by the serial bus host controller. writing to the register causes a command to be executed. the table following the bit description provides additi onal information on the operation of the run/stop and debug bits. bit default and access description 15:7 00h ro reserved 8 0 r/w loop back test mode: 0 = disable loop back test mode. 1 = the intel? sch is in loop back test mode. when both ports are connected together, a write to one port will be seen on the other port and the data will be st ored in i/o offset 18h. 7 0 r/w max packet (maxp) : this bit selects the maximum packet size that can be used for full speed bandwidth recl amation at the end of a frame. this value is used by the host controller to determine whether it should initiate another transaction based on the time remaining in the sof counter. use of reclamation packets larger than the programmed size will cause a babble error if executed during the critical window at frame end. the babble error results in the offending endpoint being stalled. software is responsible for ensuring that any pack et which could be executed under bandwidth reclamation be within this size limit. 0 = 32 bytes 1 = 64 bytes 6 0 r/w configure flag (cf) : this bit has no effect on th e hardware. it is provided only as a semaphore service for software. 0 = indicates that software has not co mpleted host controller configuration. 1 = hcd software sets this bit as the last action in the process of configuring the host controller. 5 0 r/w software debug (swdbg) : the swdbg bit must only be manipulated when the controller is in the stoppe d state. this can be determined by checking the hchalted bit in the usbsts register. 0 = normal mode. 1 = debug mode. in sw debug mode, th e host controller clears the run/ stop bit after the completion of each usb transaction. the next transaction is executed when software sets the run/stop bit back to 1. 4 0 r/w force global resume (fgr) : 0 = software resets this bit to 0 afte r 20 ms has elapsed to stop sending the global resume signal. at that ti me all usb devices should be ready for bus activity. the 1 to 0 transiti on causes the port to send a low speed eop signal. this bit will remain a 1 until the eop has completed. 1 = host controller sends the global resume signal on the usb, and sets this bit to 1 when a resume event (connect, disconnect, or k-state) is detected while in gl obal suspend mode.
datasheet 213 uhci host controller (d29:f0, f1, f2) 3 0 r/w enter global suspend mode (egsm) 0 = software resets this bit to 0 to come out of global suspend mode. software writes this bit to 0 at the same time that force global resume (bit 4) is written to 0 or after writing bit 4 to 0. 1 = host controller enters the global suspend mode . no usb transactions occur during this time. the host controller is able to receive resume signals from usb and interrupt the sy stem. software must ensure that the run/stop bit (bit 0) is clea red prior to sett ing this bit. 2 0 r/w global reset (greset) 0 = this bit is reset by the software after a minimum of 10 ms has elapsed as specified in chapter 7 of the usb specification. 1 = global reset. the host controller sends the global reset signal on the usb and then resets all of its logic, including the intern al hub registers. the hub registers are reset to thei r power on state. chip hardware reset has the same effect as global reset (bit 2), except that the host controller does not send the global reset on usb. 1 0 r/w host controller reset (hcreset) : the effects of hcreset on hub registers are slightly different from chip hardware reset and global usb reset. the hcreset affects bits [8,3 :0] of the port st atus and control register (portsc) of each port. hcreset resets the state machines of the host controller includin g the connect/disconnect state machine (one for each port). when the connect/discon nect state machine is reset, the output that signals connect/disconnect are negated to 0, effectively signaling a disconnect, even if a device is attached to the port. this virtual disconnect causes the port to be disabled. this di sconnect and disabling of the port causes bit 1 (connect status change) and bit 3 (port enable/disable change) of the portsc to get set. the disconnect also causes bit 8 of portsc to reset. about 64 bit times after hcreset goes to 0, the connect and low-speed detect will take place, and bits 0 and 8 of the portsc will change accordingly. 0 = reset by the host controller when the reset process is complete. 1 = reset. when this bit is set, the host controller module resets its internal timers, counters, state machines, et c. to their initial value. any transaction currently in progress on usb is immediately terminated. 0 0 r/w run/stop (rs) : when set to 1, the intel? sch proceeds with execution of the schedule. the intel? sch continues execution as long as this bit is set. when this bit is cleared, the intel? sch completes the current transaction on the usb and then halts. the hc halted bit in the status register indicates when the host contro ller has finished the transaction and has entered the stopped state. the host controller clears this bit when the following fatal errors oc cur: consistency check failure, pci bus errors. 0 = stop 1 = run note: this bit should only be cleared if there are no active transaction descriptors in the executable sche dule or software will reset the host controller prior to setting this bit again. bit default and access description
uhci host controller (d29:f0, f1, f2) 214 datasheet when the usb host controller is in software debug mode (usbcmd register bit 5=1), the single stepping software debug operation is as follows: to enter software debug mode: 1. hcd puts host controller in stop state by setting the run/stop bit to 0. 2. hcd puts host controller in debug mode by setting the swdbg bit to 1. 3. hcd sets up the correct command list and start of frame value for starting point in the frame list single step loop. 4. hcd sets run/stop bit to 1. 5. host controller executes next active td, sets run/stop bit to 0, and stops. 6. hcd reads the usbcmd register to check if the single step execution is completed (hchalted=1). 7. hcd checks results of td execution. go to step 4 to execute next td or step 8 to end software debug mode. 8. hcd ends software debug mode by setting swdbg bit to 0. 9. hcd sets up normal command list and frame list table. 10. hcd sets run/stop bit to 1 to resume normal schedule execution. in software debug mode, when the run/stop bit is set, the host controller starts. when a valid td is found, the run/stop bi t is reset. when the td is finished, the hchalted bit in the usbsts register (bit 5) is set. the sw debug mode skips over inactive tds an d only halts after an active td has been executed. when the last active td in a frame has been executed, the host controller waits until the next sof is sent and then fetc hes the first td of the next frame before halting. this hchalted bit can also be used outside of software debug mode to indicate when the host controller has detected the run/stop bit and has completed the current transaction. outside of the software debug mode, setting the run/stop bit to 0 always resets the sof counter so that when the run/ stop bit is set the host controller starts over again from the frame list location poin ted to by the frame list index (see frnum register description) rather than continuing where it stopped. table 33. run/stop, debug bit interaction swdb g (bit 5), run/stop (bit 0) operation swdbg (bit 5) run/stop (bit 0) description 00 if executing a command, the host controller completes the command and then stops. the 1.0 ms frame counter is reset and command list execution resumes from start of fr ame using the frame list pointer selected by the current value in the frnum register. (while run/ stop=0, the frnum register (bas e + 06h) can be reprogrammed). 01 execution of the command list resumes from start of frame using the frame list pointer selected by the current value in the frnum register. the host controller remains running until the run/stop bit is cleared (by software or hardware). 10 if executing a command, the host controller completes the command and then stops and the 1.0 ms fram e counter is frozen at its current value. all status are preserved. the host controller begins execution of the command list from where it le ft off when the run/stop bit is set. 11 execution of the command list resumes from where the previous execution stopped. the run/stop bit is set to 0 by the host controller when a td is being fetched. this ca uses the host controller to stop again after the execution of the td (single step). when the host controller has completed execution, the hc halted bit in the status register is set.
datasheet 215 uhci host controller (d29:f0, f1, f2) 12.3.2 usbsts?usb status register i/o offset: base + (02h ? 03h) attribute: r/wc, ro default value: 0020h size: 16 bits this register indicates pending interrupts and various states of the host controller. the status resulting from a transaction on the serial bus is not indicated in this register. bit default and access description 15:6 00h ro reserved 5 1 r/w hchalted 0 = software clears this bit by writing a 1 to it. 1 = the host controller has stopped executing as a result of the run/stop bit being set to 0, either by software or by the host controller hardware (debug mode or an internal error). default. 4 0 r/wc host controller process error 0 = software clears this bit by writing a 1 to it. 1 = the host controller has detected a fatal error. this indicates that the host controller suffered a consistency check failure while processing a transfer descriptor. an example of a consistency check failure would be finding an invalid pid field wh ile processing the packet header portion of the td. when this error occurs, the host controller clears the run/stop bit in the command register (d29:f0/f1/f2:base + 00h, bit 0) to prevent further schedule execution. a hardware interrupt is generated to the system. 3 0 r/wc host system error 0 = software clears this bit by writing a 1 to it. 1 = a serious error occurred during a host system access involving the host controller module. in a pci system, conditions that set this bit to 1 include pci parity error, pci mast er abort, and pci target abort. when this error occurs, the host cont roller clears the run/stop bit in the command register to prevent fu rther execution of the scheduled tds. a hardware interrupt is generated to the system. 2 0 r/wc resume detect (rsm_det) 0 = software clears this bit by writing a 1 to it. 1 = the host controller received a ?resume? signal from a usb device. this is only valid if the host cont roller is in a global suspend state (command register, d29:f0/f1/f2:base + 00h, bit 3 = 1). 1 0 r/wc usb error interrupt 0 = software clears this bit by writing a 1 to it. 1 = completion of a usb transaction resu lted in an error condition (e.g., error counter underflow). if the td on which the error interrupt occurred also had its ioc bit (d29:f 0/f1/f2:base + 04h, bit 2) set, both this bit and bit 0 are set. 0 0 r/wc usb interrupt (usbint) 0 = software clears this bit by writing a 1 to it. 1 = the host controller sets this bit when the cause of an interrupt is a completion of a usb transaction whose transfer descriptor had its ioc bit set. also set when a short packet is detected (actual length field in td is less than maximum length field in td), an d short packet detection is enabled in that td.
uhci host controller (d29:f0, f1, f2) 216 datasheet 12.3.3 usbintr?usb interrupt enable register i/o offset: base + (04h ? 05h) attribute: r/w, ro default value: 0000h size: 16 bits this register enables and disables reporting of the corresponding interrupt to the software. when a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. fatal errors (host controller processor error, (d29:f0/f1/ f2:base + 02h, bit 4, usbsts register) cann ot be disabled by the host controller. interrupt sources that are disabled in this register still appear in the status register to allow the software to poll for events. bit default and access description 15:5 0000h ro reserved 4 0 r/w scratchpad (sp) 3 0 r/w short packet interrupt enable 0 = disabled 1 = enabled 2 0 r/w interrupt on complete enable (ioc) 0 = disabled 1 = enabled 1 0 r/w resume interrupt enable 0 = disabled 1 = enabled 0 0 r/w timeout/crc interrupt enable 0 = disabled 1 = enabled
datasheet 217 uhci host controller (d29:f0, f1, f2) 12.3.4 frnum?frame number register i/o offset: base + (06 ? 07h) attribute: r/w (writes must be word writes) default value: 0000h size: 16 bits bits [10:0] of this register contain the cu rrent frame number that is included in the frame sof packet. this register reflects the count value of the internal frame number counter. bits [9:0] are used to select a pa rticular entry in the frame list during scheduled execution. this register is updated at the end of each frame time. this register must be written as a word. by te writes are not supported. this register cannot be written unless the host controller is in the stopped state as indicated by the hchalted bit (d29:f0/f1/f2:base + 02h, bit 5). a write to this register while the run/ stop bit is set (d29:f0/f1/f2:base + 00h, bit 0) is ignored. 12.3.5 frbaseadd?frame list base address register i/o offset: base + (08h ? 0bh) attribute: r/w default value: undefined size: 32 bits this 32-bit register contains the beginning address of the frame list in the system memory. hcd loads this register prior to starting the schedule execution by the host controller. when written, only the upper 20 bits are used. the lower 12 bits are written as 0s (4 kb alignment). the contents of th is register are combined with the frame number counter to enable the host contro ller to step through the frame list in sequence. the two least significant bits are always 00. this requires dword-alignment for all list entries. this configuration supports 1024 frame list entries. bit default and access description 15:11 00h ro reserved 10:0 000h r/w frame list current index/frame number : this field provides the frame number in the sof frame. the value in this register increments at the end of each time frame (approximat ely every 1 ms). in addition, bits 9:0 are used for the frame list curre nt index and correspond to memory address signals 11:2. bit default and access description 31:12 r/w base address : these bits correspond to me mory address signals 31:12, respectively. 11:0 000h ro reserved
uhci host controller (d29:f0, f1, f2) 218 datasheet 12.3.6 sofmod?start of frame modify register i/o offset: base + (0ch) attribute: r/w default value: 40h size: 8 bits this register is used to modify the value us ed in the generation of sof timing on the usb. when a new value is written to bits 7: 0, the sof timing of the next frame will be adjusted. this feature can be used to adjust out any offset from the clock source that generates the clock that drives the sof counter. this register can also be used to maintain real time synchronization with the rest of the system so that all devices have the same sense of real time. using this register, the frame length can be adjusted across the full range required by the usb spec ification. the initial programmed value is system dependent based on the accuracy of hardware usb clock and is initialized by system bios. it may be reprogrammed by us b system software at any time. the value will take effect from the beginning of the next frame. this register is reset upon a host controller reset or global reset. software must maintain a copy of the value for reprogramming if necessary. bit default and access description 70, roreserved 6:0 40h r/w sof timing value : guidelines for the modification of frame time are contained in chapter 7 of the usb specification. the sof cycle time (number of sof counter clock periods to generate a sof frame length) is equal to 11936 + value in this field. the default value is decimal 64 which gives a sof cycle time of 12000. for a 12-mhz sof counter clock input, this produces a 1-ms frame period. the following table indicates what sof timing value to program into this field for a certain frame period. frame length (# 12 mhz clocks) (decimal) sof timing value (this register) (decimal) 11936 0 11937 1 ?? 11999 63 12000 64 ?? 12063 127
datasheet 219 uhci host controller (d29:f0, f1, f2) 12.3.7 portsc[0,1]?port stat us and control registers i/o offset: port 0,2,4: base + (10h ? 11h) attribute: r/wc, ro, port 1,3,5: base + (12h ? 13h) r/w (word writes only) default value: 0080h size: 16 bits after a power-up reset, global reset, or host controller reset, the initial conditions of a port are: no device connected, port disabled, and the bus line status is 00 (single- ended 0). port reset and enable sequence when software wishes to reset a usb device it will assert the port reset bit in the port status and control register. the minimum rese t signaling time is 10 ms and is enforced by software. to complete the reset sequence, software clears the port reset bit. the uhci controller must re-detect the port connect after reset signaling is complete before the controller will allow the port enable bit to reset. this time is approximately 5.3 s. software has several possible options to meet the timing requirement and a partial list is enumerated below: ? iterate a short wait, setting the port enab le bit and reading it back to see if the enable bit is set. ? poll the connect status bit and wait for the hardware to recognize the connect prior to enabling the port. ? wait longer than the hardware detect time after clearing the port reset and prior to enabling the port. bit default and access description 15:13 0 ro reserved 12 0 r/w suspend (sus) : this bit should not be written to a 1 if global suspend is active (bit 3=1 in the usbcmd register ). bit 2 and bit 12 of this register define the hub st ates as follows: when in suspend state, do wnstream propagation of da ta is blocked on this port, except for single-e nded 0 resets (global re set and port reset). the blocking occurs at the en d of the current transaction, if a transaction was in progress when this bit was written to 1. in the suspend state, the port is sensitive to resume detection. note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction cu rrently in progress on the usb. 1 = port in suspend state. 0 = port not in suspend state note: normally, if a transaction is in pr ogress when this bit is set, the port will be suspende d when the current transaction completes. 11 0 r/wc overcurrent indicator : set by hardware. softwa re clears this bit by writing a 1. 0 = no inactive to active transition has occurred 1 = overcurrent pin has gone from in active to active on this port bits [12,2] hub state x,0 disable 0, 1 enable 1, 1 suspend
uhci host controller (d29:f0, f1, f2) 220 datasheet 10 0 ro overcurrent active : this bit is set and cleared by hardware. 0 = indicates that the overcu rrent pin is inactive (high) 1 = indicates that the overcu rrent pin is active (low) 9 0 r/w port reset (pr) 0 = port is not in reset 1 = port is in reset. when set, the port is disabled and sends the usb reset signaling. 8 0 ro low speed device attached (ls) 0 = full speed device is attached 1 = low speed device is attached to this port 7 1 ro reserved. hardwired to 1 6 0 r/w resume detect (rsm_det) : software sets this bit to a 1 to drive resume signaling. the host controller sets this bit to a 1 if a j-to-k transition is detected for at least 32 microseconds while the port is in the suspend state. the intel? sch will then reflect the k-state back onto the bus as long as the bit remains a 1, and the port is still in the suspend state (bit 12,2 are 11). writing a 0 (from 1) causes the port to send a low speed eop. this bit will remain a 1 until the eop has completed. 0 = no resume (k-state) detected/driven on port. 1 = resume detected/driven on port. 5:4 0 ro line status : these bits reflect the d+ (bit 4) and d? (bit 5) signals lines? logical levels. these bits are used for fault detect and recovery as well as for usb diagnostics. this field is upda ted at eof2 time (see chapter 11 of the usb specification). 3 0 r/wc port enable/disable change : for the root hub, this bit gets set only when a port is disabled due to disc onnect on that po rt or due to the appropriate conditions existing at th e eof2 point (see chapter 11 of the usb specification). 0 = no change. software clears this bi t by writing a 1 to the bit location. 1 = port enabled/disabled status has changed. 2 0 r/w port enabled/disabled (port_en) : ports can be enabled by host software only. ports can be disabled by either a fa ult condition (disconnect event or other fault condition) or by host software. note that the bit status does not ch ange until the port state actually changes and that there may be a delay in disabling or enabling a port if there is a transaction current ly in progress on the usb. 0 = disable 1 = enable bit default and access description
datasheet 221 uhci host controller (d29:f0, f1, f2) 10 0 ro overcurrent active : this bit is set and cleared by hardware. 0 = indicates that the overcu rrent pin is inactive (high) 1 = indicates that the overcu rrent pin is active (low) 9 0 r/w port reset (pr) 0 = port is not in reset 1 = port is in reset. when set, the port is disabled and sends the usb reset signaling. 8 0 ro low speed device attached (ls) 0 = full speed device is attached 1 = low speed device is attached to this port 7 1 ro reserved. hardwired to 1 6 0 r/w resume detect (rsm_det) : software sets this bit to a 1 to drive resume signaling. the host controller sets this bit to a 1 if a j-to-k transition is detected for at least 32 microseconds while the port is in the suspend state. the intel? sch will then reflect the k-state back onto the bus as long as the bit remains a 1, and the port is still in the suspend state (bit 12,2 are 11). writing a 0 (from 1) causes the port to send a low speed eop. this bit will remain a 1 until the eop has completed. 0 = no resume (k-state) detected/driven on port. 1 = resume detected/driven on port. 5:4 0 ro line status : these bits reflect the d+ (bit 4) and d? (bit 5) signals lines? logical levels. these bits are used for fault detect and recovery as well as for usb diagnostics. this field is upda ted at eof2 time (see chapter 11 of the usb specification). 3 0 r/wc port enable/disable change : for the root hub, this bit gets set only when a port is disabled due to disc onnect on that po rt or due to the appropriate conditions existing at th e eof2 point (see chapter 11 of the usb specification). 0 = no change. software clears this bi t by writing a 1 to the bit location. 1 = port enabled/disabled status has changed. 2 0 r/w port enabled/disabled (port_en) : ports can be enabled by host software only. ports can be disabled by either a fa ult condition (disconnect event or other fault condition) or by host software. note that the bit status does not ch ange until the port state actually changes and that there may be a delay in disabling or enabling a port if there is a transaction current ly in progress on the usb. 0 = disable 1 = enable bit default and access description
uhci host controller (d29:f0, f1, f2) 222 datasheet 1 0 r/wc connect status change : this bit indicates that a change has occurred in the port?s current connect status (see bit 0). the hub device sets this bit for any changes to the port device conn ect status, even if system software has not cleared a connect status change. if, for example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting? an already-set bit (i.e., the bit will remain set). however, the hub transfers the change bit only once when the host controller requests a data tran sfer to the status change endpoint. system software is resp onsible for determining st ate change history in such a case. 0 = no change. software clears this bit by writing a 1 to it. 1 = change in current connect status. 0 0 ro current connect status : this value reflects the cu rrent state of the port, and may not correspond directly to the event that caused the connect status change bit (bit 1) to be set. 0 = no device is present. 1 = device is present on port. bit default and access description
datasheet 223 ehci host controller (d29:f7) 13 ehci host controller (d29:f7) 13.1 functional description the intel? sch contains an enhanced host controller interface (ehci), which supports up to eight usb 2.0 high-speed root ports. usb 2.0 allows data transfers up to 480 mb/ s. ports 0-5 of the ehci share the same pins as the six usb full-speed/low-speed ports detailed in chapter 12 . the two other high-speed ports, ports 6 and 7, only support usb 2.0. the intel? sch contains port-routing logic that determines whether a usb port is controlled by one of the three uhci controllers or by the ehci controller. a usb 2.0-based debug port is also implemented in intel? sch and is documented in this chapter. a summary of the key architectural differences between the uhci and ehci host controllers are shown in ta b l e 3 4 . 13.1.1 ehci initialization the expected initialization sequence of the ehci begins with a complete power cycle during which the suspend well and core well ha ve been off. after core power wells have been powered up and stabilized, the bios performs a number of platform customization steps to configure the intel? sch and its attached devices. this makes the system ready for the first operating syst em drivers to be loaded and initialized. (see chapter 4 of the enhanced host controller interface specification for universal serial bus, revision 1.0 for more information on usb driver initialization.) in addition to the standard intel? sch hard ware resets, portions of the ehci are reset by the hcreset bit and the transition from the d3 hot device power management state to the d0 state. the effects of each of these resets are as follows: table 34. uhci vs. ehci parameter usb uhci usb ehci accessible by i/o space memory space memory data structure single linked list separated into periodic and asynchronous lists differential signaling voltage 3.3 v 400 mv ports per controller 2 8 reset does reset does not reset comments hcreset bit set. memory space registers except structural parameters (which is written by bios). configuration registers. the hcreset must only effect registers that the ehci driver controls. pci configuration space and bios-programmed parameters cannot be reset. software writes the device power state from d3 hot (11b) to d0 (00b). core well registers (except bios- programmed registers). suspend well registers; bios- programmed core well registers. the d3-to-d0 transition must not cause wake information (suspend well) to be lost. it also must not clear bios-programmed registers because bios may not be invoked following the d3-to-d0 transition.
ehci host controller (d29:f7) 224 datasheet any exceptions mentioned in the detailed register descriptions supersede the rules given above. this summary is provided to help explain the reasons for the reset policies. 13.1.2 usb 2.0 interrupts and error conditions section 4 of the enhanced host controller interface specification for universal serial bus, revision 1.0 goes into detail on the ehci inte rrupts and the error conditions that cause them. all error conditions that the ehci detects can be reported through the ehci interrupt status bits. only intel? sch-specific interrupt and error-reporting behavior is documented in this section. the ehci interrupts section must be read first, followed by this section to fully comprehe nd the ehci interrupt and error-reporting functionality. ? based on the ehci?s buffer sizes and bu ffer management policies, the data buffer error can never occur on the intel? sch. ? master abort and target abort responses fr om hub interface on ehci-initiated read packets will be treated as fatal host errors. the ehci halts when these conditions are encountered. ? the intel? sch may assert the interru pts which are based on the interrupt threshold as soon as the status for the last complete transaction in the interrupt interval has been posted in the internal write buffers. the requirement in the enhanced host controller interface specification for universal serial bus, revision 1.0. ? since the intel? sch supports the 1024-e lement frame list size, the frame list rollover interrupt occurs every 1024 milliseconds. ? the intel? sch delivers interrupts using pirqh#. ? the intel? sch does not modify the cerr count on an interrupt in when the ?do complete-split? execution criteria are not met. ? for complete-split transactions in the peri odic list, the ?missed microframe? bit does not get set on a control-structure-fetch that fails the late-start test. if subsequent accesses to that control structure do not fail the late-start test, then the ?missed microframe? bit will get set and written back. 13.1.2.1 aborts on usb 2. 0?initiated memory reads if a read initiated by the ehci is aborted, the ehci treats it as a fatal host error. the following actions are taken when this occurs: ? the host system error status bit is set ? the dma engines are halted after completi ng up to one more transaction on the usb interface ? if enabled (by the host system error enable), then an interrupt is generated ? if the status is master abort, then the received master abort bit in configuration space is set ? if the status is target abort, then the received target abort bit in configuration space is set ? if enabled (by the serr enable bit in the function?s configuration space), then the signaled system error bit in configuration bit is set.
datasheet 225 ehci host controller (d29:f7) 13.1.3 usb 2.0 power management 13.1.3.1 pause feature this feature allows platforms (especially mobile systems) to dynamically enter low- power states during brief periods when the system is idle (i.e., between keystrokes). this is useful for enabling power manageme nt features like enhanced intel speedstep ? technology in the intel? sch. the policies fo r entering these states typically are based on the recent history of system bus activity to incrementally enter deeper power management states. normally, when the ehci is enabled, it regularly accesses main memory while traversing the dma schedules looking for work to do; this activity is viewed by the power management software as a non-idle system, thus preventing the power managed states to be entered. suspending all of the enabled ports can prevent the memory accesses from occurring, but there is an inherent latency overhead wi th entering and exiting the suspended state on the usb ports that makes this unacceptable for the purpose of dynamic power management. as a result, the ehci software drivers are allowed to pause the ehci?s dma engines when it knows that the traffic patterns of the attached devices can afford the delay. the pause only prevents the ehci from generating memory accesses; the sof packets continue to be generated on the usb ports (unlike the suspended state). 13.1.3.2 suspend feature the enhanced host controller interface (ehci) for universal serial bus specification , section 4.3 describes the details of port suspend and resume. 13.1.3.3 acpi device states the usb 2.0 function only supports the d0 and d3 pci power management states. notes regarding the intel? sch implementation of the device states: 1. the ehci hardware does not inherently co nsume any more power when it is in the d0 state than it does in the d3 state. however, software is required to suspend or disable all ports prior to entering the d3 state such that the maximum power consumption is reduced. 2. in the d0 state, all implemented ehci features are enabled. 3. in the d3 state, accesses to the ehci memory-mapped i/o range will master abort. note: since the debug port uses the same memory range, the debug port is only operational when the ehci is in the d0 state. 4. in the d3 state, the ehci interrupt must never assert for any reason. the internal pme# signal is used to signal wake events, etc. 5. when the device power state field is written to d0 from d3, an internal reset is generated. see section ehci resets for ge neral rules on the effects of this reset. 6. attempts to write any other value into the device power state field other than 00b (d0 state) and 11b (d3 state) will complete normally without changing the current value in this field.
ehci host controller (d29:f7) 226 datasheet 13.1.3.4 acpi system states the ehci behavior as it relates to other power management states in the system is summarized in the following list: ? the system is always in the s0 state when the ehci is in the d0 state. however, when the ehci is in the d3 state, the system may be in any power management state (including s0). ? when in d0, the pause feature (see section 13.1.3.1 ) enables dynamic processor low-power states to be entered. ? the pll in the ehci is disabled when entering the s3/s4/s5 states (core power turns off). ? all core well logic is reset in the s3/s4/s5 states. 13.1.3.5 activity during c-states the usb2 host controller can operating while the processor is in low c-states, causing pop-up to c2. 13.1.3.6 mobile considerations the intel? sch usb 2.0 implementation does not behave differently in the mobile configurations versus the desktop configurations. however, some features may be especially useful for the mobile configurations. ? if a system (e.g., mobile) does not implement all ten usb 2.0 ports, the intel? sch provides mechanisms for changing the structural parameters of the ehci and hiding unused uhci controllers. ? mobile systems may want to minimize the conditions that will wake the system. the intel? sch implements the ?wake enable? bits in the port status and control registers, as specified in the ehci spec, for this purpose. ? mobile systems may want to cut suspend well power to some or all usb ports when in a low-power state. the intel? sch impl ements the optional port wake capability register in the ehci configuration space for this platform-specific information to be communicated to software. 13.1.4 interaction with uhci host controllers the enhanced host controller shares its ports with uhci host controllers in the intel? sch. the uhc at d29:f0 shares ports 0 and 1; the uhc at d29:f1 shares ports 2 and 3; the uhc at d29:f2 shares ports 4 and 5. there is very little interaction between th e enhanced and the uhci controllers other than the multiplexing control which is provided as part of the ehci. figure 4 shows the usb port connections at a conceptual level. note: ports 6 and 7 are not multiplexed onto a uhci controller, so they are only capable of high-speed operation. this means they can on ly be used for internal device attachment as usb 2.0 spec requires that external ports be backward compatible with usb 1.1 devices. 13.1.4.1 port-routing logic integrated into the ehci functionality is port-routing logic, which performs the multiplexing between the uhci and ehci host controllers. the intel? sch conceptually implements this logic as described in section 4.2 of the enhanced host controller interface specification for universal serial bus, revision 1.0. if a device is connected that is not capable of usb 2.0?s high-speed signaling protocol or if the ehci software
datasheet 227 ehci host controller (d29:f7) drivers are not present as indicated by the configured flag, then the uhci controller owns the port. owning the port means that the differential output is driven by the owner and the input stream is only visible to the owner. the host controller that is not the owner of the port internally sees a disconnected port. note: the port-routing logic is the only block of lo gic within the intel? sch that observes the physical (real) connect/disconnect information. the port status logic inside each of the host controllers observes the electrical connect/disconnect information that is generated by the port-routing logic. only the differential signal pairs are multiplexed/de-multiplexed between the uhci and ehci host controllers. the other usb functional signals are handled as follows: ? the overcurrent inputs (oc[7:0]#) are directly routed to both controllers. an overcurrent event is recorded in both controllers? status registers. the port-routing logic is implemented in the suspend power well so that re- enumeration and re-mapping of the usb port s is not required following entering and exiting a system sleep state in which the core power is turned off. the intel? sch also allows the usb debug port traffic to be routed in and out of port 0. when in this mode, the enhanced host controller is the owner of port 0. figure 4. intel? sch usb port connections uchi #0 uhci #1 uhci #2 enhanced host controller logic debug port port 3 port 4 port 5 port 2 port 1 port 0 port 6 port 7
ehci host controller (d29:f7) 228 datasheet 13.1.4.2 device connects the enhanced host controller interface spec ification for universal serial bus, revision 1.0 describes the details of handling device connects in section 4.2. there are four general scenarios that are summarized below. 1. configure flag = 0 and a full-speed /low-speed-only device is connected ? in this case, the uhc is the owner of the port both before and after the connect occurs. the ehci (except for the port-routing logic) never sees the connect occur. the uhci driver handles the connection and initialization process. 2. configure flag = 0 and a high-speed-capable device is connected ? in this case, the uhc is the owner of the port both before and after the connect occurs. the ehci (except for the port-routing logic) never sees the connect occur. the uhci driver handles the conne ction and initialization process. since the uhc does not perform the high-speed chirp handshake, the device operates in compatible mode. 3. configure flag = 1 and a full-speed /low-speed-only device is connected ? in this case, the ehci is the owner of the port before the connect occurs. the ehci driver handles the connection and pe rforms the port reset. after the reset process completes, the ehci hardware has cleared (not set) the port enable bit in the ehc?s portsc register. the ehci driver then writes a 1 to the port owner bit in the same register, causing the uh c to see a connect event and the ehci to see an ?electrical? disconnect event. the uhci driver and hardware handle the connection and initialization process from that point on. the ehci driver and hardware handle the perceived disconnect. 4. configure flag = 1 and a high-speed-capable device is connected ? in this case, the ehci is the owner of the port before, and remains the owner after, the connect occurs. the ehci driver handles the connection and performs the port reset. after the reset process completes, the ehci hardware has set the port enable bit in the ehc?s portsc register. the port is functional at this point. the uhc continues to see an unconnected port. 13.1.4.3 device disconnects the enhanced host controller interface spec ification for universal serial bus, revision 1.0 describes the details of handling device connects in section 4.2. there are three general scenarios that are summarized below. 1. configure flag = 0 and the device is disconnected ? in this case, the uhc is the owner of the port both before and after the disconnect occurs. the ehci (except for the port-routing logic) never sees a device attached. the uhci driver handles disconnection process. 2. configure flag = 1 and a full-speed/low-speed-capable device is disconnected ? in this case, the uhc is the owner of th e port before the disconnect occurs. the disconnect is reported by the uhc and serviced by the associated uhci driver. the port-routing logic in the ehci cluster forces the port owner bit to 0, indicating that the ehci owns the unconnected port. 3. configure flag = 1 and a high-sp eed-capable device is disconnected ? in this case, the ehci is the owner of the port before, and remains the owner after, the disconnect occurs. the ehci hardware and driver handle the disconnection process. the uhc never sees a device attached.
datasheet 229 ehci host controller (d29:f7) 13.1.4.4 effect of resets on port-routing logic as mentioned above, the port routing logic is implemented in the suspend power well so that remuneration and re-mapping of the usb ports is not required following entering and exiting a system sleep state in which the core power is turned off. 13.1.5 usb 2.0 based debug port the intel? sch supports the elimination of the legacy com ports by providing the ability for new debugger software to interact with devices on a usb 2.0 port. for details on the debug port , refer to appendix c of enhanced host controller interface specification fo r universal serial bus, revision 1.0. reset event effect on configure flag effect on port owner bits suspend well reset cleared (0) set (1) core well reset no effect no effect d3-to-d0 reset no effect no effect hcreset cleared (0) set (1)
ehci host controller (d29:f7) 230 datasheet 13.2 usb ehci configuration registers note: all bit descriptions in this chapter assume the default configuration of device 29 supporting usb ports 0-2. note: all configuration registers in this section are in the core well and rese t by a core well reset and the d3-to-d0 warm re set, except as noted. table 35. usb ehci pci register address map offset mnemonic register name default value type 00h?01h vid vendor identification 8086h ro 02h?03h did device identification 8117h ro 04h?05h pcicmd pci command 0000h r/w, ro 06h?07h pcists pci status 0010h r/w, ro 08h rid revision identification see description ro 09h?0bh cc class codes 0c0320h ro 0dh mlt master latency timer 00h ro 0eh headtyp header type 00h ro 10h?13h mem_base memory base address 00000000h r/w, ro 2ch?2dh svid usb ehci subsystem vendor identification uuuuh r/w (special) 2eh?2fh sid usb ehci subsystem identification uuuuh r/w (special) 34h cap_ptr capabili ties pointer 50h ro 3ch int_ln interrupt line 00h r/w 3dh int_pn interrupt pin see description ro 50h pm_capid pci power management capability id 01h ro 51h nxt_ptr1 next item pointer 58h r/w (special) 52h?53h pm_cap power management ca pabilities c9c2h r/w (special) 54h?55h pm_ctl_sts power management control/status 0000h r/w, r/wc, ro 58h debug_capid debug port capability id 0ah ro 59h nxt_ptr2 next item pointer #2 00h ro 5ah?5bh debug_base debug port base offset 20a0h ro 60h usb_relnum usb release number 20h ro 61h fl_adj frame length adjustment 20h r/w 62h?63h pwake_cap port wake capabilities 03fdh ro 64h?65h cuo classic usb override 0000h ro, r/w 68h?6bh leg_ext_cap usb ehci legacy support extended capability 00000001h r/w, ro 6ch?6fh leg_ext_cs usb ehci legacy extended support control/status 00000000h r/w, r/wc, ro 70h?73h special_smi intel specific usb 2.0 smi 00000000h r/w, r/wc 80h access_cntl access control 00h r/w c0h?c3h fd function disable 00000000h ro, r/w
datasheet 231 ehci host controller (d29:f7) 13.2.1 vid?vendor iden tification register offset address: 00h ? 01h attribute: ro default value: 8086h size: 16 bits 13.2.2 did?device identification register offset address: 02h ? 03h attribute: ro default value: 8117h size: 16 bits 13.2.3 pcicmd?pci command register address offset: 04h ? 05h attribute: r/w, ro default value: 0000h size: 16 bits bit default and access description 15:0 8086 ro vendor id : this is a 16-bit value assigned to intel. bit default and access description 15:0 8117h ro device id : the value 8117h corresponds to the intel? sch ehci controller. bit default and access description 15:11 0 ro reserved 10 0 r/w interrupt disable 0 = the function is capable of genera ting interrupts. 1 = the function cannot generate its interrupt to the interrupt controller. note that the corresponding interrupt status bit (d29:f7:06h, bit 3) is not affected by the interrupt enable. 9:3 00h ro reserved 2 0 r/w bus master enable (bme) 0 = disables this functionality. 1 = enables the intel? sch to act as a master on the pci bus for usb transfers. 1 0 r/w memory space enable (mse) : this bit controls access to the usb 2.0 memory space registers. 0 = disables this functionality. 1 = enables accesses to the usb 2.0 registers. the base address register (d29:f7:10h) for usb 2.0 should be pr ogrammed before this bit is set. 0 0 ro reserved
ehci host controller (d29:f7) 232 datasheet 13.2.4 pcists?pci status register address offset: 06h ? 07h attribute: r/w, ro default value: 0010h size: 16 bits 13.2.5 rid?revision iden tification register offset address: 08h attribute: ro default value: see bit description size: 8 bits 13.2.6 cc?class codes register address offset: 09h?0bh attribute: ro default value: 0c0320h size: 24 bits bit default and access description 15:5 000h ro reserved 4 1 ro capabilities list (cap_list) : hardwired to 1 indicating that offset 34h contains a valid ca pabilities pointer. 3 0 ro interrupt status : this bit reflects the state of this function?s interrupt at the input of the enable/disable logic. 0 = this bit will be 0 when the interru pt is deasserted. 1 = this bit is a 1 when th e interrupt is asserted. the value reported in this bit is inde pendent of the value in the interrupt enable bit. 2:0 0 ro reserved bit default and access description 7:0 ro revision id : refer to the intel ? system controller hub (intel ? sch) specification update for the value of the revision id register bit default and access description 23:16 0ch ro base class code (bcc) 0ch = serial bus controller. 15:8 03h ro sub class code (scc) 03h = universal serial bus host controller. 7:0 20h ro programming interface (pi) : a value of 20h indicates that this usb 2.0 host controller conforms to the ehci specification.
datasheet 233 ehci host controller (d29:f7) 13.2.7 mlt?master latency timer register address offset: 0dh attribute: ro default value: 00h size: 8 bits 13.2.8 headtyp?heade r type register address offset: 0eh attribute: ro default value: 00h size: 8 bits 13.2.9 mem_base?base address register address offset: 10h ? 13h attribute: r/w, ro default value: 00000000h size: 32 bits bit default and access description 7:0 00h ro master latency timer (mlt) : hardwired to 00h. because the ehci controller is internally implemented wi th arbitration on an interface (and not pci), it does not need a master latency timer. bit default and access description 7 0 ro multi-function device : hardwired to 0h indica ting this is a single function device. 6:0 00h ro configuration layout . hardwired to 00h, which indicates the standard pci configuration layout. bit default and access description 31:10 0000h r/w memory base address : bits 31:10 correspond to memory address signals 31:10, respectively. this gives 1 kb of locatable memory space aligned to 1 kb boundaries. 9:4 00h ro reserved 3 0 ro prefetchable : hardwired to 0 indicating that this range should not be prefetched. 2:1 00b ro type : hardwired to 00b indicating that this range can be mapped anywhere within 32-bit address space. 0 0 ro resource type indicator (rte) : hardwired to 0 indicating that the base address field in this regist er maps to memory space.
ehci host controller (d29:f7) 234 datasheet 13.2.10 svid?usb ehci subs ystem vendor id register address offset: 2ch ? 2dh attribute: r/w (special) default value: uuuuh size: 16 bits reset: none 13.2.11 sid?usb ehci subsystem id register address offset: 2eh ? 2fh attribute: r/w (special) default value: uuuuh size: 16 bits reset: none 13.2.12 cap_ptr?capabili ties pointer register address offset: 34h attribute: ro default value: 50h size: 8 bits bit default and access description 15:0 r/w subsystem vendor id (svid) (special): this register, in combination with the usb 2.0 subsystem id register, enables the operating system to distinguish each subs ystem from the others. note: writes to this register are enabled when the wrt_rdonly bit (d29:f7:80h, bit 0) is set to 1. bit default and access description 15:0 r/w subsystem id (sid) (special): bios sets the value in this register to identify the subsystem id. this register, in combination with the subsystem vendor id register, enables the operating system to distinguish each subsystem from other(s). note: writes to this register are enabled when the wrt_rdonly bit (d29:f7:80h, bit 0) is set to 1. bit default and access description 7:0 50h ro pointer (ptr) : this register points to the starting offset of the usb 2.0 capabilities ranges.
datasheet 235 ehci host controller (d29:f7) 13.2.13 int_ln?interrupt line register address offset: 3ch attribute: r/w default value: 00h size: 8 bits 13.2.14 int_pn?interrupt pin register address offset: 3dh attribute: ro default value: see description size: 8 bits 13.2.15 pm_capid?pci power ma nagement capability id register address offset: 50h attribute: ro default value: 01h size: 8 bits bit default and access description 7:0 00h r/w interrupt line (int_ln) : this data is not used by the intel? sch. it is used as a scratchpad regi ster to communicate to so ftware the interrupt line that the interrupt pin is connected to. bit default and access description 7:0 00h ro interrupt pin . this reflects the value of d29ip.eip (chipset config registers:offset 3108:bits 31:28). note: bits 7:4 are always 0. bit default and access description 7:0 01h ro power management capability id : a value of 01h indicates that this is a pci power management capabilities field.
ehci host controller (d29:f7) 236 datasheet 13.2.16 nxt_ptr1?next item pointer #1 register address offset: 51h attribute: r/w (special) default value: 58h size: 8 bits 13.2.17 pm_cap?power manage ment capabilities register address offset: 52h ? 53h attribute: r/w (special), ro default value: c9c2h size: 16 bits notes: 1. normally, this register is read-only to re port capabilities to the power management software. to report different power management capa bilities, depe nding on the system in which the intel? sch is used, bits 15:11 and 8:6 in this register are writable when the wrt_rdonly bit (d29:f7:80h, bit 0) is set. th e value written to this register does not effect the hardware other than changing the value returned during a read. 2. this register is reset during a core well reset, but not d3-to-d0 state transition. bit default and access description 7:0 58h r/w next item pointer 1 value (special): this regi ster defaults to 58h, which indicates that the next capabili ty registers begin at configuration offset 58h. this register is wr itable when the wrt_rdonly bit (d29:f7:80h, bit 0) is set. this allows bios to effectively hide the debug port capability registers, if necessary. this register should only be written during system initialization before the plug-and-play software has enabled any master-initiated traffic. only valu es of 58h (debug port visible) and 00h (debug port invisible) are expected to be programmed in this register. note: register not reset by d3-to-d0 warm reset. bit default and access description 15:11 11001b r/w pme support (pme_sup) (special): this 5-bit field in dicates the power states in which the function may asse rt pme#. the ehci does not support the d1 or d2 states. for all other stat es, the ehci is capable of generating pme#. software should never need to modify this field. 10 0 ro d2 support (d2_sup) . 0 = d2 state is not supported 9 0 ro d1 support (d1_sup) . 0 = d1 state is not supported 8:6 111b r/w auxiliary current (aux_cur). the ehci reports 375 ma maximum suspend well current required when in the d3 cold state. this value may be rewritten by bios when a be tter current value is known. 5 0 ro device specific initialization (dsi ). the intel? sch reports 0, indicating that no device-specific initialization is required. 4 0 ro reserved 3 0 ro pme clock (pme_clk) . the intel? sch reports 0, indicating that no pci clock is required to generate pme#. 2:0 010b ro version (ver) . the intel? sch reports 010b, indicating that it complies with revision 1.1 of the pci power management specification.
datasheet 237 ehci host controller (d29:f7) 13.2.18 pwr_cntl_sts?power ma nagement control/status register address offset: 54h ? 55h attribute: r/w, r/wc, ro default value: 0000h size: 16 bits note: reset (bits 15, 8): suspend well, and not d3 -to-d0 warm reset nor core well reset. bit default and access description 15 0 r/wc pme status (sts) 0 = writing a 1 to this bit will clea r it and cause the internal pme to deassert (if enabled). 1 = this bit is set when the ehci woul d normally assert the pme# signal independent of the state of the pme_en bit. note: this bit must be explicitly clea red by the operating system each time the operating system is loaded. 14:13 00b ro data scale (dsca) : hardwired to 00b indicating it does not support the associated data register. 12:9 0h ro data select (dsel) : hardwired to 0000b indicating it does not support the associated data register. 8 0 r/w pme enable (en) 0 = disable. 1 = enable. enables ehci to genera te an internal pme signal when pme_status is 1. note: this bit must be explicitly clea red by the operating system each time it is initially loaded. 7:2 00h ro reserved 1:0 00b r/w power state : this 2-bit field is used both to determine the current power state of ehci function and to set a ne w power state. the definition of the field values are: 00 = d0 state 11 = d3 hot state if software attempts to write a value of 10b or 01b in to this field, the write operation must complete normally; howe ver, the data is discarded and no state change occurs. when in the d3 hot state, the intel? sch must not accept accesses to the ehci memory range; but the configuration space must still be accessible. when software changes this value from the d3 hot state to the d0 state, an internal warm (soft) rese t is generated, and softwa re must re-i nitialize the function.
ehci host controller (d29:f7) 238 datasheet 13.2.19 debug_capid?debug port capability id register address offset: 58h attribute: ro default value: 0ah size: 8 bits 13.2.20 nxt_ptr2?next item pointer #2 register address offset: 59h attribute: ro default value: 00h size: 8 bits 13.2.21 debug_base?debug po rt base offset register address offset: 5ah ? 5bh attribute: ro default value: 20a0h size: 16 bits 13.2.22 usb_relnum?usb release number register address offset: 60h attribute: ro default value: 20h size: 8 bits bit default and access description 7:0 0ah ro debug port capability id : hardwired to 0ah indicating that this is the start of a debug port capability structure. bit default and access description 7:0 00h ro next (next) : hardwired to 00h to indicate there are no more capability structures in this function. bit default and access description 15:13 02h ro bar number : hardwired to 001b to indicate the memory bar begins at offset 10h in the ehci configuration space. 12:0 a0h ro debug port offset : hardwired to 0a0h to indi cate that the debug port registers begin at offset a0 h in the ehci memory range. bit default and access description 7:0 20h ro usb release number : a value of 20h indicates that this controller follows universal serial bus (usb) specification, revision 2.0 .
datasheet 239 ehci host controller (d29:f7) 13.2.23 fl_adj?frame leng th adjustment register address offset: 61h attribute: r/w default value: 20h size: 8 bits this feature is used to adjust any offset from the clock source that generates the clock that drives the sof counter. when a new value is written into these six bits, the length of the frame is adjusted. its initial prog rammed value is system dependent based on the accuracy of hardware usb clock and is initialized by system bios. this register should only be modified when the hchalted bit (d29:f7:caplength + 24h, bit 12) in the usb2.0_sts register is a 1. changing valu e of this register while the host controller is operating yields undefined results. it should not be reprogrammed by usb system software unless the default or bios programm ed values are incorrect, or the system is restoring the register while returning from a suspended state. these bits in suspend well and not reset by a d3-to-d0 warm rest or a core well reset. bit default and access description 7:6 00b ro reserved. these bits are reserved for future use and should read as 00b. 5:0 20h r/w frame length timing value : each decimal value change to this register corresponds to 16 high-speed bit ti mes. the sof cycle time (number of sof counter clock periods to generate a sof micro-frame length) is equal to 59488 + value in this field. the de fault value is decimal 32 (20h), which gives a sof cycle time of 60000. frame length (# 480 mhz clocks) (decimal) frame length timing value (this register) (decimal) 59488 0 59504 1 59520 2 ?? 59984 31 60000 32 ?? 60480 62 60496 63
ehci host controller (d29:f7) 240 datasheet 13.2.24 pwake_cap?port wake capability register address offset: 62 ? 63h attribute: ro default value: 01ffh size: 16 bits this register is in the suspend power well. a one in a bit position indicates that a device connected below the port can be enabled as a wake-up device and the port may be enabled for disconnect/connect or over-current events as wake-up events. this is an information-only mask register. reset: suspend well, and not d3-to- d0 warm reset nor core well reset. 13.2.25 cuo?classic usb override register address offset: 64h attribute: ro, r/w default value: 00h size: 16 bits this 16-bit register provides a bit correspond ing to each of the ports on the ehci host controller. when a bit is set to 1, the corresponding usb port is routed to the classic (uhci) host controller and will only oper ate using the classic signaling rates. the feature is implemented with the following requirements: ? the associated port owner bit does not reflect the value in this new override register. this ensures compatibility with ehci drivers. ? bios must only write to this register duri ng initialization (while the configured flag is 0). ? the register is implemented in the suspend well to maintain port-routing when the core power goes down ? when a 1 is present in the cuo register, then the classic controller operates the port regardless of the ehci port routing logic. the corresponding ehci port will always appear disconnected in this mode. ? port 0 must not be programmed into classic usb override mode as this is the debug port. bit default and access description 15:9 0 ro reserved 8:1 1ffh ro port wake up capability mask : bit positions 1 through 8 (device 29) correspond to a physical port implem ented on this host controller. for example, bit position 1 corresponds to port 1, bit position 2 corresponds to port 2, etc. 0 1b ro port wake implemented : a 1 in this bit indicates that this register is implemented to software. bit default and access description 15:8 00h ro reserved 7:1 00h r/w classic usb port owner : a 1 in a bit position forces the corresponding usb port to the classic host controller. 0 0 ro reserved
datasheet 241 ehci host controller (d29:f7) 13.2.26 leg_ext_cap?usb ehci legacy support extended capability register address offset: 68 ? 6bh attribute: r/w, ro default value: 00000001h size: 32 bits note: these bits are not reset by a d3-to-d0 warm rest or a core well reset. this register lives in the resume power well. 13.2.27 leg_ext_cs?usb ehci legacy support extended control/status register address offset: 6c ? 6fh attribute: r/w, r/wc, ro default value: 00000000h size: 32 bits power well: suspend note: these bits are not reset by a d3-to-d0 warm rest or a core well reset. bit default and access description 31:25 00h ro reserved. hardwired to 00h 24 0 r/w hc os owned semaphore : system software sets this bit to request ownership of the ehci controller. ow nership is obtained when this bit reads as 1 and the hc bios owned semaphore bit reads as clear. 23:17 00h ro reserved. hardwired to 00h 16 0 r/w hc bios owned semaphore : the bios sets this bit to establish ownership of the ehci controller. sy stem bios will clear this bit in response to a request fo r ownership of the ehci controller by system software. 15:8 00h ro next ehci capability pointer : hardwired to 00h to indicate that there are no ehci extended capability structures in this device. 7:0 01h ro capability id : hardwired to 01h to indicate that this ehci extended capability is the legacy support capability. bit default and access description 31 0 r/wc smi on bar : software clears this bi t by writing a 1 to it. 0 = base address register (bar) not written. 1 = this bit is set to 1 when the base address register (bar) is written. 30 0 r/wc smi on pci command : software clears this bit by writing a 1 to it. 0 = pci command (pcicmd) register not written. 1 = this bit is set to 1 when the pci command (pcicmd) register is written. 29 0 r/wc smi on os ownership change : software clears this bit by writing a 1 to it. 0 = no hc os owned semaphore bit change. 1 = this bit is set to 1 when the hc os owned semaphore bit in the leg_ext_cap register (d29:f7:68h, bit 24) transitions from 1-to-0 or 0-to-1.
ehci host controller (d29:f7) 242 datasheet 28:22 00h ro reserved. hardwired to 00h 21 0 ro smi on async advance : this bit is a shadow bit of the interrupt on async advance bit (d29:f7:caplength + 24h, bit 5) in the usb2.0_sts register. note: to clear this bit system software must write a 1 to the interrupt on async advance bit in the usb2.0_sts register. 20 0 ro smi on host system error : this bit is a shadow bit of host system error bit in the usb2.0_sts register (d29:f7:caplength + 24h, bit 4). note: to clear this bit system software must write a 1 to the host system error bit in the usb2.0_sts register. 19 0 ro smi on frame list rollover : this bit is a shadow bit of frame list rollover bit (d29:f7:caplength + 24h, bit 3) in the usb2.0_sts register. note: to clear this bit system software must write a 1 to the frame list rollover bit in the usb2.0_sts register. 18 0 ro smi on port change detect : this bit is a shadow bit of port change detect bit (d29:f7:caplength + 24h, bit 2) in the usb2.0_sts register. note: to clear this bit system software must write a 1 to the port change detect bit in the usb2.0_sts register. 17 0 ro smi on usb error : this bit is a shadow bit of usb error interrupt (usberrint) bit (d29:f7:caplength + 24h, bit 1) in the usb2.0_sts register. note: to clear this bit system software must write a 1 to the usb error interrupt bit in the usb2.0_sts register. 16 0 ro smi on usb complete : this bit is a shadow bit of usb interrupt (usbint) bit (d29:f7:caplength + 24h, bit 0) in the usb2.0_sts register. note: to clear this bit system softwa re must write a 1 to the usb interrupt bit in the usb2.0_sts register. 15 0 r/w smi on bar enable 0 = disable. 1 = enable. when this bi t is 1 and smi on bar (d29:f7:6ch, bit 31) is 1, then the host controller will issue an smi. 14 0 r/w smi on pci command enable 0 = disable. 1 = enable. when this bi t is 1 and smi on pci command (d29:f7:6ch, bit 30) is 1, then the host controller will issue an smi. 13 0 r/w smi on os ownership enable 0 = disable. 1 = enable. when this bit is a 1 and the os ownership change bit (d29:f7:6ch, bit 29) is 1, the host controller will issue an smi. 12:6 00h ro reserved: hardwired to 00h bit default and access description
datasheet 243 ehci host controller (d29:f7) 5 0 r/w smi on async advance enable 0 = disable. 1 = enable. when this bit is a 1, and the smi on async advance bit (d29:f7:6ch, bit 21) is a 1, the host controller will issue an smi immediately. 4 0 r/w smi on host system error enable 0 = disable. 1 = enable. when this bit is a 1, and the smi on host system error (d29:f7:6ch, bit 20) is a 1, the host controller will issue an smi. 3 0 r/w smi on frame list rollover enable 0 = disable. 1 = enable. when this bit is a 1, an d the smi on frame list rollover bit (d29:f7:6ch, bit 19) is a 1, the host controller will issue an smi. 2 0 r/w smi on port change enable 0 = disable. 1 = enable. when this bit is a 1, an d the smi on port change detect bit (d29:f7:6ch, bit 18) is a 1, the host controller will issue an smi. 1 0 r/w smi on usb error enable 0 = disable. 1 = enable. when this bit is a 1, and the smi on usb error bit (d29:f7:6ch, bit 17) is a 1, the host controller will issue an smi immediately. 0 0 r/w smi on usb complete enable 0 = disable. 1 = enable. when this bit is a 1, and the smi on usb complete bit (d29:f7:6ch, bit 16) is a 1, the host controller will issue an smi immediately. bit default and access description
ehci host controller (d29:f7) 244 datasheet 13.2.28 special_smi?intel sp ecial usb 2.0 smi register address offset: 70h ? 73h attribute: r/w, r/wc default value: 00000000h size: 32 bits power well: suspend bit default and access description 31:30 00b ro reserved. hardwired to 00b 29:22 0 r/wc smi on portowner : software clears these bi ts by writing a 1 to it. 0 = no port owner bit change. 1 = bits 29:22 correspond to the port owner bits for ports 8 (29) through 1 (22). these bits are set to 1 when the associated port owner bits transition from 0 to 1 or 1 to 0. 21 0 r/wc smi on pmcsr c: software clears these bi ts by writing a 1 to it. 0 = power state bits not modified. 1 = software modified the power state bits in the power management control/status (pmcsr) register (d29:f7:54h). 20 0 r/wc smi on async : software clears these bits by writing a 1 to it. 0 = no async schedule enable bit change 1 = async schedule enable bit transitioned from 1-to-0 or 0-to-1. 19 0 r/wc smi on periodic : software clears this bit by writing a 1 it. 0 = no periodic schedule enable bit change. 1 = periodic schedule enable bit tr ansitions from 1-to-0 or 0-to-1. 18 0 r/wc smi on cf : software clears this bit by writing a 1 it. 0 = no configure flag (cf) change. 1 = configure flag (cf) transi tions from 1-to-0 or 0-to-1. 17 0 r/wc smi on hchalted : software clears this bit by writing a 1 it. 0 = hchalted did not transition to 1 (a s a result of the run/stop bit being cleared). 1 = hchalted transitions to 1 (as a result of the run/stop bit being cleared). 16 0 r/wc smi on hcreset : software clears this bit by writing a 1 it. 0 = hcreset did not transitioned to 1. 1 = hcreset transitioned to 1. 15:14 00b ro reserved: hardwired to 00b 13:6 00h r/w smi on portowner enable 0 = disable. 1 = enable. when any of these bits are 1 and the corresponding smi on portowner bits are 1, th en the host controller will issue an smi. unused ports should have thei r corresponding bits cleared. 5 0 r/w smi on pmscr enable 0 = disable. 1 = enable. when this bi t is 1 and smi on pmscr is 1, then the host controller will issue an smi.
datasheet 245 ehci host controller (d29:f7) note: these bits are not reset by a d3-to-d0 warm rest or a core well reset. 13.2.29 access_cntl?acce ss control register address offset: 80h attribute: r/w default value: 00h size: 8 bits 4 0 r/w smi on async enable 0 = disable. 1 = enable. when this bit is 1 and smi on async is 1, then the host controller will issue an smi 3 0 r/w smi on periodic enable 0 = disable. 1 = enable. when this bit is 1 and sm i on periodic is 1, then the host controller will issue an smi. 2 0 r/w smi on cf enable 0 = disable. 1 = enable. when this bit is 1 and smi on cf is 1, then the host controller will issue an smi. 1 0 r/w smi on hchalted enable 0 = disable. 1 = enable. when this bit is a 1 and smi on hchalted is 1, then the host controller will issue an smi. 0 0 r/w smi on hcreset enable 0 = disable. 1 = enable. when this bit is a 1 an d smi on hcreset is 1, then host controller will issue an smi. bit default and access description bit default and access description 7:1 00h ro reserved 0 0 r/w wrt_rdonly : when set to 1, this bit enables a select group of normally read-only registers in the ehci function to be written by software. registers that may only be written when this mode is entered are noted in the summary tables and deta iled description as ?read/write-special?. the registers fall into two categories : system-configured parameters and status bits.
ehci host controller (d29:f7) 246 datasheet 13.2.30 fd?function disable register address offset: c0h?c3h attribute: ro, r/w default value: 00000000h size: 32 bits 13.3 memory-mapped i/o registers the ehci memory-mapped i/o space is compos ed of two sets of registers: capability registers and operational registers. note: the intel? sch ehci controller will not accept memory transactions (neither reads nor writes) as a target that are locked transact ions. the locked transactions should not be forwarded to pci as the address space is known to be allocated to usb. note: when the ehci function is in the d3 pci power state, accesses to the usb 2.0 memory range are ignored and result a master abort. similarly, if the memory space enable (mse) bit (d29:f7:04h, bit 1) is not set in the command register in configuration space, the memory range will not be deco ded by the intel? sch enhanced host controller (ehc). if the mse bit is not set, th en the intel? sch must default to allowing any memory accesses for the range specified in the bar to go to pci. this is because the range may not be valid and, therefore, the cycle must be made available to any other targets that may be currently using that range. 13.3.1 host controller capability registers these registers specify the limits, restrictions and capabilities of the host controller implementation. within the host controller capability registers, only the structural parameters register is writable. these registers are implemented in the suspend well and is only reset by the standard suspend- well hardware reset, not by hcreset or the d3-to-d0 reset. note: the ehci controller does not support as a target memory transactions that are locked transactions. attempting to access the ehci controller memory-mapped i/o space using locked memory transactions will result in undefined behavior. note: when the usb2 function is in the d3 pci power state, accesses to the usb2 memory range are ignored and will result in a mast er abort similarly, if the memory space enable (mse) bit is not set in the comman d register in configuration space, the memory range will not be decoded by the e nhanced host controller (ehc). if the mse bit is not set, then the ehci will not clai m any memory accesses for the range specified in the bar. bit default and access description 31:3 0s ro reserved 2 0 r/w clock gating disable (cgd) 0 = clock gating within this function is enabled 1 = clock gating within this function is disabled 1 0 ro reserved 0 0 r/w disable (d) 0 = this function is enabled 1 = this function is disabled and the configuration space is not accessible.
datasheet 247 ehci host controller (d29:f7) note: read/write special means that the register is normally read-only, but may be written when the wrt_rdonly bit is set. because these registers are expected to be programmed by bios during initialization, th eir contents must not get modi fied by hcreset or d3-to-d0 internal reset. 13.3.1.1 caplength?capability registers length register offset: mem_base + 00h attribute: ro default value: 20h size: 8 bits 13.3.1.2 hciversion?host controller interface version number register offset: mem_base + 02h ? 03h attribute: ro default value: 0100h size: 16 bits table 36. ehci capability registers mem_base + offset mnemonic register default type 00h caplength capabilities registers length 20h ro 02h?03h hciversion host controller interface version number 0100h ro 04h?07h hcsparams host controller structural parameters 00104208h r/w (special), ro 08h?0bh hccparams host controller capability parameters 00006871h ro bit default and access description 7:0 20h ro capability register length value: this register is us ed as an offset to add to the memory base register (d29 :f7:10h) to find the beginning of the operational register space. this field is hardwired to 20h indicating that the operation regist ers begin at offset 20h. bit default and access description 15:0 0100h ro host controller interface version number: this is a two-byte register containing a bcd encoding of the versio n number of interface that this host controller inte rface conforms.
ehci host controller (d29:f7) 248 datasheet 13.3.1.3 hcsparams?host cont roller structural parameters offset: mem_base + 04h ? 07h attribute: r/w (special), ro default value: 00103206h size: 32 bits note: this register is in the suspend well and is reset by a suspend well reset and not a d3- to-d0 reset or hcreset. note: this register is writable wh en the wrt_rdonly bit is set. bit default and access description 31:24 00h ro reserved 23:20 1h ro debug port number (dp_n) (special): hardwired to 1h indicating that the debug port is on the lowest numbered port on the ehci. 19:16 0h ro reserved 15:12 3h r/w number of companio n controllers (n_cc) : this field indicates the number of companion controllers associated with this usb ehci host controller. a 0 in this field indicates there are no companion host controllers. port- ownership hand-off is not supported . only high-speed devices are supported on the host controller root ports. a value of 1 or more in this field indicates there are companion usb uhci host controller(s). port-ownership hand-offs are supported. high, full- and low-speed devices are supported on the host controller root ports. the intel? sch allows the default value of 3h to be over-written by bios. when removing classic controllers, they must be disabled in the following order: function 2, function 1, and function 0, which correspond to ports 5:4, 3:2, and 1:0, respectively for device 29. 11:8 2h ro number of ports per companion controller (n_pcc) : hardwired to 2h. this field indicates the number of ports supported per companion host controller. it is used to indicate th e port routing configuration to system software. 7 0h ro port routing rules (prr) : indicating the first npcc ports are routed to the lowest numbered function compan ion host controller, the next npcc ports are routed to the next lowest function companion controller, and so on. hardwired to 0. 6:4 000b ro reserved 3:0 8h r/w number of ports (n_ports) : this field specifies the number of physical downstream ports implemen ted on this host controller. the value of this field determines how many port registers are addressable in the operational register space. valid values are in the range of 1h to fh. the intel? sch reports 8h by defaul t. however, software may write a value less than the defaul t for some platform conf igurations. a 0 in this field is undefined.
datasheet 249 ehci host controller (d29:f7) 13.3.1.4 hccparams?host controlle r capability parameters register offset: mem_base + 08h ? 0bh attribute: ro default value: 00016871h size: 32 bits bit default and access description 31:17 0000h ro reserved 16 1 ro periodic schedule update capability (psuc) : indicates the ehci supports ecmd.pue. 15:8 68h ro ehci extended capabilities pointer (eecp) : this field is hardwired to 68h, indicating that the eh ci capabilities list exists and begins at offset 68h in the pci configuration space. 7:4 7h ro isochronous scheduling threshold : this field indicates, relative to the current position of the executing ho st controller, where software can reliably update the isochronous schedule. when bit 7 is 0, the value of the least significant 3 bits indicates th e number of micro-frames a host controller hold a set of isochronous da ta structures (one or more) before flushing the state. when bit 7 is a 1, then host software assumes the host controller may cache an isochronous da ta structure for an entire frame. refer to the ehci specif ication for details on how software uses this information for scheduling isochronous transfers. this field is hardwired to 7h. 3 0 ro reserved. these bits are reserv ed and should be set to 0. 2 0 ro asynchronous schedule park capability : this bit is hardwired to 0 indicating that the host controller do es not support this optional feature. 1 0 ro programmable frame list flag : 0 = system software must use a frame list length of 1024 elements with this host controller. the usb2.0_c md register (d29:f7:caplength + 20h, bits 3:2) frame list size field is a read-only register and must be set to 0. 1 = system software can sp ecify and use a smaller fr ame list and configure the host controller by the usb2.0_cmd register frame list size field. the frame list must always be alig ned on a 4-k page boundary. this requirement ensures that the frame list is always physically contiguous. 0 1 ro 64-bit addressing capability : this field do cuments the addressing range capability of this implementation. the value of this field determines whether software should use the 32-bit or 64-bit data structures. values for this field have the following interpretation: 0 = data structures using 32- bit address memory pointers 1 = data structures using 64-bi t address memory pointers this bit is hardwired to 1. note: the intel? sch only implements 44 bits of addressing. bits 63:44 will always be 0.
ehci host controller (d29:f7) 250 datasheet 13.3.2 host controller operational registers this section defines the enhanced host controller operational registers. these registers are located after the capabilities registers. the operational register base must be dword-aligned and is calculated by adding the value in the first capabilities register (caplength) to the base addr ess of the enhanced host controller register address space (mem_base). since caplength is always 20h, ta b l e 3 7 already accounts for this offset. all registers are 32 bits in length. the first set of registers in ta b l e 3 7 (offsets mem_base + 20:3bh) are implemented in the core power well. these core well register s are reset by either a core well hardware reset, manually resetting the ehci contro ller by the hcreset bi t in the usb2.0_cmd register. the second set of registers (offsets mem_ base + 60:83h) are powered by the suspend power well and remain powered during the s3 sleep state. these registers are reset either during a suspend well hardware reset or by resetting the ehci controller (by the usb2.0_cmd.hcreset bit). table 37. enhanced host controller operational register address map mem_base + offset mnemonic register name default type 20h?23h usb2.0_cmd usb 2.0 command 00080000h r/w, ro 24h?27h usb2.0_sts usb 2.0 status 00001000h r/wc, ro 28h?2bh usb2.0_intr usb 2.0 interrupt enable 00000000h r/w 2ch?2fh frindex usb 2.0 frame index 00000000h r/w, 30h?33h ctrldssegment control data structure segment 00000000h r/w, ro 34h?37h perodiclistbase period frame list base address 00000000h r/w 38h?3bh asynclistaddr current asynchronous list address 00000000h r/w 60h?63h configflag configure flag 00000000h r/w 64h?67h port0sc port 0 status and control 00003000h r/w, r/ wc, ro 68h?6bh port1sc port 1 status and control 00003000h r/w, r/ wc, ro 6ch?6fh port2sc port 2 status and control 00003000h r/w, r/ wc, ro 70h?73h port3sc port 3 status and control 00003000h r/w, r/ wc, ro 74h?77h port4sc port 4 status and control 00003000h r/w, r/ wc, ro 78h?7bh port5sc port 5 status and control 00003000h r/w, r/ wc, ro 7ch?7fh port6sc port 6 status and control 00003000h r/w, r/ wc, ro 80h?83h port7sc port 7 status and control 00003000h r/w, r/ wc, ro
datasheet 251 ehci host controller (d29:f7) 13.3.2.1 usb2.0_cmd?usb 2.0 command register offset: mem_base + 20?23h attribute: r/w, ro default value: 00080000h size: 32 bits bit default and access description 31:24 00h ro reserved. these bits are reserved and sh ould be set to 0 when writing this register. 23:16 08h r/w interrupt threshold control : system software uses this field to select the maximum rate at which the host co ntroller will issue interrupts. the only valid values are defined below. if software writes an invalid value to this register, the results are undefined. 15:12 0h ro reserved. these bits are reserved and sh ould be set to 0 when writing this register. 11:8 0h ro unimplemented asynchronous park mode : hardwired to 0h indicating the host controller does not support this optional feature. 7 0 ro light host controller reset : hardwired to 0. the intel? sch does not implement this optional reset. 6 0 r/w interrupt on async advance doorbell : this bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. 0 = the host controller sets this bit to a 0 after it has set the interrupt on async advance status bi t (d29:f7:caplength + 24h, bit 5) in the usb2.0_sts register to a 1. 1 = software must write a 1 to this bit to ring the doorbell. when the host controller has evicted all appropriate cached schedule state, it sets the interrupt on async advance status bi t in the usb2.0_sts register. if the interrupt on async advance enable bit in the usb2.0_intr register (d29:f7:caplength + 28h, bit 5) is a 1 then the host controller will assert an interrupt at the next interru pt threshold. see the ehci specification for operational details. note: software should not write a 1 to this bit when the asynchronous schedule is inactive. doing so will yield undefined results. 5 0 r/w asynchronous schedule enable : default 0b. this bit controls whether the host controller skips processing the asynchronous schedule. 0 = do not process the asynchronous schedule 1 = use the asynclistaddr register to access the asynchronous schedule. 4 0 r/w periodic schedule enable : default 0b. this bit controls whether the host controller skips processing the periodic schedule. 0 = do not process the periodic schedule 1 = use the periodiclistbase register to access the periodic schedule. value maximum interrupt interval 00h reserved 01h 1 micro-frame 02h 2 micro-frames 04h 4 micro-frames 08h 8 micro-frames (= ~1 ms) (default) 10h 16 micro-frames (2 ms) 20h 32 micro-frames (4 ms) 40h 64 micro-frames (8 ms)
ehci host controller (d29:f7) 252 datasheet note: the command register indicates the command to be executed by the serial bus host controller. writing to the register causes a command to be executed. 3:2 0 ro frame list size : the intel? sch ha rdwires this field to 00b because it only supports the 1024-element frame list size. 1 0 r/w host controller reset (hcreset) : this control bit us ed by software to reset the host controller. the effects of this on root hub registers are similar to a chip hardware reset (i.e., rsmrst# as sertion and pwrok deassertion on the intel? sch). when software writes a 1 to this bit, the host contro ller resets its internal pipelines, timers, counters, state machines, etc. to their initial value. any transaction currently in progress on usb is immediately terminated. a usb reset is not driven on downstream ports. note: pci configuration registers and host controller capability registers are not effected by this reset. all operational registers, including po rt registers and port state machines are set to their initial values. port ow nership reverts to the companion host controller(s), with the si de effects described in the ehci spec. software must re-initialize the host controller in order to return the host controller to an operational state. this bit is set to 0 by the host co ntroller when the reset process is complete. software cannot terminate th e reset process early by writing a 0 to this register. software should not set this bi t to a 1 when the hchalted bit (d29:f7:caplength + 24h, bit 12) in the usb2.0_sts register is a 0. attempting to reset an actively runni ng host controller will result in undefined behavior. this re set me be used to leav e ehci port test modes. 0 0 r/w run/stop (rs) : 0 = stop (default) 1 = run. when set to a 1, the host co ntroller proceeds with execution of the schedule. the host controller continues execution as long as this bit is set. when this bit is set to 0, the host controller completes the current transaction on the usb and then halts. the hchalted bit in the usb2.0_sts register indicates when the host controller has finished the transaction and has entered the stopped state. software should not write a 1 to this field unless the host controller is in the halted state (i.e., hchalted in the usbsts register is a 1). the halted bit is cleared immediately when the run bit is set. the following table explains how the different combinations of run and halted should be interpreted: memory read cycles initiated by the ehci that receive any status other than successful will result in this bit being cleared. bit default and access description run/stop halted interpretation 0b 0b in the process of halting 0b 1b halted 1b 0b running 1b 1b invalid - the hchalted bit clears immediately
datasheet 253 ehci host controller (d29:f7) 13.3.2.2 usb2.0_sts?usb 2.0 status register offset: mem_base + 24h?27h attribute: r/wc, ro default value: 00001000h size: 32 bits this register indicates pending interrupts and various states of the ehci controller. the status resulting from a transaction on the serial bus is not indicated in this register. see the interrupts description in section 4 of the ehci specification for additional information concerning usb 2.0 interrupt conditions. note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 has no effect. bit default and access description 31:16 0000h ro reserved. these bits are reserved and sh ould be set to 0 when writing this register. 15 0 ro asynchronous schedule status : this bit reports the current real status of the asynchronous schedule. 0 = status of the asynchronous schedule is disabled. (default) 1 = status of the asynchronous schedule is enabled. note: the host controller is not required to immediately disable or enable the asynchronous schedule wh en software transitions the asynchronous schedule enable bit (d29:f7:caplength + 20h, bit 5) in the usb2.0_cmd register. when this bit and the asynchronous schedule enable bit are the same value, the asynchronous schedule is either enabled (1) or disabled (0). 14 0 ro periodic schedule status : this bit reports the curre nt real status of the periodic schedule. 0 = status of the periodic schedule is disabled. (default) 1 = status of the periodic schedule is enabled. note: the host controller is not required to immediately disable or enable the periodic schedule when software transitions the periodic schedule enable bit (d29:f7:caplength + 20h, bit 4) in the usb2.0_cmd register. when this bit and the periodic schedule enable bit are the same value, the periodic schedule is either enabled (1) or disabled (0). 13 0 ro reclamation 0 = this read-only status bit is used to detect an em pty asynchronous schedule. the operationa l model and valid transitions for this bit are described in section 4 of the ehci specification. 12 1 ro hchalted 0 = this bit is a 0 when the run/stop bit is a 1. 1 = the host controller sets this bit to 1 after it has stopped executing as a result of the run/stop bit being set to 0, either by software or by the host controller hardware (e.g ., internal error). (default) 11:6 00h ro reserved 5 0 r/wc interrupt on async advance : 0=default. system so ftware can force the host controller to issue an interrupt the next time the host controller advances the asynchronous sche dule by writing a 1 to the interrupt on async advance doorbell bit (d29:f7:caplength + 20h, bit 6) in the usb2.0_cmd register. this bit indica tes the assertion of that interrupt source.
ehci host controller (d29:f7) 254 datasheet 4 0 r/wc host system error 0 = no serious error occurred during a host system access involving the host controller module 1 = the host controller sets this bit to 1 when a serious error occurs during a host system access involving the host controller module. a hardware interrupt is generated to the system . memory read cycles initiated by the ehci that receive any status other than successful will result in this bit being set. when this error occurs, th e host controller clears the run/stop bit in the usb2.0_cmdregister (d29:f7:caplength + 20h, bit 0) to prevent further execution of the scheduled tds. a hard ware interrupt is generated to the system (if enabled in the in terrupt enable register). 3 0 r/wc frame list rollover 0 = no frame list index rollover from its maximum value to 0. 1 = the host controller sets this bit to a 1 when the frame list index (see section) rolls over from its maximum value to 0. since the intel? sch only supports the 1024-entry frame list size, the frame list index rolls over every time frnum13 toggles. 2 0 r/wc port change detect : this bit is allowed to be maintained in the auxiliary power well. alternatively, it is also acceptable that on a d3 to d0 transition of the ehci hc device, this bit is load ed with the or of all of the portsc change bits (including: force port resume, over current change, enable/ disable change and co nnect status change). regardless of the implementation, when this bit is readab le (i.e., in the d0 state), it must provide a valid view of the port status registers. 0 = no change bit transition from a 0 to 1 or no force port resume bit transition from 0 to 1 as a result of a j-k transition detected on a suspended port. 1 = the host controller sets this bi t to 1 when any port for which the port owner bit is set to 0 has a change bit tr ansition from a 0 to 1 or a force port resume bit transition from 0 to 1 as a result of a j-k transition detected on a suspended port. 1 0 r/wc usb error interrupt (usberrint) 0 = no error condition. 1 = the host controller sets this bit to 1 when completion of a usb transaction results in an error condit ion (e.g., error counter underflow). if the td on which the error interrup t occurred also had its ioc bit set, both this bit and bit 0 are set. see the ehci specification for a list of the usb errors that will result in this interrupt being asserted. 0 0 r/wc usb interrupt (usbint) 0 = no completion of a usb transaction whose transfer descriptor had its ioc bit set. no short packet is detected. 1 = the host controller sets this bit to 1 when the cause of an interrupt is a completion of a usb transaction whose transfer descriptor had its ioc bit set. the host controller also sets this bit to 1 when a short packet is detected (actual number of bytes re ceived was less than the expected number of bytes). bit default and access description
datasheet 255 ehci host controller (d29:f7) 13.3.2.3 usb2.0_intr?usb 2.0 interrupt enable register offset: mem_base + 28h?2bh attribute: r/w default value: 00000000h size: 32 bits this register enables and disables report ing of the corresponding interrupt to the software. when a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. interrupt sources that ar e disabled in this register still appear in the usb2.0_sts register to allow the software to poll for events. each interrupt enable bit description indicates whether it is depe ndent on the interrupt threshold mechanism (see section 4 of the ehci specification), or not. bit default and access description 31:6 0000000h ro reserved. these bits are reserved and should be 0 when writing this register. 5 0 r/w interrupt on async advance enable 0 = disable. 1 = enable. when this bit is a 1, and the interrupt on async advance bit (d29:f7:caplength + 24h, bit 5) in the usb2.0_sts register is a 1, the host controller will issue an interrupt at th e next interrupt threshold. the interrupt is acknowledged by so ftware clearing the interrupt on async advance bit. 4 0 r/w host system error enable 0 = disable. 1 = enable. when this bit is a 1, an d the host system error status bit (d29:f7:caplength + 24h, bit 4) in the usb2.0_sts register is a 1, the host controller will issue an interrupt. the interrupt is acknowledged by software cleari ng the host system error bit. 3 0 r/w frame list rollover enable 0 = disable. 1 = enable. when this bit is a 1, and the frame list rollover bit (d29:f7:caplength + 24h, bit 3) in the usb2.0_sts register is a 1, the host controller will issue an interrupt. the interrupt is acknowledged by software clearing the frame list rollover bit. 2 0 r/w port change interrupt enable 0 = disable. 1 = enable. when this bit is a 1, and the port ch ange detect bit (d29:f7:caplength + 24h, bit 2) in the usb2.0_sts register is a 1, the host controller will issue an interrupt. the interrupt is acknowledged by software clearing the port chan ge detect bit. 1 0 r/w usb error interrupt enable 0 = disable. 1 = enable. when this bit is a 1, and the usberrint bit (d29:f7:caplength + 24h, bit 1) in the usb2.0_sts register is a 1, the host controller will issue an interrupt at th e next interrupt threshold. the interrupt is acknowledged by soft ware by clearing the usberrint bit in the usb2.0_sts register. 0 0 r/w usb interrupt enable 0 = disable. 1 = enable. when this bit is a 1, and the usbint bit (d29:f7:caplength + 24h, bit 0) in the usb2.0_sts regi ster is a 1, the host controller will issue an interrupt at the next interrupt threshold. the interrupt is acknowledged by software by cl earing the usbint bit in the usb2.0_sts register.
ehci host controller (d29:f7) 256 datasheet 13.3.2.4 frindex?frame index register offset: mem_base + 2ch?2fh attribute: r/w default value: 00000000h size: 32 bits the sof frame number value for the bus sof token is derived or alternatively managed from this register. refer to section 4 of the ehci specification for a detailed explanation of the sof value management requirements on the host controller. the value of frindex must be within 125 s (1 micro-fr ame) ahead of the sof token value. the sof value may be implemented as an 11-bit shadow register. for this discussion, this shadow register is 11 bits and is named sofv. sofv updates every 8 micro-frames (1 millisecond). an example implementation to achieve this behavior is to increment sofv each time the frindex[2:0] increments from 0 to 1. software must use the value of frindex to derive the current micro-frame number, both for high-speed isochronous sche duling purposes and to provide the get micro- frame number function required to client dr ivers. therefore, the value of frindex and the value of sofv must be kept consistent if chip is reset or software writes to frindex. writes to frindex must also write-through frindex[13:3] to sofv[10:0]. to keep the update as simple as possible, software should never write a frindex value where the three least significant bits are 111b or 000b. note: this register is used by the host controller to index into the periodic frame list. the register updates every 125 microseconds (once each micro-frame). bits 12:3 are used to select a particular entry in the periodic frame list during periodic schedule execution. the number of bits used for the in dex is fixed at 10 for the intel? sch since it only supports 1024-entry fr ame lists. this register must be written as a dword. word and byte writes produce undefined results. this register cannot be written unless the host controller is in the halted state as indicated by the hchalted bit (d29:f7:caplength + 24h, bit 12). a write to this register while the run/stop bit (d29:f7:caplength + 20h, bit 0) is set to a 1 (usb2.0_cmd register) produces undefined results. writes to this register also effect the sof value. see section 4 of the ehci specification for details. bit default and access description 31:14 00000h ro reserved 13:0 0000h r/w frame list current index/frame number : the value in this register increments at the end of each time frame (e.g., micro-frame). bits 12:3 are used for the frame list current index. this means that each location of the frame list is access ed 8 times (frames or micro-frames) before moving to the next index.
datasheet 257 ehci host controller (d29:f7) 13.3.2.5 ctrldssegment?control da ta structure segment register offset: mem_base + 30h?33h attribute: r/w, ro default value: 00000000h size: 32 bits this 32-bit register corresponds to the most significant address bits 63:32 for all ehci data structures. since the intel? sch hardwires the 64-bit addressing capability field in hccparams to 1, then this register is used with the link pointers to construct 64-bit addresses to ehci control data structures. this register is concatenated with the link pointer from either the periodiclistb ase, asynclistaddr, or any control data structure link field to construct a 64-bit address. this register allows the host software to locate all control data structures within the same 4 gb memory segment. 13.3.2.6 periodiclistbase?periodic frame list base address register offset: mem_base + 34h?37h attribute: r/w default value: 00000000h size: 32 bits this 32-bit register contains the beginning address of the periodic frame list in the system memory. since the intel? sch host controller operates in 64-bit mode (as indicated by the 1 in the 64-bit addressi ng capability field in the hccsparams register) (offset 08h, bit 0), then the most significant 32 bits of every control data structure address comes from the ctrldssegment register. hcd loads this register prior to starting the schedule execution by the host controller. the memory structure referenced by this physical memory poin ter is assumed to be 4 kb aligned. the contents of this register are combined with the frame index register (frindex) to enable the host controller to step through the periodic frame list in sequence. bit default and access description 31:12 00000h r/w upper address[63:44] : hardwired to 0s. the ehci is only capable of generating addresses up to 16 terabytes (44 bits of address). 11:0 000h r/w upper address[43:32] : this 12-bit field corresp onds to address bits 43:32 when forming a contro l data structure address. bit default and access description 31:12 00000h r/w base address (low) : these bits correspond to memory address signals 31:12, respectively. 11:0 000h r/w reserved: must be written as 0s. during runtime, the value of these bits are undefined.
ehci host controller (d29:f7) 258 datasheet 13.3.2.7 asynclistaddr?current asyn chronous list address register offset: mem_base + 38h?3bh attribute: r/w default value: 00000000h size: 32 bits this 32-bit register contains the address of the next asynchronous queue head to be executed. since the intel? sch host controller operates in 64-bit mode (as indicated by a 1 in 64-bit addressing capability field in the hccparams register) (offset 08h, bit 0), then the most significant 32 bits of every control data structure address comes from the ctrldssegment register (offset 08h). bits 4:0 of this register cannot be modified by system software and will always retu rn 0s when read. the memory structure referenced by this physical memory poin ter is assumed to be 32-byte aligned. 13.3.2.8 configflag?configure flag register offset: mem_base + 60h?63h attribute: r/w default value: 00000000h size: 32 bits this register is in the suspend power well. it is only reset by hardware when the suspend power is initially applied or in response to a host controller reset. bit default and access description 31:5 0000000h r/w link pointer low (lpl) : these bits correspon d to memory address signals 31:5, respectively. this fiel d may only reference a queue head (qh). 4:0 0h ro reserved: these bits are reserved and their value has no effect on operation. bit default and access description 31:1 00000000h ro reserved. read from this field will always return 0. 0 0 r/w configure flag (cf) : host software sets this bit as the last action in its process of configuring the host controller. this bit controls the default port-routing control logic. bit values and side-effects are listed below. see section 4 of the ehci spec for operation details. port routing control logic default-rout es each port to the uhcis (default). port routing control logic default-routes all ports to this host controller.
datasheet 259 ehci host controller (d29:f7) 13.3.2.9 port[7:0]sc?port n status and control register offset: port0sc: mem_base + 64h ? 67h port1sc: mem_base + 68h ? 6bh port2sc: mem_base + 6ch ? 6fh port3sc: mem_base + 70h ? 73h port4sc: mem_base + 74h ? 77h port5sc: mem_base + 78h ? 7bh port6sc: mem_base + 7ch ? 7fh port7sc: mem_base + 80h ? 83h attribute: r/w, r/wc, ro default value: 00003000h size: 32 bits a host controller must implement one or mo re port registers. software uses the n_ports information from the structural parameters register to determine how many ports need to be serviced. all ports have the structure defined below. software must not write to unreported port status and control registers. this register is in the suspend power well. it is only reset by hardware when the suspend power is initially applied or in resp onse to a host controller reset. the initial conditions of a port are: ? no device connected ?port disabled when a device is attached, the port state transitions to the attached state and system software will process this as with any status change notification. refer to section 4 of the ehci specification for operational requirem ents for how change events interact with port suspend mode. bit default and access description 31:23 0000h ro reserved. these bits are reserved for fu ture use and will return a value of 0s when read. 22 0 r/w wake on overcurrent enable (wkoc_e) : 0 = disable. (default) 1 = enable. writing this bit to a 1 enab les the setting of the pme status bit in the power management control/st atus register (offset 54, bit 15) when the overcurrent active bit (b it 4 of this register) is set. 21 0 r/w wake on disconnect enable (wkdscnnt_e) : 0 = disable. (default) 1 = enable. writing this bit to a 1 enab les the setting of the pme status bit in the power management control/st atus register (offset 54, bit 15) when the current connect stat us changes from connected to disconnected (i.e., bit 0 of th is register chan ges from 1-to-0). 20 0 r/w wake on connect enable (wkcnnt_e) : 0 = disable. (default) 1 = enable. writing this bit to a 1 enab les the setting of the pme status bit in the power management control/st atus register (offset 54, bit 15) when the current connect status changes from disconnected to connected (i.e., bit 0 of this register chan ges from 0-to-1).
ehci host controller (d29:f7) 260 datasheet 19:16 0h r/w port test control (ptc) : when this field is 0s, the port is not operating in a test mode. a non-zero value indicates that it is operating in test mode and the specific test mode is indicate d by the specific value. the encoding of the test mode bits are (0110b ? 1111b are reserved): refer to usb specification revision 2. 0, chapter 7 for details on each test mode. 15:14 00b ro reserved 13 1 r/w port owner (po) : default = 1b. this bit unconditionally goes to a 0 when the configured flag bit in the us b2.0_cmd register makes a 0 to 1 transition. system software uses this field to release ownership of the port to a selected host controller (in the even t that the attached device is not a high-speed device). soft ware writes a 1 to this bit when the attached device is not a high-speed device. a 1 in this bit means that a companion host controller owns an d controls the port. see section 4 of the ehci specification for operational details. 12 1 ro port power (pp) : read-only with a value of 1. this indicates that the port does have power. 11:10 00b ro line status (ls) : these bits reflect the curren t logical levels of the d+ (bit 11) and d? (bit 10) signal lines. these bits are used for detection of low-speed usb devices prior to the po rt reset and enable sequence. this field is valid only when the port en able bit is 0 and the current connect status bit is set to a 1. 00 = se0 10 = j-state 01 = k-state 11 = undefined. not low spee d device, perform ehci reset. 9 0 ro reserved. this bit will return a 0 when read. bit default and access description value maximum interrupt interval 0000b test mode not enabled (default) 0001b test j_state 0010b test k_state 0011b test se0_nak 0100b test packet 0101b force_enable
datasheet 261 ehci host controller (d29:f7) 8 0 r/w port reset (pr) : default = 0. when software wr ites a 1 to this bit (from a 0), the bus reset sequence as defined in the usb specification, revision 2.0 is started. software writes a 0 to this bit to terminate the bus reset sequence. software must ke ep this bit at a 1 long enough to ensure the reset sequence completes as specified in the usb specification, revision 2.0 . 1 = port is in reset. 0 = port is not in reset. note: when software writes a 0 to this bit, there may be a delay before the bit status changes to a 0. the bit status will not read as a 0 until after the reset has completed. if the port is in high-speed mode after reset is complete, the ho st controller will automatically enable this port (e.g., set the port enable bit to a 1). a host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of soft ware transitioning this bit from 0-to-1. for example: if the port detects th at the attached device is high- speed during reset, then the host controller must have the port in the enabled state within 2 ms of software writing this bit to a 0. the hchalted bit (d29:f7:caplength + 24h, bit 12) in the usb2.0_sts register should be a 0 before software attempts to use this bit. the host controller may hold port reset asserted to a 1 when the hchalted bit is a 1. th is bit is 0 if port power is 0. note: system software should not at tempt to reset a port if the hchalted bit in the usb2.0_sts register is a 1. doing so will result in undefined behavior. 7 0 r/w suspend (sus) 0 = port not in susp end state.(default) 1 = port in suspend state. port enabled bit and suspend bit of this register define th e port states as follows: when in suspend state, downstream prop agation of data is blocked on this port, except for port reset. note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port depending on the acti vity on the port. the host controller will unconditionall y set this bit to a 0 when software sets the force port resume bit to a 0 (from a 1). a write of 0 to this bit is ignored by the host controller. if host software sets this bit to a 1 wh en the port is not enabled (i.e., port enabled bit is a 0) the results are undefined. bit default and access description port enabled suspend port state 0xdisabled 10enabled 11suspend
ehci host controller (d29:f7) 262 datasheet 6 0 r/w force port resume (fpr) 0 = no resume (k-state) detected/driven on port. (default) 1 = resume detected/driven on port. soft ware sets this bit to a 1 to drive resume signaling. the host controller sets this bit to a 1 if a j-to-k transition is detected while the port is in the suspend state. when this bit transitions to a 1 because a j-to-k transition is detected, the port change detect bit (d29:f7:ca plength + 24h, bit 2) in the usb2.0_sts register is also set to a 1. if software sets this bit to a 1, the host controller must not se t the port change detect bit. note: when the ehci controller owns the port, the resume sequence follows the defined sequence docume nted in the usb specification, revision 2.0. the resume signaling (full-speed 'k') is driven on the port as long as this bit remains a 1. software mu st appropriately time the resume and set this bit to a 0 when the appropriate amount of time has elapsed. writing a 0 (from 1) causes the port to return to high-speed mode (forci ng the bus below the port into a high-speed idle). this bit will remain a 1 until the port has switched to the high-speed idle. 5 0 r/wc overcurrent change (occ) : the functionality of this bit is not dependent upon the port owne r. software clears this bit by writing a 1 to it. 0 = no change. (default) 1 = there is a change to overcurrent active. 4 0 ro overcurrent active (oca) 0 = this port does not have an overcurrent condition. (default) 1 = this port currently has an over current condition. this bit will automatically transition from 1 to 0 when the over current condition is removed. the intel? sch automatica lly disables the port when the overcurrent active bit is 1. 3 0 r/wc port enable/disable change (pedc) : for the root hub, this bit gets set to a 1 only when a port is disabled due to the appropriate conditions existing at the eof2 point (see chapte r 11 of the usb specification for the definition of a port error) . this bit is not set due to the disabled-to-enabled transition, nor due to a disconnect. softwa re clears this bit by writing a 1 to it. 0 = no change in status. (default). 1 = port enabled/disabled status has changed. 2 0 r/w port enabled/disabled (ped) : ports can only be enabled by the host controller as a part of the reset and enable. software cann ot enable a port by writing a 1 to this bit. ports can be disabled by either a fault condition (disconnect event or other fault co ndition) or by host software. note that the bit status does not change until th e port state actual ly changes. there may be a delay in disabling or enabling a port due to other host controller and bus events. 0 = disable 1 = enable (default) bit default and access description
datasheet 263 ehci host controller (d29:f7) 13.3.3 usb 2.0 based debug port register the debug port?s registers are located in th e same memory area, defined by the base address register (mem_base), as the standard ehci registers. the base offset for the debug port registers (a0h) is declared in the debug port base offset capability register at configuration offset 5ah (d29:f7:offset 5ah). the address map of the debug port registers is shown in ta b l e 3 8 . notes: 1. all of these registers are implemented in the core well and re set by reset#, ehci hcreset, and a ehci d3-to-d0 transition . 2. the hardware associated with this register provides no chec ks to ensure that software programs the interface correct ly. how the hardware behaves when programmed in an invalid manner is undefined. 1 0 r/wc connect status change (csc) : this bit indicates a change has occurred in the port?s current connect status. so ftware sets this bit to 0 by writing a 1 to it. 0 = no change (default). 1 = change in current connect status. th e host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. for example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be ?setting? an already-set bit (i.e., the bit will remain set). 0 0 ro current connect status (ccs) : this value reflects the current state of the port, and may not correspond direct ly to the event that caused the connect status change bi t (bit 1) to be set. 0 = no device is present. (default) 1 = device is present on port. bit default and access description table 38. debug port register address map mem_base + offset mnemonic register name default type a0?a3h cntl_sts control/status 00000000h r/w, r/wc, ro, wo a4?a7h usbpid usb pids 00000000h r/w, ro a8?abh databuf[3:0] data buffer (bytes 3:0) 00000000h r/w ac?afh databuf[7:4] data buffer (bytes 7:4) 00000000h r/w b0?b3h config configuration 00007f01h r/w
ehci host controller (d29:f7) 264 datasheet 13.3.3.1 cntl_sts?control/status register offset: mem_base + a0h attribute: r/w, r/wc, ro, wo default value: 0000h size: 32 bits bit default and access description 31 ro reserved 30 r/w owner_cnt 0 = ownership of the debug port is not forced to the ehci controller (default) 1 = ownership of the debug port is forced to the ehci controller (i.e., immediately taken away fro m the companion classic usb host controller) if the port was already owned by the ehci controller, then setting this bit has no effe ct. this bit overrides all of the ownership-related bits in th e standard ehci registers. 29 ro reserved 28 r/w enabled_cnt 0 = software can clear this by writing a 0 to it. the hardware clears this bit for the same conditions where the port enable/disable change bit (in the portsc register) is set. (default) 1 = debug port is enabled for operatio n. software can directly set this bit if the port is already enabled in the associated portsc register (this is enforced by the hardware). 27:17 ro reserved 16 r/wc done_sts : software can clear this by writing a 1 to it. 0 = request not complete 1 = set by hardware to indicate that the request is complete. 15:12 ro link_id_sts : this field identifies the link interface. 0h = hardwired. indicates th at it is a usb debug port. 11 ro reserved. this bit returns 0 when read. wr ites have no effect. 10 r/w in_use_cnt : set by software to indicate that the port is in use. cleared by software to in dicate that the port is free and may be used by other software. this bit is cleared afte r reset. (this bit has no effect on hardware.) 9:7 ro exception_sts : this field indicates the exception when the error_good#_sts bit is set. this field should be ignored if the error_good#_sts bit is 0. 000 = no error. (default) note : this should not be seen, si nce this field should only be checked if there is an error. 001 = transaction error: indicates the usb 2.0 transaction had an error (crc, bad pid, timeout, etc.) 010 = hardware error. request was attempted (or in progress) when port was suspended or reset. all other combinations are reserved
datasheet 265 ehci host controller (d29:f7) notes: 1. software should do read-modify-write operations to this register to preserve the contents of bits not being modified. this include reserved bits. 2. to preserve the usage of reserved bits in the future, software sh ould always write the same value read from the bit unti l it is defined. reserved bits will always return 0 when read. 6ro error_good#_sts 0 = hardware clears this bit to 0 after the proper completion of a read or write. (default) 1 = error has occurred. details on the nature of the error are provided in the exception field. 5 wo r/w go_cnt ? wo 0 = hardware clears this bit when hardware sets the done_sts bit. (default) 1 = causes hardware to perform a read or wr ite request. note: writing a 1 to this bit when it is already set may result in undefined behavior. 4 0 r/w write_read#_cnt : software clears this bi t to indicate that the current request is a read. software se ts this bit to indicate that the current request is a write. 0 = read (default) 1 = write 3:0 r/w data_len_cnt : this field is used to indicate the size of the data to be transferred. default = 0h. for write operations, this field is se t by software to indicate to the hardware how many bytes of data in data buffer are to be transferred to the console. a value of 0h indicates that a zero-length packet should be sent. a value of 1?8 indicates 1?8 bytes are to be transferred. values 9? fh are invalid and how hardware behaves if used is undefined. for read operations, this field is set by hardware to indicate to software how many bytes in data buffer are valid in response to a read operation. a value of 0h indicates that a zero length packet was returned and the state of data buffer is not defined. a value of 1?8 indicates 1?8 bytes were received. hardware is not allowed to return values 9?fh. the transferring of data always starts with byte 0 in the data area and moves toward byte 7 until the transfer size is reached. bit default and access description
ehci host controller (d29:f7) 266 datasheet 13.3.3.2 usbpid?usb pids register offset: mem_base + a4h attribute: r/w, ro default value: 0000h size: 32 bits this dword register is used to communica te pid information between the usb debug driver and the usb debug port. the debug port uses some of these fields to generate usb packets, and uses other fields to retu rn pid information to the usb debug driver. 13.3.3.3 databuf[7:0]?data buffer bytes [7:0] register offset: mem_base + a8h?afh attribute: r/w default value: 0000000000000000h size: 64 bits this register can be accessed as 8 separate 8-bit registers or 2 separate 32-bit register. bit default and access description 31:24 00h ro reserved: these bits will return 0 when read. writes will have no effect. 23:16 00h ro received_pid_sts : hardware updates this field with the received pid for transactions in either direct ion. when the controller is writing data, this field is upda ted with the handshake pi d that is received from the device. when the host controller is reading data, this field is updated with the data packet pid (if the devi ce sent data), or the handshake pid (if the device naks the request). this field is valid when the hardware clears the go_done#_cnt bit. 15:8 00h r/w send_pid_cnt: hardware sends this pid to begin the data packet when sending data to usb (i.e., write_read#_cnt is asserted). software typically sets this field to either data0 or data1 pid values. 7:0 00h r/w token_pid_cnt : hardware sends this pid as the token pid for each usb transaction. software typically sets this field to either in, out, or setup pid values. bit default and access description 63:0 0s r/w databuffer[63:0] : this field is the 8 bytes of the data buffer. bits 7:0 correspond to least significant byte (byte 0). bits 63:56 correspond to the most significant byte (byte 7). the bytes in the data buffer must be written with data before software initiates a write request. for a read request, the data buffer contains valid data when done_sts bit (offs et a0, bit 16) is cleared by the hardware, error_good#_sts (offset a0, bit 6) is cleared by the hardware, and the data_length_cn t field (offset a0, bits 3:0) indicates the number of bytes that are valid.
datasheet 267 ehci host controller (d29:f7) 13.3.3.4 config?configuration register offset: mem_base + b0?b3h attribute: r/w default value: 00007f01h size: 32 bits bit default and access description 31:15 0000h ro reserved 14:8 7fh r/w usb_address_cnf : the usb device address used by the controller for all token pid generation. 7:4 0h ro reserved 3:0 1h r/w usb_endpoint_cnf : this 4-bit field identi fies the endpoint of all to ke n p i d s .
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datasheet 269 usb client controller (d26:f0) 14 usb client controller (d26:f0) the intel? sch usb client implements a so ftware defined usb device. this allows a platform based on the intel? sch chipset to connect to other platforms implementing a usb host interface for purposes of file transfer, network connectivity, or any other functionality that can be implemented as a usb device. this usb client implementation provides very little hardware acceleration or assistance, and is optimized for flexibility and hardware simplicity. software is responsible for almost all behaviors above the usb protocol layer and dma, including handling usb descriptors, transaction leve l formatting, and implementing defined device classes. 14.1 functional description the intel? sch contains a universal serial bu s 2.0 client controller. the usb client is configured to operate on usb port 2. the serial information transmitted and receiv ed by the usb client contains layers of communication protocols. these communication protocols are defined by universal serial bus specification , revision 2.0 . the most basic of these protocols are defined within fields. examples of these usb fields include: sync, packet identifier, address, endpoint, frame number, data, and crc. fields are used to produce packets . depending on the packet function, a different combination and number of fields can be us ed. packet types include: token, data, and handshake. token packets may be of several types including start of frame, and ping (high-speed). packets are assembled to produce transactions . transactions fall into six groups: data in, data out, sof, setup, status and ping (h s). data flow is relative to the usb host controller. in packets represent data flow from the usb client to the usb host controller. out packets represent data flow from the usb host controller to the usb client. sof transactions signify the start of a new frame. setup and status transactions are used for control transfers. ping transactions are used in high-speed mode to assist with bulk transfers. some sets of transactions together make up transfers and are used to transfer data between the host and device. transfers fall in to four groups: bulk, control, interrupt, and isochronous. sof and ping transactions are not components of transfers. the term transfer may refer to a set of related data tran sfer transactions within a single frame/ frame (hs) such as for a bulk transfer which may transfer an amount of data split into many packets of related data within a single frame/ frame (hs), or it may refer to related data transferred across several frames/ frames (hs), such as for an interrupt transfer. transactions are strung together into frames for low-speed and full-speed operation modes, or frames during high-speed mode. while a transfer refers to transactions with related data, but not necessarily in any specific order, frames and frames represent a series of transactions put togeth er in the order which will be observed on the usb bus, but not necessarily having related data. figure 5 graphically represents the communication layers in the protocol. see universal serial bus specification , revision 2.0 for more details on usb protocol. the usb host controller referenced in this chapter refers to any universal serial bus specification -compliant usb host controller.
usb client controller (d26:f0) 270 datasheet software is responsible for handling all tran sactions, including setup transactions, with the exception of the set_address transaction. in contrast to other hardware designs available in the industry which may rely on hardware to handle us b interface descriptor requests and property get/set operations , the intel? sch usb client relies on software to handle these operations. softwa re must, in a timely manner, process all packets received on out endpoints, and wh ere required provide the requested data through the appropriate in endpoint. 14.2 operation the intel? sch usb client device is constr ucted of a series of endpoints which use dma engines to transfer data between the usb controller and memory. endpoints 0_in and 0_out are always implemented as the default control endpoint and represent the default way that the host software communicates with the device to determine capabilities, configure option s, and select interfaces. the intel? sch supports six other end points, known as 1_in, 1_out, 2_in, 2_out, 3_in, and 3_out. these additional endpoints may be configured as needed, such as a set of bulk in and bulk out endpoints, to facilitate data transfer. as an example, a communications class device will use the endpoint 0 in and out as a control pipe, and endpoint 1_in and 1_out as a data class pipe to transfer packets. figure 5. communication protocol la yers in the usb client controller sync packet identifier address endpoint frame data crc fields token data handshake packets sof data in data out setup status ping (hs) transactions frames / nframes (hs) isochronous interrupt bulk control
datasheet 271 usb client controller (d26:f0) dma engines are associated with the endpoints which transfer the data being transferred to or from the host from the client system ram. the dma engine for a particular endpoint must be configured before data can be exchanged with the host. transfers (exchanges between client and host) are comprised of zero to many data packets which contain a number of bytes equal to the max packet size, and a last packet containing fewer bytes (including zero-length packets) known as a short packet. for instance, to transfer a 1500-byte ethern et frame, a client may provide a 1024-byte packet followed by a 478-byte short packet. in many interface class definition, the receiver implicitly understands that the tran sfer is complete when it sees the short packet. in other usage models (such as streaming video) the stream may simply be a large number of bytes, where the transfer framing information is contained within the data format itself. a bulk in endpoint may be used to send available bytes when the host asks for them. packets are made of individual phases. different phases and token types to different endpoint types: ? control endpoint use setup pid, data0/1 phases, and ack phase ? bulk endpoints use in/out pid, data0/1 phases, and ack phase ? isoch endpoints use in/out pid and data0 phases only ? interrupt endpoints use in/out pid, data0/1 phases, and ack phase. important hardware requirements: ? hardware must identify destination by matching packet address on packet and handling based on endpoint address and direction. ? hardware must handle data0/1 toggling fo r control, interrupt, and bulk endpoints ? hardware must generate (in) or check (out) crc of packet (except in control dma mode) ? hardware must handle the sof token by placing the frame number in the frame register ? hardware must detect short packets ? hardware must ack packets received properly, and nak packets with errors ? hardware must nak packets if there is no data to send or no room in the receive buffer ? hardware must detect bus conditions, such as suspend, resume, and reset, and report the conditions to the software. 14.2.1 usb features ? usb revision 2.0, high-speed/full-speed compliant device ? eight, concurrent programmable endpoints ? programmable endpoint type: bulk, isochronous, or interrupt ? programmable endpoint maximum packet size ? 4 ?in? endpoints, and 4 ?out? endpoints ? interface and endpoint requests handled entirely by software ? 1 in and 1 out endpoint used as ep0 control pipe ? automatic hardware handling of set_address
usb client controller (d26:f0) 272 datasheet 14.2.2 dma features ? supports aligned and unaligned transfers to and from system memory. ? supports 4 in (client memory to usb) and 4 out (usb to client memory) endpoints. ? supports control, linear, and scatter gath er modes of operation to allow efficient use of client system memory. ? retrieves trailing bytes in the receive endpoint fifos. ? supports up to 4 gbytes of data transfer per descriptor. packets longer than the defined max packet size are automatically transferred as multiple packets. ? control mode dma supports placing all packet information (including pid) from a single transaction in the dma buffer ? linear and scatter/gather dma modes for out/in endpoints place/fetch the data phase of multiple usb transactions to/fro m the same endpoint linearly in memory to optimize lengthy transfers. ? automatic nak support for endpoints which do not yet have data ready. 14.2.3 reset the usb client port may be reset by either a device reset message from the intel? sch?s internal message bus or using a usb reset packet from the usb host. 14.2.4 pci device reset clear all mmio registers to reset values, flush fifo, and initialize all state machines to their power on condition. on the usb bus, if the client is currently connected to the usb host, the client signal disconnect/reconnect 14.2.5 wake of client the intel? sch usb client does not issue pme# interrupts which would wake the system from a sleep state. 14.2.6 wake of host (usb resume) the dev_ctrl.signalresume bit allows the clie nt device to signal resume to the host while the link is in the suspend state. this may allow the client to bring the host to s0, or merely resume a link suspended for power reasons. before software sets this bit, it must make sure that the client has been enabled to signal wake. the host os will write a 1 to the ?remote wakeup? bit in the bmattributes field of the standard configuration descripto r to signal that the client may generate resume signaling. software must also make sure that the link has been in the suspend state for at least 5 ms, per usb spec requir ements. software may determine that more than 5 ms has elapsed by monitoring the suspend bit in the device status register. when software writes a 1 to this bit, hardware will generate resume signaling on the link if the link is in the suspend state. soft ware is responsible for knowing whether the device has been enabled to generate th e signaling by the host system, and for ensuring that the link has been in the suspend state for the 5-ms minimum, per usb 2.0 specification, section 7.1.7.7. hardware is responsible for asserting the re sume signaling on the link for the requisite amount of time. when the resume signaling is completed, hardware will clear this bit to a 0. while resume signaling is enabled, so ftware writes to this bit will be ignored.
datasheet 273 usb client controller (d26:f0) 14.3 pci configuration registers note: address locations that are not shown should be treated as reserved. 14.3.1 vid?vendor iden tification register offset address: 00h ? 01h attribute: ro default value: 8086h size: 16 bits table 39. usb client controller pci register address map (d26:f0) offset mnemonic register name default type 00?01h vid vendor identification 8086h ro 02?03h did device identification 8118h ro 04?05h pcicmd pci command 0000h r/w, ro 06?07h pcists pci status 0010h ro 08h rid revision identification see note ro 09h?0bh cc class codes 0c0380h ro 0eh htype header type 00h ro 10?13h mem_base memory base address 00000000h ro, r/w 2c?2fh ss subsystem identification 00000000h r/w 34h cap_ptr capabilities pointer 50h ro 3ch int_ln interrupt line 00h ro 3dh int_pn interrupt pi n see description r/w 40h usbpr usb port routing 02h ro, r/w 50h pm_capid pci power management capability id 01h ro 51h nxt_ptr next item pointer 00h ro 52h?53h pm_cap power management capabilities 0000h ro 54h?55h pm_cntl_sts power management control/ status 00000000h ro, r/w c4h ure usb resume enable 00h ro, r/w fch fd function disable 00000000h ro, r/w bit default and access description 15:0 8086 ro vendor id: this is a 16-bit value assigned to intel.
usb client controller (d26:f0) 274 datasheet 14.3.2 did?device iden tification register offset address: 02h ? 03h attribute: ro default value: 8118h size: 16 bits 14.3.3 pcicmd?pci command register address offset: 04h ? 05h attribute: r/w, ro default value: 0000h size: 16 bits bit default and access description 15:0 8118h ro device id: 8118h assigned to the usb client controller in the intel? sch. bit default and access description 15:11 0 ro reserved 10 0 r/w interrupt disable (id) 0 = the function is capable of generating interrupts. 1 = the function cannot generate its interrupt to the in terrupt controller and it may not generate an msi. note that the corresponding interrupt st atus bit (pcists, bit 3) is not affected by the interrupt enable. 9 0 ro reserved 2 0 r/w bus master enable (bme) 0 = disables this functionality. 1 = enables the usb client to generate bus master cycles. it also controls msi generation since msi are essentially memory writes. 1 0 r/w memory space enable (mse): this bit controls ac cess to the usb 2.0 memory space registers. 0 = disables this functionality. 1 = enables accesses to the usb 2.0 re gisters. the base address register (d29:f7:10h) for usb 2.0 should be programmed before this bit is set. 0 0 ro reserved
datasheet 275 usb client controller (d26:f0) 14.3.4 pcists?pci status register address offset: 06h ? 07h attribute: r/w, ro default value: 0010h size: 16 bits 14.3.5 rid?revision identification register offset address: 08h attribute: ro default value: see bit description size: 8 bits 14.3.6 cc?class codes register address offset: 09h?0bh attribute: ro default value: 0c0380h size: 24 bits bit default and access description 15:5 0 ro reserved 4 1 ro capabilities li st (cap_list): hard wired to 1 indicating that the usb client controller contains a capabi lities pointer list at offset 34h. 3 0 ro interrupt status: this bit reflects the state of this function?s interrupt at the input of the enable/disable logic. 0 = this bit will be 0 when the interrupt is cleared 1 = this bit is a 1 when th e interrupt is asserted the value reported in this bit is inde pendent of the value in the interrupt disable (id) bit in the pcicmd register. 2:0 0 ro reserved bit default and access description 7:0 ro revision id: refer to the intel ? system contro ller hub (intel ? sch) specification update for the value of the revision id register. bit default and access description 23:16 0ch ro base class code (bcc): this register indicates that the function implements a serial bu s controller device. 15:8 03h ro sub class code (scc): indicates that the programming interface is 'not a host', i.e., it's not ehci, uhci, or ohci. 7:0 80h ro programming interface (pi): universal serial bus with no specific programming interface.
usb client controller (d26:f0) 276 datasheet 14.3.7 htype - header type register address offset: 0e attribute: ro default value: 00h size: 8 bits 14.3.8 mem_base? usb client me mory base address register address offset: 10h ? 17h attribute: r/w, ro default value: 00000000h size: 32 bits this base address register creates 2048 by tes of memory space to signify the base address of usb client memory mapped configuration registers. bit default and access description 7:0 00h ro header type (htype): implements a type 0 configuration header. bit default and access description 63:32 0s rw upper address (ua): upper 32 bits of the ba se address for the usb client controller's memo ry mapped configuration re gisters. this may be read-only 0's if 64b address decode is not supported. 31:11 0s r/w lower address (la): base address for the usb client controller's memory mapped configuration registers. 2048 bytes are requested by hardwiring bits 10:4 to 0s. 10:4 0s ro reserved 3 0 ro prefetchable (pref): indicates that this bar is not pre-fetchable. 2:1 10 ro address range (addrng): indicates that this bar can be located anywhere in 64 bit address space. note that this needs to be adjusted if the usbcbaru is implemented as read only to indicate that 64b address decode is not supported. 0 0h ro space type (sptyp): indicates that this bar is located in memory space
datasheet 277 usb client controller (d26:f0) 14.3.9 sid?subsystem id register address offset: 2ch ? 2fh attribute: r/w default value: 00000000h size: 32 bits this register matches the value written to the lpc bridge. 14.3.10 cap_ptr?capabilities pointer register address offset: 34h attribute: ro default value: 50h size: 8 bits 14.3.11 int_ln?interrupt line register address offset: 3ch attribute: r/w default value: 00h size: 8 bits bit default and access description 31:15 0000h rw subsystem id (ssid): these rw bits have no hardware functionality. 15:0 0000h rw subsystem vendor id (svid): these rw bits have no hardware functionality. bit default and access description 7:0 50h ro capability pointer (cp): indicates that the first capability pointer offset is offset 50h bit default and access description 7:0 00h r/w interrupt line (int_ln): this data is not used by the intel? sch. it is used as a scratchpad register to communicate to software the interrupt line that the interrupt pin is connected to.
usb client controller (d26:f0) 278 datasheet 14.3.12 int_pn?interrupt pin register address offset: 3dh attribute: ro default value: see description size: 8 bits 14.3.13 usbpr?usb port routing register address offset: 40h attribute: ro default value: 02h size: 8 bits 14.3.14 pm_capid?pci power ma nagement capability id register address offset: 50h attribute: ro default value: 01h size: 8 bits bit default and access description 7:4 0h ro reserved 3:0 ro interrupt pin: this reflects the value of d26ip.utip (chipset config registers:offset 3114, bits 3:0). bit default and access description 7 0 r/w enableportrouting 0 = usb port 2 will be routed to the usb host controller 1 = usb port 2 will be routed to the usb client controller 6 0 r/w forceportrouting 1 = the usb port indicated by pid will always be routed to the usb client controller, regardless of the state of the external id pin. 0 = the usb port indicated by pid will be routed to the usb controller only when the input gpiosus3 is set to a 1. if is set to 0 and there is a 0 at the gpiosus3 input, the usb client controller will consider the port disconnected. 5:4 00b ro reserved 3:0 02h r/w port id (pid): denotes the binary encoding of the port number to be configured as a client. port 2 is the default. all other values are reserved. bit default and access description 7:0 01h ro power management capability id: a value of 01h indicates that this is a pci power management capabilities field.
datasheet 279 usb client controller (d26:f0) 14.3.15 nxt_ptr?next item pointer register address offset: 51h attribute: r/w (special) default value: 00h size: 8 bits 14.3.16 pm_cap?power manageme nt capabilities register address offset: 52h ? 53h attribute: r/w (special), ro default value: 0002h size: 16 bits bit default and access description 7:0 00h r/w next item pointer 1 value (nxt_ptr1): this register indicates that this is the last capability in the list. bit default and access description 15:11 11001b ro pme support (pme_sup): indicates pme# can be generated from only d0 states. 10 0b ro d2_support: the d2 state is not supported. 9 0b ro d1_support: the d1 state is not supported. 8:6 000b ro auxiliary current (aux_cur) (special): reports 0ma maximum suspend well current required when in the d3 cold state. 5 0 ro device specific initialization (dsi): indicates that no device-specific initialization is required. 4 0 ro reserved 4 0 ro pme clock (pmec): does not apply. hard wired to 0. 2:0 010b ro version (ver): indicates that it complies with revision 1.1 of the pci power management specification .
usb client controller (d26:f0) 280 datasheet 14.3.17 pm_cntl_sts?power ma nagement control/status register address offset: 54h ? 55h attribute: r/w, ro default value: 00000000h size: 32bits note: reset (bits 15, 8): suspend well, and not d3 -to-d0 warm reset no r core well reset. bit default and access description 31:24 00h ro data: no data 23 0b ro bus power/clock control enable (bpcce): does not apply. hard wired to 0. 22 0b ro b2/b3 support (b23): does not apply. hard wired to 0. 21:2 0...0b ro reserved 1:0 00b r/w power state (ps): this field is used both to determine the current power state of the usb client controller and to set a new power state. the values are: 00 = d0 state 01 = reserved 10 = reserves 11 = d3 hot state when in d3 hot , the usb client controller?s configuration space is available, but the i/o and memory spaces are not. additionally, interrupts are blocked. when software change s this value from d3 hot to d0, an internal warm (soft) reset is generated, and softwa re must re-initial ize the function.
datasheet 281 usb client controller (d26:f0) 14.3.18 ure?usb resume enable address offset: c4h attribute: r/w, ro default value: 00000000h size: 32bits 14.3.19 fd?function disable register address offset: fch attribute: r/w default value: 00000000h size: 32 bits bit default and access description 7:1 0s ro reserved 0 0b r/w port 0 enable (p0e): when set, uhc monitors port 0 for wakeup and connect/disconnect events. bit default and access description 31:3 0000h ro reserved 2 0 r/w clock gating disable (cgd): when set, clock gating within the function is disabled. when cleare d, clock gating within the function is enabled. 1 0 ro reserved 0 0 r/w disable (d): when set, the function is di sabled (configura tion space is disabled).
usb client controller (d26:f0) 282 datasheet 14.4 memory-mapped i/o registers table 40. usb client i/o registers (she et 1 of 2) mem_base +offset mnemonic register default type 000?003h gcap global capabilities 4007000h ro 100?103h dev_sts device status 00000000h ro 104?107h frame frame number 00000000h ro 10c?10fh int_sts interrupt status 00000000h ro, r/wc 110?113h int_ctrl interrupt control 00000000h ro, r/w 000?003h gcap global capabilities 4007000h ro 100?103h dev_sts device status 00000000h ro 104?107h frame frame number 00000000h ro 10c?10fh int_sts interrupt status 00000000h ro, r/wc 110?113h int_ctrl interrupt control 00000000h ro, r/w 114?117h dev_ctrl device control 00000000h ro, r/w 200?207h 220?227h 240?247h 260?267h 280?287h 2a0?2a7h 2c0?2c7h 2e0?2e7h ep0ib ep0ob ep1ib ep1ob ep2ib ep2ob ep3ib ep3ob endpoint 0 in base endpoint 0 out base endpoint 1 in base endpoint 1 out base endpoint 2 in base endpoint 2 out base endpoint 3 in base endpoint 3 out base 00000000 00000000h ro, r/w 208?209h 228?229h 248?249h 268?269h 288?289h 2a8?2a9h 2c8?2c9h 2e8?2e9h ep0il ep0ol ep1il ep1ol ep2il ep2ol ep3il ep3ol endpoint 0 in length endpoint 0 out length endpoint 1 in length endpoint 1 out length endpoint 2 in length endpoint 2 out length endpoint 3 in length endpoint 3 out length 0000h r/w 20a?20bh 22a?22bh 24a?24bh 26a?26bh 28a?28bh 2aa?2abh 2ca?2cbh 2ea?2ebh ep0ipb ep0opb ep1ipb ep1opb ep2ipb ep2opb ep3ipb ep3opb endpoint 0 in position in buffer endpoint 0 out position in buffer endpoint 1 in position in buffer endpoint 1 out position in buffer endpoint 2 in position in buffer endpoint 2 out position in buffer endpoint 3 in position in buffer endpoint 3 out position in buffer 0000h ro, wc 20c?20dh 22c?22dh 24c?24dh 26c?26dh 28c?28dh 2ac?2adh 2cc?2cdh 2ec?2edh ep0idl ep0odl ep1idl ep1odl ep2idl ep2odl ep3idl ep3odl endpoint 0 in descriptor in list endpoint 0 out descriptor in list endpoint 1 in descriptor in list endpoint 1 out descriptor in list endpoint 2 in descriptor in list endpoint 2 out descriptor in list endpoint 3 in descriptor in list endpoint 3 out descriptor in list 0000h ro, wc
datasheet 283 usb client controller (d26:f0) 20e?20fh 22e?22fh 24e?24fh 26e?26fh 28e?28fh 2ae?2afh 2ce?2cfh 2ee?2efh ep0itq ep0otq ep1itq ep1otq ep2itq ep2otq ep3itq ep3otq endpoint 0 in transfer in queue endpoint 0 out transfer in queue endpoint 1 in transfer in queue endpoint 1 out transfer in queue endpoint 2 in transfer in queue endpoint 2 out transfer in queue endpoint 3 in transfer in queue endpoint 3 out transfer in queue 0000h ro, wc 210?211h 230?231h 250?251h 270?271h 290?291h 2b0?2b1h 2d0?2d1h 2f0?2f1h ep0imps ep0omps ep1imps ep1omps ep2imps ep2omps ep3imps ep3omps endpoint 0 in max packet size endpoint 0 out max packet size endpoint 1 in max packet size endpoint 1 out max packet size endpoint 2 in max packet size endpoint 2 out max packet size endpoint 3 in max packet size endpoint 3 out max packet size 0040h ro, r/w 212?213h 232?233h 252?253h 272?273h 292?293h 2b2?2b3h 2d2?2d3h 2f2?2f3h ep0is ep0os ep1is ep1os ep2is ep2os ep3is ep3os endpoint 0 in status endpoint 0 out status endpoint 1 in status endpoint 1 out status endpoint 2 in status endpoint 2 out status endpoint 3 in status endpoint 3 out status 0000h ro, r/wc 214?214h 234?234h 254?254h 274?274h 294?294h 2b4?2b4h 2d4?2d4h 2f4?2f4h ep0ic ep0oc ep1ic ep1oc ep2ic ep2oc ep3ic ep3oc endpoint 0 in configuration endpoint 0 out configuration endpoint 1 in configuration endpoint 1 out configuration endpoint 2 in configuration endpoint 2 out configuration endpoint 3 in configuration endpoint 3 out configuration 0000h ro, r/w 237h 277h 2b7h 2f7h ep0osps ep1osps ep2osps ep3osps endpoint 0 output setup package status endpoint 1output setup package status endpoint 2 output setup package status endpoint 3 output setup package status 00h ro, r/wc 238?23fh 278?27fh 2b8?2bfh 2f8?2ffh ep0osp ep1osp ep2osp ep3osp endpoint 0 output setup packet endpoint 1output setup packet endpoint 2 output setup packet endpoint 3 output setup packet 0r/w table 40. usb client i/o registers (sheet 2 of 2) mem_base +offset mnemonic register default type
usb client controller (d26:f0) 284 datasheet 14.4.1 gcap?global capabilities register address offset: 000h?003h attribute: ro default value: 40000003h size: 32 bits bit default and access description 31:28 4h ro endpoint cap: indicates the number of endpoints supported by this device. one ?in' and one 'out' pair is considered an endpoint, so the minimum device configuration would have a default value of '1', indicating that only the endpoint 0 in and endpoint 0 out are supported. (reset value may vary if other than four endpoint pairs are supported.) 27:5 0s ro reserved 4 0b ro interrupt on completion capable (iocc) 1 = the hardware has the capability of generating an interrupt based on the transfer or scatter gather dma mode buffer desc riptor ioc bit. 3 0 ro transfer mode capable (tm) 1 = the device supports transfer mode dma operation. 2 0 ro scatter gather mode capable (sgm) 1 = indicates the device supports scatter gather mode dma operation 1 1 ro linear mode capable (lm) 1 = indicates the de vice supports buffer mode dma operation. 0 1 ro control mode capable (cm) 1 = indicates the devi ce supports control mode dma operation
datasheet 285 usb client controller (d26:f0) 14.4.2 dev_sts?device status register address offset: 100h?103h attribute: ro default value: 00000000h size: 32 bits 14.4.3 frame?frame number register address offset: 104h?107h attribute: ro default value: 00000000h size: 32 bits bit default and access description 31:15 0000h ro reserved 14:8 00h ro address (addr): this field provides the address of the device on the bus. at initialization, this is zero, and will reset to zero if the device is disconnected from the bus or a bus reset event is detected on the link. this register will reflect the address assign ed to the device by the controller when the address has been assigned. this is read/write to facilitate testing - software should not writ e under normal operation 7:4 0h ro reserved 3 0 ro rate (r): the intel? sch assigns this bit after negotiating with a usb host. 0 = device is operating in full-speed (12 mbps) mode. 1 = device is operating in high-speed (480 mbps) mode. a second read maybe required after conn ected is read asse rted in order to read the correct rate value. 2 0 ro reserved 1 0 ro connected (c): 0 = the device is not electrically connected to a usb host or hub device. 1 = the hardware is electrically conne cted to a usb host or hub device based on d+/d- signaling and if has determined whether the connection is high sp eed or full speed. if the host resets the device, this bit is reset to a ?0? and it is set back to a ?1? only after the spee d mode is established. 0 0 ro suspend (s): 0 = a link resume is seen to take the device out of reset. 1 = the hardware has detected that more than 3 ms have elapsed since the last activity on the bus, indicating that the device should enter usb ?suspend? state. bit default and access description 31:12 00000h ro reserved 11:0 000h ro number (num): indicates the last 11b fram e number received in a sof packet on the bus
usb client controller (d26:f0) 286 datasheet 14.4.4 int_sts?interrupt status register address offset: 10ch?10fh attribute: ro, r/wc default value: 00000000h size: 32 bits bit default and access description 31:19 000h ro reserved 18 0 r/wc reset (r): a device reset signal on th e usb port has been detected. when a bus reset is received, the intel? sch must immediately stop any transmissions. endpoint fifos are flushed. all endpoint enable bits sh ould transition to a '0' at the detection of usb bus reset, but all other endpoint bits should not be affected. while the reset is being signaled on the usb bus, software may set the enable bit on endpoints so that they are ready when bus activity resumes. 17 0 r/wc connect (c): set by hardware when the device status connected bit (100h:1) transitions from 0-to-1 or 1-to-0. 16 0 r/wc suspend (s): set by hardware when the device status suspend bit (100h:0) transitions from 0-to-1 or 1-to-0. 15:8 000h ro reserved 7:0 00h ro endpoint status (epsts): these are status bits only; the actual interrupt(s) are cleared by writing a 1 to the appropriate bit(s) in the ep0_in_sts register. bit endpoint 7 ep3_out 6 ep3_in 5 ep2_out 4 ep2_in 3 ep1_out 2 ep1_in 1 ep0_out 0 ep0_in
datasheet 287 usb client controller (d26:f0) 14.4.5 int_ctrl?interr upt control register address offset: 110h?113h attribute: ro, r/w default value: 00000000h size: 32 bits bit default and access description 31:19 000h ro reserved 18 0 r/w reset interrupt enable (rien): when set, and int_sts.r is set, an interrupt is generated. 17 0 r/w connect interrupt enable(cien): when set and int_sts.c is set, an interrupt is generated. 16 0 r/w suspend interrupt enable(sien): when set and int_sts.s is set, an interrupt is generated. 15:8 000h r/w reserved 7:0 00h r/w endpoint interrupt enable (epinten): when one of the endpoint interrupt enable bits is set and th e corresponding interrupt status bit (int_sts.epsts) is set, an interrupt is generated. each bit maps to a particular endpoint as shown below: bit endpoint 7ep3_in 6ep3_out 5ep2_in 4ep2_out 3ep1_in 2ep1_out 1ep0_in 0ep0_out
usb client controller (d26:f0) 288 datasheet 14.4.6 dev_ctrl?device control register address offset: 114h?117h attribute: ro, r/w default value: 00000000h size: 32 bits bit default and access description 31 0 r/w enable (en): while cleared, any writes to an y bit(s) in any register other than this bit are ignored. they comple te, but will have no effect on any registers. hardware must not drive d+/d- to signal a connection to the host. when software sets this bit, hardwa re transitions to the running state. software must poll this bit and not perform any reads or writes to the register space until the bit is read as a '1'. if the bit is not read as a '1' within 5 ms, software may assume that there is a hardware fault. when software clears this bit, hardwa re transitions all registers to their reset values (except register "offset 104h: frame - frame number" which keeps the last frame number received ), and deasserts any interrupts, clears any fifos, and pe rforms a device reset. 30 0 r/w connection enable (ce): 0 = d+/d- must not be pull ed up to indicate to a host that a device is connected, and should a ppear as not connected. 1 = appropriate pull-ups are enabled to signal a connection to a host. when transitioning from '1' to '0', the de vice shall appear to the host to disconnect, as defined in section 7.1.7.3 of the usb 2.0 specification . 29:0 0 ro reserved 8 0 r/w testmode: when set to a 1, the usb client will respond with fast chirp's to speed test time. 7 0b r/w test_se0_nak_mode: when set to a '1', the usb client will be configured in high-speed mode and will respond with nak to all incoming in packets. 6:5 000b ro reserved 4 0 r/w signalresume (sr): when software writes a 1 to this bit, hardware will generate resume sign aling on the link if the link is in the suspend state. software is responsible for knowing whether the device has been enabled to generate the signaling by the host system, and for ensuri ng that the link has been in the suspend stat e for the 5 ms minimum, per usb 2.0 specification, section 7.1.7.7. hardware is responsible for asserting the resume signaling on the link for the requisite amount of time. when the resume signaling is completed, hardware will clear this bit to a '0'. while resume signaling is enabled, software writes to this bit will be ignored.
datasheet 289 usb client controller (d26:f0) 3:1 000b r/w charge enable (cge): software will program the maximum number of unit loads that the device may cons ume from the bus. software will determine this based on the device configuration selected by the host software. this value may be from 000b to 101b, representing 0 to 5 unit loads. since a unit load is defined as 100 ma, hardware may then proceed to draw up to the indicated amount of current. hardware may assume that 1 unit load (100 ma) of current will be available, and up to 500 ma may be avai lable if the client device is plugged into a host or powered hub. hardware may optionally use this software provided value to charge a battery or draw power off the link for other purposes, or it may ignore the value if it has no need for link power. if hardware does not implement this fu nctionality, it may be read-only '000b'. 0 0 r/w force full speed (ffs): if set, the intel? sch will not attempt to negotiate high-speed operation, and wi ll fall back to default full-speed operation. bit default and access description
usb client controller (d26:f0) 290 datasheet 14.5 device endpoint register map the following provides the device endpoint register map. 14.5.1 epnib?endpoint [0..3] input base address register address offset: ep0_in_base 200h?207h attribute: ro, r/w ep1_in_base 240h?247h ep2_in_base 280h?287h ep3_in_base 2c0h?2c7h default value: 0000000000000000h size: 64 bits 14.5.2 epnil?endpoint [0,1 ] input length register address offset: ep0il 208h?209h attribute: r/w ep1il 248h?249h ep2iil 288h?289h ep3il 2c8h?2c9h default value: 0000h size: 16 bits byte offset 7 6 5432107 address offset input base address 00h transfer in queue descriptor in li st position in buffer input length 08h reserved status configuration maxdata packet size 10h reserved 18h output base address 20h transfer in queue descriptor in li st position in buffer output length 28h setup packet status reserved status configuration maxdata packet size 30h setup packet 38h bit default and access description 63:0 000000000h r/w base address (ba): must be 64b aligned. this register may be implemented as a 32b register, with the upper 32b read only 00000000h. bit default and access description 15:0 0000h r/w length (len): if epnic.md is buffer, this fi eld indicates the length of the data buffer. if epnic.md is scattergather or transf er, this field indicates the number of entries in the descriptor list.
datasheet 291 usb client controller (d26:f0) 14.5.3 epnipb?endpoint [0..3] in put position in buffer register address offset: ep0ipb 20ah?20bh attribute: ro, w/c ep1ipb 24ah?24bh ep2ipb 28ah?28bh ep3ipb 2cah?2cbh default value: 0000h size:16 bits 14.5.4 epnidl?endpoint [0..3] input descriptor in list register address offset: ep0idl 20ch?20dh attribute: ro, w/c ep1idl 24ch?24dh ep2idl 28ch?28dh ep3idl 2cch?2cdh default value: 0000h size:16 bits 14.5.5 epnitq?endpoint [0..3] inpu t transfer in queue register address offset: ep0itq 20eh?20fh attribute: ro, w/c ep1itq 24eh?24fh ep2itq 28eh?28fh ep3itq 2ceh?2cfh default value: 0000h size:16 bits bit default and access description 15:0 0000h r/wc position (pos): byte offset of the last by te fetched by the dma engine within the current buffer. bit default and access description 15:0 0000h r/wc position (pos): if epnic.md is linear, this is field is ro and not used. if epnic.md is transfer or scatter gather, this field indicates the offset of the current descriptor in the descriptor list. bit default and access description 15:0 0000h r/wc position (pos): if epnic.md is linear this, this field is ro and not used. if epnic.md is transfer, this field indicate s the offset of the current transfer in the transfer queue.
usb client controller (d26:f0) 292 datasheet 14.5.6 epnimps?endpoint [0..3] input maximum packet size register address offset: ep0imps 210h?211h attribute: ro, r/w ep1imps 250h?251h ep2imps 290h?291h ep3imps 2d0h?2d1h default value: 0040h size: 16 bits 14.5.7 epnis?endpoint [0..3] input status register address offset: ep0is 212h?213h attribute: ro, r/wc ep1is 252h?253h ep2is 292h?293h ep3is 2d2h?2d3h default value: 0000h size:16 bits bit default and access description 15:11 00h ro reserved 10:0 040h r/w size (s): this field indicates the maximum number of data bytes that may be sent in each inbound data packet, up to 1024 bytes. software is responsible for making sure that the value programmed here does not break the usb protocol (suc h as setting to 1024b on a control endpoint). this defaults to 64 bytes, which is the default si ze of a control endpoint. bit default and access description 15 0 r/wc bad pid type detected (bp): an inappropriate pid type was seen; for instance, a setup pid to an endpoint configured as a bulk endpoint. 14 0 r/wc crc error (ce): a crc error on the packet from the usb host detected. 13 0 r/wc fifo error (fe): data over-run. the packet received may have been corrupted. 12 0 r/wc dma error (de): there was an error fetching descriptors, or writing buffer data. hardware may stall transa ctions targeted at this endpoint (rather than naking them) to indicate to the host that a serious problem as occurred. 11 0 r/wc transfer complete (tc): length bytes have been sent, or one queue descriptor is complete and ioc was set 10 0 ro reserved 9 0 r/wc interrupt on completion (ioc): if gc.iocc is set, when in scatter gather or transfer mode, indicates th at a dma buffer whic h has ioc set in the descriptor has been completely tran sferred. if gc.iocc is cleared, this bit is read-only 0. 8:0 00h ro reserved
datasheet 293 usb client controller (d26:f0) 14.5.8 epnic?endpoint [0..3] input configuration register address offset: ep0ic 214h?215h attribute: ro, r/w ep1ic 254h?255h ep2ic 294h?295h ep3ic 2d4h?2d5h default value: 0000h size:16 bits bit default and access description 15 0 r/w interrupt on bad pid type (bp): enables epnis.bpt to generate an interrupt when set. 14 0 r/w interrupt on crc error (ice): enables epnis.ce to generate an interrupt when set. 13 0 r/w interrupt on fifo error (ife): enables epnis.fe to generate an interrupt when set. 12 0 r/w interrupt on dma error (ide): enables epnis.de to generate an interrupt when set. 11 0 r/w interrupt on transfer complete (itc): enables epnis.tc to generate an interrupt when set. 10 0 ro reserved 9 0 rw interrupt on dma interrupt on completion (idioc): enables epnis.ioc to generate an interrupt when set. 8 0 ro reserved 7:6 00b r/w mode (md): indicates the way the address and length fields are interpreted, and the way the data is fetched. see section error! reference source not found. for a description of these modes. 00 = linear mode, only linear mode and control mode are supported by the intel? sch 01 = scatter gather mode 10 = transfer mode 11 = control mode 5:4 00b r/w type (typ): changes some endpoint behaviors based on the type of the endpoint. in particular, isochronou s endpoints do not send ack/nak packets, and do not perform error chec king. the transfer limits for control and interrupt are also smaller than the limits for isoch or bulk (but only software cares). 00 = control/message 01 = isochronous 10 = bulk 11 = interrupt when control/message, software should set md to linear mode so that the software can handle each arriving packet. endpoints 0_in and 0_out (the default control pipe) will always be used in control/message mode.
usb client controller (d26:f0) 294 datasheet 14.5.9 epnob?endpoint [0..3] ou tput base address register address offset: attribute: ro, r/w ep0ob 220h?227h ep1ob 260h?267h ep2ob 2a0h?2a7h ep3ob 2e0h?2e7h default value: 0000000000000000h size: 64 bits 3:2 00b ro reserved 1 0 r/w enable (en) 1 = hardware will send data from the data buffer (fetching from dma as needed) for as long as there is data remaining to be sent in the buffer. the size of each individual transf er is limited by the epnimps. if in_enable is set when the length regi ster is zero (indicating no bytes or no descriptors), a zero length packet will be sent on the next transfer. 0 = input from this endpoint is not enable d. if v is set, hardware will send a nak for any packet addressed to this endpoint. if v is cleared, hardware will stall any in transfer to indicate a problem with the endpoint. on a transition from 1-to-0 the fifo must be flushed so that the next data transmission is fe tched from memory. 0 0 r/w valid (v): this bit indicates whether this is a valid and configured endpoint on this device. clearing this bit causes an endpoint reset. during the reset: ? all register values associated with this endpoint must return to their default values. ? the data0/1 sequence toggling for this endpoint defaults back to data0 ? all interrupts and status bits associ ated with this endpoint are cleared. ? all dma fifos and state machines are cleared and reset, including any fifo errors ? intel? sch minimizes power usage to the extent possible bit default and access description bit default and access description 63:0 000000000h r/w base address (ba): must be 64b aligned. this register may be implemented as a 32b register, with the upper 32b read only 00000000h.
datasheet 295 usb client controller (d26:f0) 14.5.10 epnol?endpoint [0..3] output length register address offset: attribute: r/w ep0ol 228h?229h ep1ol 268h?269h ep2ol 2a8h?2a9h ep3ol 2e8h?2e9h default value: 0000h size: 16 bits 14.5.11 epnopb?endpoint [0..3] ou tput position in buffer register address offset: ep0opb 22ah?22bh attribute: ro, w/c ep1opb 26ah?24bh ep2opb 2aah?2abh ep3opb 2eah?2ebh default value: 0000h size:16 bits 14.5.12 epnodl?endpoint [0..3] output descriptor in list register address offset: ep0odl 22ch?20dh attribute: ro, w/c ep1odl 26ch?24dh ep2odl 2ach?28dh ep3odl 2ech?2cdh default value: 0000h size:16 bits bit default and access description 15:0 0000h r/w length (len): if epnic.md is buffer, this fi eld indicates the length of the data buffer. if epnic.md is scattergather or transf er, this field indicates the number of entries in the descriptor list. bit default and access description 15:0 0000h r/wc position (pos): byte offset of the last byte written to by the dma engine within the current buffer. bit default and access description 15:0 0000h r/wc position (pos): if epnic.md is linear, this field is ro and not used. if epnic.md is transfer or scatter gather, this field indicates the offset of the current descriptor in the descriptor list.
usb client controller (d26:f0) 296 datasheet 14.5.13 epnotq?endpoint [0..3] output transfer in queue register address offset: ep0otq 20eh?20fh attribute: ro, w/c ep1otq 24eh?24fh ep2otq 28eh?28fh ep3otq 2ceh?2cfh default value: 0000h size:16 bits 14.5.14 epnomps?endpoint [0..3] ou tput maximum packet size register address offset: ep0omps 230h?231h attribute: ro, r/w ep1omps 270h?271h ep2omps 2b0h?2b1h ep3omps 2f0h?2f1h default value: 0040h size: 16 bits bit default and access description 15:0 0000h r/wc position (pos): if epnic.md is linear this field is ro and not used. if epnic.md is transfer, this field indicate s the offset of the current transfer in the transfer queue. bit default and access description 15:11 00h ro reserved 10:0 040h r/w size (s): this field indicates the maximum number of data bytes than may be sent in each inbound data packet, up to 1024 bytes. software is responsible for making sure that the value programmed here does not break the usb protocol (suc h as setting to 1024b on a control endpoint). this defaults to 64 bytes, which is the default si ze of a control endpoint.
datasheet 297 usb client controller (d26:f0) 14.5.15 epnos?endpoint [0..3] output status register address offset: ep0os 232h?233h attribute: ro, r/wc ep1os 272h?273h ep2os 2b2h?2b3h ep3os 2f2h?2f3h default value: 0000h size:16 bits 14.5.16 epnoc?endpoint [0..3] ou tput configuration register address offset: ep0oc 234h?235h attribute: ro, r/w ep1oc 274h?275h ep2oc 2b4h?2b5h ep3oc 2f4h?2f5h default value: 0000h size:16 bits bit default and access description 15 0 r/wc bad pid type detected (bptd): an inappropriate pid type was seen; for instance, a setup pid to an endpoint configured as a bulk endpoint 14 0 r/wc crc error (ce): a crc error on the packet from the usb host detected. 13 0 r/wc fifo error (fe): data under-run. the packet received may have been corrupted. 12 0 r/wc dma error (de): there was an error fetching descriptors, or fetching buffer data. hardware may stall transa ctions targeted at this endpoint (rather than naking them) to indicate to the host that a serious problem as occurred. 11 0 r/wc transfer complete (tc): short packet detected, meaning less than epnomps bytes were sent in a data0/1 phase. this includes zero length packets. this will also be set if or one queue descriptor is complete and ioc was set. 10 0 ro ping nak sent (pns): set if hardware responds to a ping with a nak. software can use this bit as an indicati on that the buffer si ze is insufficient, and that the host is waiting to send a larger packet than can be accommodated. 9 0 r/wc interrupt on completion (ioc): if gc.iocc is set, when in scatter gather or transfer mode, indicates th at a dma buffer which has ioc set in the descriptor has been completely transf erred. if gc.iocc is cleared, this bit is read-only '0'. 8:0 00h ro reserved bit default and access description 15 0 r/w interrupt on bad pid type (ibpt): enables epnos.bpt to generate an interrupt when set. 14 0 r/w interrupt on crc error (ice): enables epnos.ce to generate an interrupt when set. 13 0 r/w interrupt on fifo error (ife): enables epnos.fe to generate an interrupt when set.
usb client controller (d26:f0) 298 datasheet 12 0 r/w interrupt on dma error (ide): enables epnos.de to generate an interrupt when set. 11 0 r/w interrupt on transfer complete (itc): enables epnos.tc to generate an interrupt when set. 10 0 ro interrupt on pingnaksent (ipns): enables epnos.pns to generate an interrupt when set. 9 0 rw interrupt on dma interrupt on completion (idioc): enables epnos.ioc to generate an interrupt when set. 8 0 ro reserved 7:6 00b r/w mode (md): indicates the way the addres s and length fields are interpreted, and the way the data is fetched. 00 = linear mode, only linear mode and control mode are supported by the intel? sch 01 = scatter gather mode 10 = transfer mode 11 = control mode 5:4 00b r/w type (typ): changes some endpoint behavior s based on the type of the endpoint. in particular, isochronou s endpoints do not send ack/nak packets, and do not perform error checking. the transfer limits for control and interrupt are also smaller than the limits for isoch or bulk (but only software cares). 00 = control/message 01 = isochronous 10 = bulk 11 = interrupt when control/message, software should set md to linear mode so that the software can handle each arriving packet. endpoints 0_in and 0_out (the default control pipe) will always be used in control/message mode. 3:2 00b ro reserved 1 0 r/w enable (en) 1 = hardware will receive data into the data buffer for as long as there is space in the buffer. 0 = output on this endpoint is not enabled. if v is set, hardware will send a nak for any packet addressed to th is endpoint. if v is cleared, hardware will stall any in transfer to indicate a problem with the endpoint. on a transition from 1-to-0, the dma fi fo must be flushed so that all of the data received is flushed to memo ry. on a transition from 0-to-1, the position in buffer register, and the description descriptor in list and transaction in queue registers, if impl emented, will be reset to zero to cause the dma to begin transferring th e next transaction at the beginning of the buffer. bit default and access description
datasheet 299 usb client controller (d26:f0) 14.5.17 epnosps?endpoint [0..3] output setup package status register address offset: ep0osps 237h attribute: ro, r/w ep1osps 277h ep2osps 2b7h ep3osps 2f7h default value: 00h size:8 bits 14.5.18 epnosp?endpoint [0..3] output setup packet register address offset: ep0osp 238h-23fh attribute: ro, ep1osp 278h-27fh ep2osp 2b8h-2bfh ep3osp 2f8h-2ffh default value: 0000000000000000h size: 64 bits 0 0 r/w valid (v): indicates whether this is a vali d and configured endpoint on this device. clearing th is bit causes an endpoint reset. during the reset: ? all register values associated with this endpoint must return to their default values. ? the data0/1 sequence toggling for this endpoint defaults back to data0 ? all interrupts and status bits associ ated with this endpoint are cleared. ? all dma fifos and state machines are cleared and reset, including any fifo errors ? intel? sch minimizes power usage to the extent possible bit default and access description bit default and access description 7:1 00h ro reserved 0 0 r/wc valid (v): indicates that a valid setu p packet is in epnosp. bit default and access description 63:0 0 ro received setup packet data
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datasheet 301 sdio/mmc (d30:f0, f1, f2) 15 sdio/mmc (d30:f0, f1, f2) 15.1 sdio functional description (d30:f0, f1, f2) the intel? sch contains three sdio/mmc ports. ? port 0 and port 1 are 4-bits wide. port 2 is 8-bits wide. the controller supports mmc 4.1 and sdio 1.1 specifications. ? mmc 4.1 transfer rates can be up to 48 mhz and bus widths of 1, 4, or 8 bits. ? sdio 1.1 supports transfer rates up to 24 mhz and bus widths of 1 or 4 bits. 15.1.1 protocol overview the sdio/mmc transfer protocol utilizes the following definitions: ? command: a command is a 6-byte token that starts an operation. the command set includes card initialization, card regi ster reads and writes, and data transfers. the mmc/sd/sdio controller sends the comma nd serially on the sd_cmd signal pin. ? response: a response is a token that is an answer to a command token. each command has either a specific response type or no response type. the format for a response varies according to the command sent and the card mode. response formats are detailed in the multimediacard system specification version 4.0 . ? data: data is transferred serially between the sdio/mmc controller and the card in 8-bit blocks and at rates up to 48 mb/s. the format for the data depends on the card mode. depending on the status of certain enable bits, a particular response type can be selected. ta b l e 4 1 summarizes these response type dependencies. once known, the response type will be tr ansmitted by occupying a certain bit field within the 48-bit or 136-bit response. ta b l e 4 2 summarizes the response register mapping. table 41. determining the response type response type select index check enable crc check enable response type 00 0 0 no response 01 0 1 r2 10 0 0 r3, r4 10 1 1 r1, r5, r6 11 1 1 r1b, r5b
sdio/mmc (d30:f0, f1, f2) 302 datasheet 15.1.2 integrated pull-up resistors the intel? sch sdio/mmc controller contains on-die pull-up resistors on each data bus pin. the value of these intern al resistors is nominally 75 k and meets the pull-up requirement for both sd/sdio 1.1 and mmc 4.1 specifications. table 42. response register mapping kind of response meaning of response length of response response mapping resp register mapping r1, r1b normal response card status 48 39:8 rep[31:0] r1b auto cmd12 response card status for autocmd12 48 39:8 rep[127:96] r2 cid, csd register response cid or csd register incl 136 127:1 rep[126:0] r3 ocr register ocr register 48 39:8 rep[31:0] r4 ocr register ocr register in i/o mode 48 39:8 rep[31:0] r5, r5b sdio response 48 39:8 rep[31:0] r6 published rca response new published rca[31:16] etc. 48 39:8 rep[31:0] figure 6. response token formats 0 0 0 0 1 1 crc crc context context ? cid or csd total length = 136 bits total length = 48 bits r1, r3, r4, r5 r2 transmitter bit: 0 = card response status bit: always 0 response content: mirrored command and status information (r1 response), ocr register (r3 response) or rca (r4 and r5), protected by a 7-bit crc checksum. end bit: always 1 end bit: always 1
datasheet 303 sdio/mmc (d30:f0, f1, f2) 15.2 pci configuration registers note: address locations that are not shown should be treated as reserved. 15.2.1 vid?vendor iden tification register address offset: 00h ? 01h attribute: ro default value: 8086h size: 16 bits table 43. sdio/mmc pci register address map offset mnemonic register name default type 00?01h vid vendor identification 8086h ro 02?03h did device identification see description. ro 04?05h pcicmd pci command 0000h r/w, ro 06?07h pcists pci status 0280h r/wc, ro 08h rid revision identification see description ro 09h?0bh cc class codes 080501h ro 0dh mlt master latency timer 00h ro 0eh headtyp header type 00h ro 10?13h mem_base base address register 00000000h r/w,r0 2ch ssid subsystem identifiers 0000h ro 34h cap_ptr capabilities pointer 00h ro 3ch int_ln interrupt line 00h r/w 3dh int_pn interrupt pin see description ro 40h slotinf slot information 02h ro 84h?87h bc buffer control 00000000h ro, r/w 90h?93h sdioid sdio identification 00000000h ro, r/w f4h-f7h capcntl capabilities control 0000000xh ro, r/w f8h-fbh manid manufacturers id 00000f86h ro fc?ffh fd function disable 00000000h ro, r/w bit default and access description 15:0 8086 ro vendor id (vid): this is a 16-bit value assigned to intel.
sdio/mmc (d30:f0, f1, f2) 304 datasheet 15.2.2 did?device iden tification register address offset: 02h ? 03h attribute: ro default value: see bit description size: 16 bits 15.2.3 pcicmd?pci command register address offset: 04h ? 05h attribute: r/w, ro default value: 0000h size: 16 bits bit default and access description 15:0 see description ro device id (did): this is a 16-bit value assigned to the sdio controller. 811ch sdio controller #1 (d30:f0) 811dh sdio controller #2 (d30:f1) 811eh sdio controller #3 (d30:f2) bit default and access description 15:3 0s ro reserved 2 0 r/w bus master enable (bme): allows the sdio controller to act as a bus master. 0 = disable bus mastering 1 = enable bus mastering 1 0 r/w memory space enable (mse) . allows access to the sdio controller memory space 0 = disable access to memory space 1 = enable access to memory space 0 0 ro reserved
datasheet 305 sdio/mmc (d30:f0, f1, f2) 15.2.4 pcists?pci status register address offset: 06h ? 07h attribute: ro default value: 0000h size: 16 bits 15.2.5 cc?class codes register address offset: 08h?0bh attribute: ro default value: 08050100h size: 32 bits bit default and access description 15:0 0000h ro reserved bit default and access description 31:24 02h ro base class code (bcc) 02h = indicates that this devi ce is a generic peripheral. note: network device mode is not supported. 23:16 00h ro sub class code (scc) 00 = this field indicates that this device is an sdio host controller note: network device mode is not supported. 15:8 01h ro programming interface (pi) 01h = indicates the dma is supported with this controller note: network device mode is not supported. 7:0 00h ro revision id (rid): matches the value of the rid register in the lpc bridge.
sdio/mmc (d30:f0, f1, f2) 306 datasheet 15.2.6 headtyp?header type register address offset: 0eh attribute: ro default value: see description size: 8 bits 15.2.7 mem_base?base address register address offset: 10h ? 13h attribute:r/w, ro default value: 00000000h size:32 bits 15.2.8 ss?subsystem identifier register offset: 2ch attribute: ro default value: see bit description size: 8 bits bit default and access description 7 1 or 0 ro multi-function device (mfd) 0 = single function devi ce (functions 1 and 2) 1 = multi function device (function 0) 6:0 00h ro configuration layout: hardwired to 00h, which indicates the standard pci configuration layout. bit default and access description 31:8 000000h r/w memory base address: provides the 256 byte t memory space for slot 1's address space. 7:1 00h ro reserved . 0 0 ro space indicator: this bit reads 0, indicating that the bar is memory mapped. bit default and access description 7:0 description ro revision id (rid): matches the value of the rid register in the lpc bridge. refer to the intel ? system controller hub (intel? sch) specification update for the rid for each stepping.
datasheet 307 sdio/mmc (d30:f0, f1, f2) 15.2.9 int_ln?interrupt line register address offset: 3ch attribute: r/w default value: 00h size: 8 bits 15.2.10 int_pn?interrupt pin register address offset: 3dh attribute: ro default value: see description size: 8 bits 15.2.11 slotinf?slot information register address offset: 40h attribute: ro default value: 02h size: 8 bits bit default and access description 7:0 ro interrupt line (int_ln): this data is not used by the intel? sch. it is to communicate to software the interr upt line that the interrupt pin is connected to. bit default and access description 7:0 ro interrupt line (int_ln): this value tells the software which interrupt pin each sdio/mmc host controller uses. the upper 4 bits are hardwired to 0000b; the lower 4 bits are determine by the interrupt pin default values that are programmed in the memo ry-mapped configuration space as follows: sdio #1 ? d30ip.sd0ip (chipset config registers:offset 3104:bits 3:0) sdio #2 ? d30ip.sd1ip (chipset config registers:offset 3104:bits 7:4) sdio #3 ? d30ip.sd2ip (chipset config registers:offset 3104:bits 11:8) note: this does not determine the mapping to the pirq pins. bit default and access description 7 0 ro reserved 6:4 000b ro number of slots (ns): 000b indicates 1 slot supported on this controller. 3 0 ro reserved 2:0 010b ro first base address regi ster number (fbar): indicates the offset containing the mem_base (10h).
sdio/mmc (d30:f0, f1, f2) 308 datasheet 15.2.12 bc?buffer control register address offset: 84h?87h attribute: ro, r/w default value: 00000000h size: 32 bits bios/firmware must correctly program the buffe r strength bits based on the length of signal traces used in the design. bit default and access description 31:6 00000h ro reserved 5:4 00 core clock delay (ccd): connects to clock buffer. the length value to program is: 00 = 0 to 4 inches 01 = 4 to 5 inches 10 = reserved 11 = reserved 3:2 00 data buffer output delay (dbod): connects to all data buffers. the length value to program is: 00 = 0 to 4 inches 01 = 4 to 5 inches 10 = reserved 11 = reserved 1:0 00 data buffer input delay (dbid): connects to all data buffers. the length value to program is: 00 = 0 to 4 inches 01 = 4 to 5 inches 10 = reserved 11 = reserved
datasheet 309 sdio/mmc (d30:f0, f1, f2) 15.2.13 sdioid?sdio iden tification register address offset: 90h?93h attribute: ro, r/w default value: 00000000h size: 32 bits 15.2.14 capcntl?sdio capa bility control register address offset: f4h?f7h attribute: ro, r/w default value: 0000000xh size: 32 bits note: bit 2:0 notes: the default value of these register bits matches the default value of the bits in register offset 40h. writing these bits to a different value allows validation to test the hardware in other configurations without changing the register bits in offset 40h. bit default and access description 31:1 0 ro reserved 0 0 r/w host controller id as network device (hcnd): 1 = the base class, bus class, and programming interface for this sdio controller changes to a network controller. | note: network device mode the is not supported. bit default and access description 31:8 000h ro reserved 2 1b rw bit 2 control: bit2 control bit for register offset 40h bit 21; 1 see des rw bit 1 control: bit1 control bit for register o ffset 40h bit 17. this bit will default to a 1 for sdio slot 0, and 0 for sdio slot 1 and 2 0 0b rw bit 0 control: bit0 control bit for register offset 40h bit 16
sdio/mmc (d30:f0, f1, f2) 310 datasheet 15.2.15 manid?manufacturer id address offset: f8h?fbh attribute: ro default value: 00000f86h size: 32 bits 15.2.16 fd?function disable register address offset: fch attribute: ro, r/w default value: 00000000h size: 32 bits bit default and access description 31:24 00h ro reserved 23:16 xh ro stepping idstate efer to the spec update 15:8 0fh ro manufacturer: 0fh = intel 7:0 86h ro process/dot: 86h = process 861.6 bit default and access description 31:1 0 ro reserved 0 0 r/w disable (d): 0 = this function is enabled 1 = this function is disabled and configuration space is disabled
datasheet 311 sdio/mmc (d30:f0, f1, f2) 15.3 sdio/mmc memory-mapped registers for the following memory mapped registers, the base address is that pointed to by the contents of the mem_base (offset 10h) register described above. here is a list of the sdio transfer restrictions: ? the intel? sch does not support zero block size transfer ? for dma mode, the intel? sch does not support the following mode: ? offset 0ch, bit 5 = 1, multiple transfer ? offset 0ch, bit 1 = 1, block count enabled ? offset 06h = 0000h, block count = 0 (aka stop multiple transfer) ? for pio mode, the intel? sch does not support the following modes: ? (stop multiple transfer) offset 0ch, bit 5 = 1, multiple transfer offset 0ch, bit 1 = 1, block count enabled offset 06h = 0000h, block count = 0 ? infinite transfer offset 0ch, bit 5 = 1, multiple transfer offset 0ch, bit 1 = 0, block count disabled offset 06h = 0000h, block count = 0 or 1 table 44. sdio/mmc memory-mapped regi ster address map (sheet 1 of 2) mem_base + offset mnemonic register name default type 00h?03h dmaadr dma address 00000000h r/w 04h?05h blksz block size 0000h ro, r/w 06h?07h blkcnt block count 0000h r/w 08h?0bh cmdarg command argument 00000000h r/w 0ch?0dh xfrmode transfer mode 0000h ro, r/w 0eh?0fh sdcmd sdio command 0000h ro, r/w 10h?1fh resp response 0s r/w 20h?23h bufdata buffer data port 00000000h r/w 24h?27h pstate present state 00000000h ro, r/w, roc 28h hostctl host control 00h ro, r/w 29h pwrctl power control 00h ro, r/w 2ah blkgapctl block gap control 00h ro, r/w 2bh wakectl wakeup control 00h ro, r/w 2ch?2dh clkctl clock control 0000h ro, r/w 2eh toctl timeout control 00h ro, r/w 2fh swrst software reset 00h ro, r/w, r/wc 30h?31h nintsts normal interrupt status 0000h ro, r/wc 32h?33h erintsts error interrupt status 0000h ro, r/wc 34h?35h ninten normal interrupt enable 0000h ro, r/w
sdio/mmc (d30:f0, f1, f2) 312 datasheet 15.3.1 dmaadr?dma address register i/o offset: base + (00h ? 03h) attribute: r/w default value: 00000000h size: 32 bits 36h?37h erinten error interrupt enable 0000h ro, r/wc 38h?39h nintsigen normal interrupt signal enable 0000h ro, r/w 3ah?3bh erintsigen error interrupt signal enable 0000h ro, r/wc 3ch?3dh ac12errsts auto cmd12 error status 0000h ro 40h?43h cap capabilities 00000000h ro 48h?4bh mccap maximum current capabilities 00000000h ro fch?fdh sltintsts slot interrupt status 0000h ro feh?ffh ctrlrver host controller version 0000h ro table 44. sdio/mmc memory-mapped regi ster address map (sheet 2 of 2) mem_base + offset mnemonic register name default type bit default and access description 31:0 0 r/w system address (sa): this field contains the system memory address for a dma transfer. during data transfers, reads of these bits will return invalid data and writes will be ignored. when the intel? sch stops a dma transfer, this points to the system address of the next data position. the dma transfer stops at every boundary specified by bs.bb. intel? sch generates dma interrupt to request so ftware to update this register. software must then write the address of the next data position to this register. when the upper byte of this register (offset 003h) is written, the intel? sch restarts the transfer. when restarting a dma transfer th rough the resume command or by setting the continue request bit in th e block gap control register, the host controller shall start at the next co ntiguous address stored here in the system address register. if the dma transfer crosses dma buffer boundary, the dma system address must be chosen such that it is any multiple of the programmed blk_size below the dma buffer boundary. this equates to: dma sys addr = dma buffer boundary ? (n * blk_size) where n is any number that will equate the dma sys addr below the dma buffer boundary.
datasheet 313 sdio/mmc (d30:f0, f1, f2) 15.3.2 blksz?block size register i/o offset: base + (04h-05h) attribute: ro, r/w default value: 0000h size: 16 bits bit default and access description 15 0 ro reserved 14:12 000b r/w buffer boundary (bb): these bits specify the size of contiguous buffer in the system memory. the dma transfer shall wait at the boundary specified by this field and intel? sch gene rates the dma interrupt to request software to update dsa. if 000b (buffer size = 4 kb), the lower 12 address bits points to data in the contiguous buffer while the upper 20 a ddress bits point to the location of the buffer in system me mory. the dma transfer stops when the host controller detects ?c arry out? of the address from bit 11 to 12. the address ?carry out bit? changes depending on the size of the buffer. this function is active when the dma enable in the tr ansfer mode register is set to 1. 11:0 000h r/w transfer block size (tbs): specifies the size of each block, in bytes, for data transfers for cmd17, cmd18, cmd24, cmd25, and cmd53. during data transfers, reads of these bits will return invalid data and writes will be ignored. bits buffer size carry out bit 004 4 kb a11 001 8 kb a12 --- --- --- 110 256 kb a17 111 512 kb a18 bits size 0000h no data transfer (not supported) 0001h 1 byte 0002h 2 bytes 0003h 3 bytes --- --- 01ffh 511 bytes 0200h 512 bytes 0400h 1024 bytes 0800h 2048 bytes (0fffh 4095 bytes
sdio/mmc (d30:f0, f1, f2) 314 datasheet 15.3.3 blkcnt?block count register i/o offset: base + (06h-07h) attribute: r/w default value: 0000h size: 16 bits 15.3.4 cmdarg?command argument register i/o offset: base + (08h-0bh) attribute: r/w default value: 00000000h size: 32 bits bit default and access description 15:0 0000h r/w count (c): contains the number of blocks to be transferred. during a transfer operation, read operations to this register will return invalid data and writes will be ignored. when a suspend command is received by the controller, this register will refl ect the number of blocks yet to be transferred. bit default and access description 31:0 00000000h r/w argument (a): contains the command to be transmitted. maps to bits 39:8 of the command format in th e sd/mmc card specifications.
datasheet 315 sdio/mmc (d30:f0, f1, f2) 15.3.5 xfrmode?trans fer mode register i/o offset: base + (0ch-0dh) attribute: r/o, r/w default value: 0000h size: 16 bits bit default and access description 15:7 00h ro reserved 6 0 rw cmc comp ata: command completion signal enable for ce-ata device 0 = device will not send command completion signal 1 = device will send command completion signal 5 0 r/w multiple block select (mbs): enables multiple block data transfers on the data bus. 0 = single block transfers only 1 = multi-block transfers allowed 4 0 r/w data direction (datdir): defines the directio n of data transfers. 0 = write (host to client) 1 = read (client to host) 3 0 ro reserved 2 0 r/w auto cmd12 enable (ac12en): multiple block transfers for memory require cmd12 be issued to stop the transaction. 0 = do not automatically issue the cmd12 command after the last block transfer. 1 = automatically issue the cmd12 comm and when the last block transfer is completed. 1 0 r/w block count enable (bce): this bit is only re levant for multi-block transfers. 0 = disables the block counter 1 = enables the block counter 0 0 r/w dma enable (dmaen): dma transfers may only be enabled if the dma support bit in the capabili ties register is set. a dma transfer begins with software writes to the upper bu te of the dma address register 0 = disable dma transfers 1 = enable dma transfers
sdio/mmc (d30:f0, f1, f2) 316 datasheet 15.3.6 xfrmode?trans fer mode register i/o offset: base + (0ch-0dh) attribute: r/o, r/w default value: 0000h size: 16 bits bit default and access description 15:6 00h ro reserved 5 0 r/w multiple block select (mbs): enables multiple block data transfers on the data bus. 0 = single block transfers only 1 = multi-block transfers allowed 4 0 r/w data direction (datdir): defines the direction of data transfers. 0 = write (host to client) 1 = read (client to host) 3 0 ro reserved 2 0 r/w auto cmd12 enable (ac12en): multiple block transfers for memory require cmd12 be issued to stop the transaction. 0 = do not automatically issue the cmd12 command after the last block transfer. 1 = automatically issue the cmd12 comma nd when the last block transfer is completed. 1 0 r/w block count enable (bce): this bit is only re levant for multi-block transfers. 0 = disables the block counter 1 = enables the block counter 0 0 r/w dma enable (dmaen): dma transfers may only be enabled if the dma support bit in the capabili ties register is set. a dma transfer begins with software writes to the upper bute of th e dma address register 0 = disable dma transfers 1 = enable dma transfers
datasheet 317 sdio/mmc (d30:f0, f1, f2) 15.3.7 cmd?command register i/o offset: base + (0eh-0fh) attribute: ro, r/w default value: 0000h size: 16 bits bit default and access description 15:14 00b ro reserved 13:8 00h r/w command index (cmdidx): contain the command number (ex: cmd16, acmd51, etc.) that is spec ified in bits 45: 40 of the command- format in the sd memory card physical layer and sdio card specifications. 7:6 00b r/w command type (ct): 00b = normal 01b = suspend (cmd52 for writing ?bus suspend? in cccr) 10b = resume 11b = abort 5 0 r/w data present select (dps): this bit is set to indicate that data is present and shall be transferred using sd_dat . it is cleared for the following: ? commands using only cmd line (ex. cmd52). ? commands with no data transfer but using busy signal on dat[0] (ex. cmd38) ? resume command 4 0 r/w command index check enable (cice): this bit determines if the command and response index fi elds should be compared. 0 = do not check the index field 1 = compare the index fields of the command and response. if the indices do not match a command index error is reported. 3 0 r/w command crc check enable (ccce): checks for errors in the crc field in the response. 0 = disable crc field checking 1 = check the crc field for errors. if an error is detected, a command crc error is reported. 2 0 r/w reserved 1:0 00b r/w response length select (rsplensel) 00b = no response 01b = response length 136 10b = response length 48 11b = response length 48 (check busy after response)
sdio/mmc (d30:f0, f1, f2) 318 datasheet 15.3.8 resp?response register i/o offset: base + (10h-1fh) attribute: r/w default value: all zeros size: 128 bits the response register holds the data cont ent that was transmitted by the sdio/mmc device to the host controller as part of its response to a command. only specific portions of this 128-bit register are used at any one time depending on the type of response send from the client device. 15.3.9 bufdata?buffer data register i/o offset: base + (20h-23h) attribute: r/w default value: 00000000h size: 32 bits 15.3.10 pstate?present state register i/o offset: base + (24h ? 27h) attribute: ro, r/w, roc default value: 00000000h size: 32 bits the pstate register indicates what sd_dat[7:0] signal(s) are in use. bit default and access description 127:0 0s r/w command response (resp): contains the content portion of a card?s response to commands issued from the sdio/mmc host controller. bit default and access description 31:0 00000000h r/w buffer data (bd): the intel? sch buffer data is accessed by this register. bit default and access description 31:25 00h ro reserved 24 0 ro command level (cmdlvl): this bit reflects th e state of the sdn_cmd signal. 23:20 0h ro sd_dat[3:0] signal level (d30lvl): the levels on these 4 bits mirror the levels of the corresponding sd_dat bus signals: bit signal 23 sd_dat[3] 22 sd_dat[2] 21 sd_dat[1] 20 sd_dat[0] 19 0 ro write protect (wp): this bit reflects the status of the sdn_wp signal used for memory cards. 0 = write enabled (sdn_wp = 0) 1 = write protected (sdn_wp = 1)
datasheet 319 sdio/mmc (d30:f0, f1, f2) 18 0 ro card detect (cd): this bit reflects the inverted status of the sd_cd# signal. 0 = card not detected (sd_ cd# = 1) 1 = card detected (sd_cd# = 0) 17 0 ro card state stable (css): this bit reflects the stability of the sd_cd# signal and can be used for testing. this state of this bit is not altered by the software reset register. 0 = sd_cd# is not stable 1 = sd_cd# is stable (either high or low) 16 0 ro card inserted (ci): this bit indicates if a card has been inserted. a 0-to- 1 transition of this bit triggers a card insertion interrupt. conversely, a 1-to-0 transition will trigger a card removal interrupt. this state of this bit is not altered by the software reset register. if a card is removed while its power is on and its clock is oscillating, the host controller shall tu rn off the bus by clearing pwrctl.buspwr and clkctl.clken. the host controller should then clear swrst.srfa. the card detect is active rega rdless of the sd bus power. 0 = reset/debouncing/no card 1 = card inserted 15:12 0h ro reserved 11 0 roc buffer read enable (bre): the status of this bit should be used for non- dma reads. a 1-to-0 transition of this bit occurs when all the block data is read from the buffer. a 0-to-1 transition occurs when all the block data is ready in the buffer and generate s a buffer read ready interrupt. 0 = read disable. all blcok data has been read. 1 = read enable. valid data exists in the host?s buffer. 10 0 roc buffer write enable (bufwren): the status of this bit should be used for non-dma writes. this read-only flag indicates if space is available for write data. a 1-to-0 transition indicates all the block data has been written to the buffer. a 0-to-1 transition occurs when the top of block data can be written to the buffer and generate s the buffer write ready interrupt. 0 = write disable 1 = write enable. data may be written to the data buffer. 9 0 roc read transfer active (rta) 0 = no data to transfer. the last data block has been received, or when all valid data blocks have been transf erred to the system and no current block transfers are being sent as a result of the stop at block gap request set to 1. 1 = transferring data. the end bit of a read command has been received, or the continue request bit of the blkgapctl register was set. a 1-to-0 transition will cause a tr ansfer complete interrupt to be generated. bit default and access description
sdio/mmc (d30:f0, f1, f2) 320 datasheet 8 0 roc write transfer active (wta) 0 = no valid write data exists in the host controller. this bit is cleared in either of the following cases: ? after getting the crc status of th e last data block as specified by the transfer count ? after getting a crc status of an y block where data transmission was stopped by a stop at block gap 1 = transferring data this bit is set in either of the following cases: ? after the end bit of the write command. ? when writing a 1 to continue request in the block gap control register to restart a write transfer. 7:3 0h reserved 2 0 roc dat line active (dla): indicates if one of the sd_dat lines is currently in use. 0 = sd_datx is inactive 1 = sd_datx is active 1 0 roc dat-command inhibit (dci): this bit is set if either the dla or rta bits are set to 1. clearing this bit sets nis.tc. 0 = a command using the sd_dat bus cannot be issued. 1 = a command using the sd_dat bus can be issued. 0 0 roc command inhibit (ci) . 0 = indicates sd_cmd is not in use and that the host controller may issue a command using the sd_cmd signal. 1 = the controller cannot issue a commend because of a command conflict error or because of a command not issued by autocmd12 error. bit default and access description
datasheet 321 sdio/mmc (d30:f0, f1, f2) 15.3.11 hostctl?host control register i/o offset: base + 28h attribute: ro, r/w default value: 00h size: 8 bits 15.3.12 pwrctl?power control register i/o offset: base + (29h) attribute: ro, r/w default value: 00h size: 8 bits bit default and access description 7:4 0000b ro reserved 3 0 r/w 8-bit mmc support (mmc8): if set, (and bit 1 = 0) the intel? sch supports 8-bit mmc. when cleared the intel? sch does not support this feature 2 0 r/w high speed enabled (hsen): high-speed mode will cause to the controller to drive sd_cmd and sd _dat[7:0] at the rising edge of sd_clk. default mode is to output at the falling edge of sd_clk for normal speed operation. 0 = normal speed mode 1 = high speed mode 1 0 r/w data transfer width (dtw): if sd8m is 0, this bit will determine the final width of the data transfers on sd_dat[7:0]. 0 = 1-bit mode 1 = 4-bit mode 0 0 r/w led control (ledctl): this bit turns the external led on or off. 0 = led is off 1 = led is on bit default and access description 7:4 0h ro reserved 3:1 000b r/w sd bus voltage select (vsel): only 111b (3.3 v) may be written to these bits. other valu es will be ignored. 0 0 r/w sd bus power en able (pwren) 0 = the sd bus is not powered 1 = the sd bus is powered
sdio/mmc (d30:f0, f1, f2) 322 datasheet 15.3.13 blkgapctl?block gap control register i/o offset: base + (2ah) attribute: ro, r/w default value: 00 size: 8 bits bit default and access description 7:4 0h ro reserved 3 0 r/w interrupt at block gap: this bit is valid only in 4-bit mode of the sdio card and selects a sample point in the interrupt cycle. setting to 1 enables interrupt detection at the block gap for a multiple block transfer. setting to 0 disables interrupt detection during a multiple block transfer. if the sd card cannot signal an in terrupt during a multiple block transfer, this bit should be set to 0. when the host driv er detects an sd ca rd insertion, it shall set this bit according to the cccr of the sdio card. 2 0 r/w read wait control (rwc): if the card supports read wait, set this bit to enable use of the read wait protocol to stop read data using the dat[2] line. otherwise the intel? sch stops sd clock to hold read data. when software detects an card insertion, if the card does not support read wait, this bit shall never be set. if this bi t is cleared, suspend/resume cannot be supported. 1 0 r/w continue request (cr): this bit is used to re start a transaction which was stopped using the sbc bit. to canc el stop at the block gap, clear sbc to 0 and set this bit to restart the transfer. intel? sch automatically clears this bit in either of the following cases: ? read transaction: ps.dla changes from 0 to 1 as a read transaction restarts. ? write transaction: ps.wta changes from 0 to 1 as the write transaction restarts. it is not necessary for soft ware to clear this bit. if sr is set, any write to this bit is ignored. 0 0 r/w stop request (sr): this is used to stop ex ecuting a transaction at the next block gap for both dma and non- dma transfers. until the transfer complete is set to 1, indicating a tr ansfer completion software shall leave this bit set to 1. clearing both this bit and cr shall not cause the transaction to restart. rwc is used to stop the read transaction at the block gap. intel? sch shall honor this bi t for write transfers, but for read transfers it requires that the card su pport read wait. software shall not set this bit during read transfers unless the card supports read wait and has set rwc. in the case of write transfers in which software writes data to the buffer data port register, software shal l set this bit after all block data is written. if set, software shall not write data to buffer data port register. this bit affects ps.rta, ps.wta, ps.d la and command inhibit (dat) in the present state register.
datasheet 323 sdio/mmc (d30:f0, f1, f2) 15.3.14 wakectl?wake control register i/o offset: base + 2bh attribute: ro, r/w default value: 00h size: 8 bits bit default and access description 7:3 00h ro reserved 2 0 r/w card removal enable (crme): fn_wus (wake up support) in cis does not effect this bit. 0 = wakeup events will not be triggered due to a card removal interrupt. 1 = enables wakeup event when a ca rd removed interrupt is detected (nintsts.cr). 1 0 r/w card insertion enable (cine): fn_wus (wake up support) in cis does not effect this bit. 0 = wakeup events will not be triggere d due to a card insertion interrupt. 1 = enables wakeup event when a card insertion interru pt is detected (nintsts.cin). 0 0 r/w card interrupt enable (cie): when set, enables wakeup event by card interrupt assertion in the normal interrupt status re gister. this bit can be set to 1 if fn_wus (wake up support) in cis is set to 1. 0 = wakeup events will not be tr iggered due to a card interrupt. 1 = enables wakeup event with a card interrupt is detected (nintsts.ci).
sdio/mmc (d30:f0, f1, f2) 324 datasheet 15.3.15 clkctl?clock control register i/o offset: base + (2ch-2dh) attribute: ro, r/w default value: 00h size: 16 bits bit default and access description 15:8 00h r/w frequency divisor (fd): this register is used to select the final frequency of sdclk pin. the value of th ese bits determines a divisor to be applied to the base clock frequency (f ound in the capabi lities register). only the following settings are allowed: 80h divide by 256 40h divide by 128 20h divide by 64 10h divide by 32 08h divide by 16 04h divide by 8 02h divide by 4 01h divide by 2 00h base clock (10 mhz ? 63 mhz) when setting multiple bits, the most si gnificant bit is used as the divisor. the two default divider valu es can be calculated by the frequency that is defined by the base clock frequenc y for sd clock in the capabilities register. at the initialization of the controller, these bits will be set according to the capabilities register. 7:3 0h ro reserved 2 0 r/w clock enable (clken) 0 = sd_clk is disabled. the controller clea rs this bit if no card is detected. 1 = sd_clk is enabled. the fd bits may not be changed. 1 0 ro internal clock stable (ics): this bit is set to 1 wh en sd clock is stable after writing to internal clock enable in this regi ster to 1. the sd host driver shall wait to set sd clock enable until this bit is set to 1. this is useful when using pll for a clock os cillator that requ ires setup time. 0 0 r/w internal clock enable (ice): this bit is set to 0 wh en the host driver is not using the host controller or the host controller awaits a wakeup interrupt. the host controller should st op its internal clock to go very low power state. still, regist ers shall be able to be read and written. clock starts to oscillate when this bit is set to 1. when clock oscillation is stable, the host controller shall set in this register to 1. this bit shall not effect card detection.
datasheet 325 sdio/mmc (d30:f0, f1, f2) 15.3.16 toctl?timeout control register i/o offset: base + (2eh) attribute: ro, r/w default value: 00h size: 8 bits bit default and access description 7:4 0h ro reserved 3:0 0h r/w data timeout counter value (dtcv): this value determines the interval by which sd_dat line timeou ts are detected. refer to the data timeout error in the error interrupt status register fo r information on factors that dictate timeout generati on. timeout clock fre quency will be generated by dividing the base cloc k tmclk value by this value. when setting this register, prevent inadvertent timeout events by clearing the data timeout error status enable (i n the error interrupt status enable register). at the initialization of the controller, these bits will be set according to the capabilities register. bit code description 1111b reserved 1110b tmclk 2 27 --- --- 0001b tmclk 2 14 0000b tmclk 2 13
sdio/mmc (d30:f0, f1, f2) 326 datasheet 15.3.17 swrst?software reset register i/o offset: base + (2f) attribute: ro, r/w default value: 00h size: 8 bits bit default and access description 7:3 0h ro reserved 2 0 rwac software reset for sd_dat: the following registers and bits are cleared by this bit: 1 0 r/w reset cmd (rc) . when set, the following bi ts are cleared: pstate.ci, nintsts.cc 0 0 r/w reset all (all) . this bit resets the entire ho st controller except the card detection circuit. which includes th e dma system address and buffer data port. 1 = the sd controller shall reset itself. register bits buffer data (bufdata) all present state (pstate) buffer read enable buffer write enable read transfer active write transfer active dat line active command inhibit (dat) block gap control (blkgapctl) continue request stop at block gap request normal interrupt status (nintsts) buffer read ready buffer write ready dma interrupt block gap event
datasheet 327 sdio/mmc (d30:f0, f1, f2) 15.3.18 nintsts?normal interrupt status register i/o offset: base + (30h-31h) attribute: ro, r/wc default value: 0000h size: 16 bits bit default and access description 15 0 ro error interrupt (ei): this bit allows the software to efficiently test for an error by checking this bit before sca nning all bits in the error interrupt status (erintsts) register. 0 = no bits in erintsts are set 0 = at least one bit in erintsts has been set 14:9 00h ro reserved 8 0 ro card interrupt (ci): this bit is cleared by rese tting the sd card interrupt factor. in 1-bit mode, the host contro ller shall detect the card interrupt without sd clock to support wakeup. in 4-bit mode, the card interrupt signal is sampled during the interrupt cycle, so there are some sample delays between the interrupt signal from the sd ca rd and the interrupt to the host system. it is necessary to define how to handle this delay. when this status has been set and the host driver needs to start this interrupt service, card interrupt stat us enable in the normal interrupt status enable register shal l be set to 0 in order to clear the card interrupt statuses latched in the ho st controller and to st op driving the interrupt signal to the host system. after completion of the card interrupt service (it should reset interrupt factors in the sd card and the interrupt signal may not be asserted), set card interrupt status enable to 1 and start sampling the interrupt signal again. 7 0 r/wc card removed (crm): this bit is cleared by writing a 1 to it. 0 = card state stable or debouncing. 1 = card removed. set when pstate.ci is cleared. when software clears this bit (by wr iting a 1 to it), the status of the pstate.ci bit should be confirmed to ensure no card de tect interrupts are missed. 6 0 r/wc card insertion (cin): this bit is cleared by writing a 1 to it. 0 = card state stable or debouncing 1 = card inserted. set when pstate.ci is set. when software clears this bit (by wr iting a 1 to it), the status of the pstate.ci bit should be confirmed to ensure no card de tect interrupts are missed. 5 0 r/wc buffer read ready (brr): set when pstate.bre is set. 4 0 r/wc buffer write ready (bwr): set when pstate.bwe is set. 3 0 r/wc dma interrupt: this status is set if the host controller detects the host dma buffer boundary during transfer . refer to the host dma buffer boundary in the block size register . other dma interrupt factors may be added in the future. this interrupt shall not be gene rated after the transfer complete.
sdio/mmc (d30:f0, f1, f2) 328 datasheet 2 0 r/wc block gap event (bge): operation of this bit is enabled if blkgapctl.sr is set. ? read: this bit is set at the falling edge of the dat line active status, when the transaction is stopped at sd bus timing. the read wait must be supported in order to use this function. ? write: set at the fallin g edge of write transfer active status (after getting crc status at sd bus timing. 1 0 r/wc transfer complete (tc): this bit is set when a read/write transfer is completed. ? read: this bit is set at the falling edge of read transfer active status. there are two cases in which this in terrupt is generate d. the first is when a data transfer is completed as specified by data length (after the last data has been read to the host system). the second is when data has stopped at the block gap and completed the data transfer by setting the stop at block gap reques t in the block gap control register (after valid data has been read to the host system). refer to section 3.10.3 for more details on the sequence of events. ? write: this bit is set at the falling edge of the dat line active status. there are two cases in which this in terrupt is generate d. the first is when the last data is written to the sd card as specified by data length and the busy signal released. the second is when data transfers are stopped at the block gap by setting stop at block gap request in the block gap control register and data transfers completed. (after valid data is written to the sd card and the busy signal released). refer to section 3.10.4 for more detail s on the sequence of events. the table below shows that transfer complete has higher priority than data timeout error. if both bits are set to 1, the data transfer can be considered complete. tc timeout error meaning of the status 0 0 interrupted by another factor 0 1 timeout occur during transfer 1 don't care data transfer complete 0 0 r/wc command complete (cc): this bit is set when get the end bit of the command response. (except auto cmd1 2) refer to pstate.ci. the table below shows that erintsts.cte has higher priority than this bit. if both bits are set, the response was not received correctly. cc cmd timeout error meaning of the status 0 0 interrupted by another factor 1 0 response received x 1 response not received within 64 sdclk cycles. bit default and access description
datasheet 329 sdio/mmc (d30:f0, f1, f2) 15.3.19 erintsts?error inte rrupt status register i/o offset: base + (32h-33h) attribute: ro, r/wc default value: 0000h size: 16 bits bit default and access description 15:9 00h ro reserved 8 0 r/wc auto cmd12 error (ac12): occurs when detecting that one of the bits in ac12es has been set. this bit is set not only on errors on auto cmd12 occur but also when auto cmd12 is not executed due to the previous command error. 7 0 r/wc current limit error (cl): by setting pc.bp, intel? sch is requested to supply power to the sd bus. if in tel? sch supports the current limit function, it can be protec ted from an invalid card by stopping power supply to the card in which case this bit indicates a failure status. reading 1 means the host controller is not suppl ying power to sd card due to some failure. reading 0 means that the host controller is su pplying power and no error has occurred. the host cont roller may require some sampling time to detect the current limit. if the host controller does not support this function, this bit shall always be set to 0. 6 0 r/wc data end bit error: occurs either when detectin g 0 at the end bit position of read data which uses the dat line or at the end bit position of the crc status. 5 0 r/wc data crc error: occurs when detect ing crc error when transferring read data which uses the dat line or wh en detecting the write crc status having a value of other than 010. 4 0 r/wc data timeout error (dte): occurs when detect ing one of following timeout conditions: ? busy timeout for r1b,r5b type ? busy timeout after write crc status ? write crc status timeout ? read data timeout. 3 0 r/wc command index error (cie): occurs if a command index error occurs in the command response. 2 0 r/wc command end bit error (cebe): occurs when the end bit of a command response is 0. 1 0 r/wc command crc error (cce): command crc error is generated in two cases. ? if a response is returned and cte is cleared, this bit is set when detecting a crc error in the command response. ? if intel? sch drives sd_cmd to 1, but detects 0 on the next sd_clk edge, intel? sch aborts the comm and (stops driving cmd line) and sets this bit. cte shall also be set. 0 0 r/wc command timeout error (cte): occurs only if no response is returned within 64 sdclks from the end bit of the command. if intel? sch detects a cmd line conflict, in which case co mmand crc error shall also be set, this bit shall be set and th e command will be aborted.
sdio/mmc (d30:f0, f1, f2) 330 datasheet 15.3.20 ninten?normal inte rrupt enable register i/o offset: base + (34h-35h) attribute: ro, r/w default value: 0000h size: 16 bits these bits enable or mask the different normal interrupts. bit default and access description 15 0 ro reserved: hardcoded to 0. 14:9 00h ro reserved 8 0 r/w card interrupt status enable (cise): this bit should be cleared before servicing a card interrup t, and then enabled afte r all interrupt requests from the card are serviced and cleared. 0 = card interrupt reporting is masked 1 = card interrupt reporting is enabled 7 0 r/w card removal status enable (crse) 6 0 r/w card insertion status enable (cise) 5 0 r/w buffer read ready status enable (brse) 4 0 r/w buffer write ready status enable (bwse) 3 0 r/w dma interrupt status enable (dise) 2 0 r/w block gap event status enable (bgse) 1 0 r/w transfer complete status enable (tcse) 0 0 r/w command complete status enable (ccse)
datasheet 331 sdio/mmc (d30:f0, f1, f2) 15.3.21 erinten?error inte rrupt enable register i/o offset: base + (36h-37h) attribute: ro, r/wc default value: 0000h size: 16 bits bit default and access description 15:9 00h ro reserved 8 0 r/wc auto cmd12 error enable 7 0 r/wc current limit error enable 6 0 r/wc data end bit error enable 5 0 r/wc data crc error enable 4 0 r/wc data timeout error enable 3 0 r/wc command index error enable 2 0 r/wc command end bit error enable 1 0 r/wc command crc error enable 0 0 r/wc command timeout error enable
sdio/mmc (d30:f0, f1, f2) 332 datasheet 15.3.22 nintsigen?normal interr upt signal enable register i/o offset: base + (38h-39h) attribute: ro, r/wc default value: 0000h size: 16 bits this register is used to select which normal interrupt status is indicated to the host system as the interrupt. these status bits all share the same 1 bit interrupt line. setting any of these bits to 1 enables interrupt generation. bit default and access description 15:9 00h ro reserved 8 0 r/w card interrupt signal enable 7 0 r/w card removal signal enable 6 0 r/w card insertion signal enable 5 0 r/w buffer read ready signal enable 4 0 r/w buffer write ready signal enable 3 0 r/w dma interrupt signal enable 2 0 r/w block gap event signal enable 1 0 r/w transfer complete signal enable 0 0 r/w command complete signal enable
datasheet 333 sdio/mmc (d30:f0, f1, f2) 15.3.23 erintsigen?error interru pt signal enable register i/o offset: base + (3ah-3bh) attribute: ro, r/wc default value: 0000h size: 16 bits this register is used to select which interrupt status is notified to the host system as the interrupt. these status bits all share th e same 1-bit interrupt line. setting any of these bits to 1 enables interrupt generation. non-reserved bits in this register are cleared by writing a 1 to them. bit default and access description 15:9 0h ro reserved 8 0 r/wc auto cmd12 error signal enable 7 0 r/wc current limit error signal enable 6 0 r/wc data end bit error signal enable 5 0 r/wc data crc error signal enable 4 0 r/wc data timeout error signal enable 3 0 r/wc command index error signal enable 2 0 r/wc command end bit error signal enable 1 0 r/wc command crc error signal enable 0 0 r/wc command timeout error signal enable
sdio/mmc (d30:f0, f1, f2) 334 datasheet 15.3.24 ac12errsts?automatic cm d12 error status register i/o offset: base + (3ch-3dh) attribute: ro default value: 0000h size: 16 bits 15.3.25 cap?capabilities register i/o offset: base + (40h-43h) attribute: ro default value: 00000060h size: 32 bits bit default and access description 15:8 00h ro reserved 7 0 ro command not issued error (ncie): when set, indicates than a command (without sd_dat being used) was not executed due to an index error, end bit error, crc error, or timeout error. 6:5 00b ro reserved 4 0 ro index error (ie): occurs if the command inde x error occurs in response to a command. 3 0 ro end bit error (ebe): occurs when the end bit if a command response is 0. 2 0 ro crc error (crce): occurs in a crc error is detected in the command response. 1 0 ro timeout error (te): if no response is return ed within 64 sd_clk?s from the command end bit, this will be set. if set, ie, ebe, and crce have no meaning. 0 0 ro not executed (ne): indicates that an error has prevented the intel? sch from issuing the autocmd12 to stop a multiple-block transfer. if set, te, ie, ebe, and crce have no meaning. bit default and access description 63:27 00h ro reserved 26 0 ro support for 1.8 v (s18) 0 = indicates 1.8 v is not supported. 25 0 ro support for 3.0 v (s30) 0 = indicates 3.0 v is not supported. 24 1 ro support for 3.3 v (s33) 1 = indicates that 3.3 v is supported. 23 0 ro suspend/resume support (srs) 1 = suspend and resume are not supported 0 = suspend and resume are supported 22 1 ro dma support (dma) 1 = indicates that dma transfers are supported.
datasheet 335 sdio/mmc (d30:f0, f1, f2) 21 1 ro high-speed support (hs) 1 = indicates that high-spe ed operation is supported. 20:18 000b ro reserved 17:16 desc ro max block length (mbl): the maximum block length is fixed by these bits. 15:14 00b ro reserved 13:8 30h ro base clock frequency for sd_clk (bcf): this value indicates the base (maximum) clock frequency for the sd clock. unit values are 1 mhz. if the real frequency is 16.5mhz, th e lager value shall be set 01 0001b (17 mhz) because the host driver use this value to calculate the clock divider value (refer to the sdclk frequency se lect in the clock control register.) and it shall not exceed upper li mit of the sd clock frequency. the supported clock range is 10 mhz to 63 mhz. if these bits are all 0, the host system has to get information using another method. 7 1 ro timeout clock unit (tcu): this bit shows the unit of base clock frequency used to detect data timeout error. 0 = khz, 1 = mhz 6 0 ro reserved 5:0 30h ro timeout clock frequency (tcf): this bit shows the base clock frequency used to detect data timeout error. the timeout clock unit defines the unit of this fields value. timeout clock unit =0 [khz] unit: 1 khz to 63 khz timeout clock unit =1 [mhz] unit: 1 mhz to 63 mhz not 0 1 khz to 63 khz or 1 mhz to 63 mhz bit default and access description function bits max block size d30:f0 10 2048 bytes d30:f1 00 512 bytes d30:f2 00 512 bytes
sdio/mmc (d30:f0, f1, f2) 336 datasheet 15.3.26 mccap?maximum current capabilities register i/o offset: base + (48h-4bh) attribute: ro default value: 00000000 00000000h size: 32 bits 15.3.27 sltintsts?slot in terrupt status register i/o offset: base + (fch-fdh) attribute: ro default value: 0000h size: 16 bits 15.3.28 hcver?host cont roller version register i/o offset: base + (feh ? ffh) attribute: ro default value: 0000h size: 16 bits bit default and access description 63:24 00h ro reserved 23:16 00h ro maximum current for 1.8 v 000 - get information from other sources 15:8 00h ro maximum current for 3.0 v 000 - get information from other sources 7:0 01h ro maximum current for 3.3 v this field reports the max current that the power supply can deliver to the sdio card. 01 = 4 ma is the max current th at the controller can deliver. however, the intel? sch does not report the actual max current, software should ignore the max current value reported in this field. bit default and access description 15:1 0000h ro reserved 0 0 ro slot 0 interrupt: logical or of the interrupt signal and wakeup signal. bit default and access description 15:8 00h ro vendor version number (vvn): 00h indicates th e first version. 7:0 00h ro specification version number (svn): 00h indicates support for specification version 1.0.
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datasheet 339 parallel ata (d31:f1) 16 parallel ata (d31:f1) 16.1 functional overview the intel? sch pata interface supports only the primary channel, with one master and one slave device. any writes to the secondary channel are ignored, and reads will return all ones, except for bit 7, which returns a 0. the parallel ata (pata) controller in the in tel? sch supports three types of data transfers: 1. programmed i/o (pio): a protocol used to transfer data between the processor as the ata device. pio allows transfer rates up to 16 mb/s. 2. multi-word dma: dma protocol that re sembles the dma on the isa bus. allows transfer rates of up to 16 mb/s. 3. ultra-dma: source synchronous dma protocol that allows transfer rates of up to 100 mb/s. 16.1.1 programmed i/o transfers the programmed i/o (pio) transfer method us es the processor to move data between an i/o port and main memory through individual operations. a typical sequence follows: ? the processor programs the i/o device with a command. ? data is transferred (either as a series of pio operations to the data port or as a dma operation) ? the i/o device asserts an interrupt when all data has been transferred. ? the processor reads status information from the device. table 45. supported pata standards and modes pata standard transfer modes supported transfer rate (mb/s) ata-1 (ata, ide) pio modes 0, 1, 2 3.3, 5.2, 8.3 single-word dma modes 0, 1, 2 2.1, 4.2, 8.3 multi-word dma mode 0 4.2 ata-2, ata-3 (eide, fast ata) pio modes 3,4 11.1, 16.6 multi-word dma modes 1,2 13.3, 16.6 ata/atapi-4 (ultra dma, ultra ata) ultra dma modes 0,1, 2 (a.k.a. ultra dma/33) 16.7, 25.0, 33.3 ata/atapi-5 (ultra-dma, ultra ata) ultra dma modes 3, 4 (a.k.a. ultra dma/66) 44.4, 66.7 ata/atapi-6 (ultra-dma, ultra ata) ultra-dma mode 5 (a.k.a. ultra dma/100) 100 (reads) 89 (writes)
parallel ata (d31:f1) 340 datasheet 16.1.1.1 ata port decode ta b l e 4 6 specifies the registers that effect the intel? sch hardware definition. the data register must be accessed using 16-bit or 32-bit i/o instructions. all other registers must be accessed using 8-bit i/o instructions. these following registers are implemented in the device. the command and control blocks are accessible at fixed i/o addresses. these blocks are decoded when cmd.iose is set. an access to these addresses results in the assertion of the appropriate chip sele ct (pata_dcs1# / pata_dcs3#) and the command strobes (pata_dior#, pata_diow#). there are two i/o ranges: the command block, which corresponds to the pata_dcs1# chip select, and the control block, which corresponds to the pata_dcs3# chip select. the command block is an 8-byte range, wh ile the control block is a 4-byte range. ? command block offset: 01f0h for primary, 0170h for secondary ? control block offset: 03f4h for primary, 0374h for secondary the secondary range, while active, does not result in cycles on the interface. table 46. ata command block registers (pata_dcs1#) i/o offset function (read) function (write) 00h data data 01h error features 02h sector count sector count 03h sector number sector number 04h cylinder low cylinder low 05h cylinder high cylinder high 06h drive head 07h status command table 47. ata control bloc k registers (pata_dcs3#) i/o offset function (read) function (write) 00h reserved 01h reserved 02h alt status device control 03h forward to lpc - not claimed by ide
datasheet 341 parallel ata (d31:f1) 16.1.1.2 pio cycle timings 16.1.1.2.1 pio timing modes an ata transaction consists of startup latency, cycle latency, and shutdown latency. ? startup latency provides the setup time for chip select and address pins with respect to the read and write strobes. ? cycle latency consists of the i/o strobe assertion length and recovery time. recovery time is provided so that transactions may occur back to back on the interface without incurring additional startup and shutdown latency. ? shutdown latency is incurred after an outstanding transaction has completed and before another transaction can proceed (such as one to a different address). it provides hold time on the chip select and address pins with respect to the read and write strobes. accesses to the data port are the only accesses where multiple cycle latency cycles may run under a single startup and shutdown latency. for non-data port and non- enhanced mode data port transactions, startup and shutdown latency are always incurred. the chip selects are assured to be deasserted for at least two ata clocks after the deassertion of the i/o strobe for the last transaction and before the startup latency of the next. 16.1.1.2.2 wait states with pata_iordy if pata_iordy is deasserted when the initia l sample point is reached, additional wait states are added. since the rising edge of pata_iordy must be synchronized, at least two additional core clocks are added. 16.1.1.2.3 write posting the intel? sch absorbs i/o writes to the da ta port into a buffer when d0tim.ppe is set. when the buffer is full, subsequent writes are held in wait-states. the buffer can accept writes of 16 bits, and will not accept data until it is completely empty. 16.1.1.2.4 read prefetch read prefetch is enabled by setting bits in the pci configuration register 40h: bit 2 for device 0 and bit 6 for device 1. a 32-bit buffer is provided per cable to pre-fetch from each data port. if pre-fetching is enabled, and the command is a ?safe? read command, the sector will be pre-fetched. pre-fetch is not initiated until the first data port read. pre-fetches from the data port are scheduled as two back-to-back 16-bit reads on the interface. words 255 and 256 of the sector are not pre- fetched to avoid fetching across a sector boundary. after the 256th word is read, pre-fe tching resumes if a subsequent data port read occurs. if a write to byte 7 of th e ata command block occurs, the buffer is invalidated and pre-fetching is disabled.
parallel ata (d31:f1) 342 datasheet 16.1.1.3 cycle snooping 16.1.1.3.1 device active status the task file is shared between two devices on a single cable. ownership is transferred between devices through a write to bit 4 of the device/head register (address 1f6h for primary, 176h for secondary). the intel? sch snoops this write so that it can run with the proper timings for that device. when cleared, the master or ?device 0? owns the cable. when set, the slave or ?device 1? owns the cable. the intel? sch only allows pre-fetching of 512-byte sectors, and certain devices. the intel? sch snoops writes to the command re gister. ?safe? read commands are defined in the table below. ? 20h: read sector with retry ? 21h: read sector without retry ? c4h: read multiple sectors 16.1.2 multi-word dma transfers in the multi-word dma and ultra dma protocol s, the intel? sch acts as a bus master to communicate with main memory, and transfers data to the device. the following terms are used for dma transfers: ? read state: data transfers from main memory to a device ? write state : data transfers from a device to main memory. dma transfers are performed as scatter-gather. software builds a table of physical region descriptors (prds) in memory that contains base memory addresses for the source or destination of data, and byte counts off that base address. ta b l e 4 8 and ta b l e 4 9 show the structure of prd base address and descriptor information. the intel? sch fetches from this table and mo ves data between the device and memory location pointed to by the table. each entry in the table is called a physical region descriptor (prd). note: the memory region specified by the desc riptor cannot cross a 64 kb boundary. ta b l e 5 0 describes how to interpret the pata status register bits after a dma transfer has started. table 48. prd base address bit description 31:0 data base address (dba): indicates the 32-bit offset of the data block. table 49. prd descriptor information bit description 31 end of list (e): when set, indicates this is the last entry in the list. intel? sch stops processing entries at this point. 30:16 reserved 15:0 byte count (bc): indicates the length, in bytes, of the data block. bit 0 of this structure must always be 0 to in dicate an even number of bytes.
datasheet 343 parallel ata (d31:f1) 16.1.2.1 dma protocol to initiate a bus master transfer between memory and a pata device, the following steps are required: 1. software prepares a prd table in system memory. the prd table must be dword- aligned and must not cross a 64 kb boundary. 2. software provides the starting address of the prd table by loading the prd table pointer register. the direction of the data transfer is specified by setting the read/ write control bit. the interrupt bit and error bit in the status register are cleared. 3. software issues the appropriate dma transfer command to the disk device. 4. the bus master function is engaged by so ftware writing a 1 to the start bit in the command register. the first entry in the prd table is fetched and loaded into two registers which are not visible by software, the current base and current count registers. these registers hold the current value of the address and byte count loaded from the prd table. the value in th ese registers is only valid when there is an active command to an ide device. 5. once the prd is loaded internally, the pata device will receive a dma acknowledge. 6. the controller transfers data to/from memo ry responding to dma requests from the pata device. the pata device and the host controller may or may not throttle the transfer several times. when the last data transfer for a region has been completed on the ide interface, the next descriptor is fetched from the table. the descriptor contents are loaded into the current base and current count registers. 7. at the end of the transfer, the pata device signals an interrupt. 8. in response to the interrupt, software resets the start/stop bit in the command register. it then reads the controller status followed by the drive status to determine if the transfer completed successfully. the last prd in a table has the end of list (eol) bit set. the pci bus master data transfers terminate when the physical region described by the last prd in the table has been completely transferred. the active bi t in the status register is reset and the ddrq signal is masked. the buffer is flushed (when in the write state) or invalidated (when in the read state) when a terminal count condition exists; that is, the current region descriptor has the eol bit set and that region has been exhausted. the buffer is also flushed (write state) or invalidated (read state) when the inte rrupt bit in the bus master pata status register is set. software that reads the status register and finds the error bit reset, and either the active bit reset or the interrupt bi t set, can be assured that all data destined for system memory has been transferred an d that data is valid in system memory. ta b l e 5 0 describes how to interpret the interrupt and active bits in the status register after a dma transfer has started. table 50. interrupt/act ive bit interaction int active description 0 1 dma transfer is in progress. 10 the device generated an interrupt. the controller exhausted the prd. indicates the size of the prd was equal to the device transfer size. 11 the device generated an in terrupt. the controller has not reached the end of the prd. indicates the size of the prd was larger than the device transfer size. 00 this is an error condition. the prd's specified a smaller size than the device?s transfer size.
parallel ata (d31:f1) 344 datasheet 16.1.3 synchronous (u ltra) dma transfers the intel? sch supports ultra dma/100/66/33 bus mastering protocol, providing support for a variety of transfer speeds with pata devices. ultra dma mode 3 provides transfers up to 33 mb/s, ultra dma mode 4 provides transfers at up to 44 mb/s or 66 mb/s, and ultra dma mode 5 can achieve read transfer rates up to 100 mb/s and write transfer rates up to 88.9 mb/s. the ultra dma definition also incorporates a cyclic redundancy checking (crc-16) error checking protocol. 16.1.3.1 operation initial setup programming consists of enablin g and performing the proper configuration of the intel? sch and the pata device for ultra dma operation. for the intel? sch, this consists of enabling synchronous dma mode and setting up appropriate synchronous dma timings. when ready to transfer data to or from an pata device, the bus master pata programming model is followed. once programmed, the pata device and the intel? sch controls the transfer of data by ultra dma protocol. the actual data transfer consists of three phases, a start-up phase, a data transfer phase, and a burst termination phase. the pata device begins the start-up phase by asserting dmarq signal. when ready to begin the transfer, the intel? sch assert s pata_dmack# signal. when pata_dmack# signal is asserted, the host controller drives cs0# and cs1# inactive, pata_da[2:0] low. for write cycles, the intel? sch deasserts stop, waits for the pata device to assert pata_iordy#, and then drives the fi rst data word and strobe signal. for read cycles, the intel? sch tri-states the pata_dd lines, deasserts stop, and asserts pata_iordy#. the pata device then sends the first data word and strobe. the data transfer phase continues the burst transfers with the data transmitter (intel? sch ? writes, pata device ? reads) prov iding data and toggling strobe. data is transferred (latched by receiver) on each rising and falling edge of strobe. the transmitter can pause the burst by holding st robe high or low, resuming the burst by again toggling strobe. the receiver can pause the burst by deasserting dmardy# and resumes the burst by asserting dmardy#. the intel? sch pauses a burst transaction to prevent an internal line buffer overflow or underflow condition, resuming once the condition has cleared. it may also pause a transaction if the current prd byte count has expired, resuming once it has fetched the next prd. the current burst can be terminated by either the transmitter or receiver. a burst termination consists of a stop request, st op acknowledge and transfer of crc data. the intel? sch can stop a burst by asserting stop, with the pata device acknowledging by deasserting dmarq. the pata device stops a burst by deasserting dmarq and the intel? sch acknowledges by asserting stop. the transmitter then drives the strobe signal to a high level. the intel? sch then drives the crc value onto the dd lines and deassert dmack#. the pata device latches the crc value on rising edge of dmack#. the intel? sch term inates a burst transfer if it needs to service the opposite pata channel, if a programmed i/o (pio) cycle is executed to the pata channel currently running the burst, or upon transferring the last data from the final prd.
datasheet 345 parallel ata (d31:f1) 16.1.3.2 ultra dma timing the cycle time and ready to pause time for ultra dma modes are programmed by the d0tim register. the cycle time represents th e minimum pulse width of the data strobe (strobe) signal. the ready to pause time represents the number of base clock periods that the intel? sch waits from deassertion of dmardy# to the assertion of stop when it desires to stop a burst read transaction. the internal base clock for ultra dma/100 (mode 5) runs at 133 mhz, and the cycle time (ct) must be set for three base clocks. the intel? sch thus toggles the write strobe signal every 22.5 ns, transferring two bytes of data on each strobe edge. this means that the intel? sch performs mode 5 write transfers at a maximum rate of 88.9 mb/s. for read transfers, the read stro be is driven by the pata device, and the intel? sch supports reads at the maximum rate of 100 mb/s. 16.2 pci configuration registers all of the pata registers are in the core power well, and none of the registers can be locked. any undefined registers in the pata register address map should be treated as reserved. note: address locations that are not shown should be treated as reserved. table 51. pata register address map offset mnemonic register name default type 00h?03h id identifiers 811a8086 ro 04h?05h pcicmd command register 0000h ro, r/w 06h?07h pcists device status 0000h ro 08h rid revision id see description ro 09h?0bh cc class codes 010180h ro 0ch cls cache line size 0000h ro 0dh mlt master latency timer 0000h ro 20h?23h bmbar bus master base address 00000001h ro, r/w 2ch?2fh ss subsystem identifiers 00000000h ro, r/w 3ch?3dh intr interrupt informat ion see description ro, r/w 60h?63h mc miscellaneous configuration 00000000h ro, r/w 80h?83h d0tim device 0 timing 00000000h ro, r/w 84h?87h d1tim device 1 timing 00000000h ro, r/w
parallel ata (d31:f1) 346 datasheet 16.2.1 id?identifiers register offset: 00?03h attribute: ro default value: 811a8086h size: 32 bits 16.2.2 pcicmd?command register offset: 04h?05h attribute: ro, r/w default value: 0000h size: 16 bits 16.2.3 pcists?device status register offset: 06h?07h attribute: ro default value: 0000h size: 16 bits bit default and access description 31:16 811ah ro device id (did): 811ah indicates this is a pata controller. 15:0 8086h ro vendor id (vid): 16-bit field which indicates the company vendor. bit default and access description 15:11 00h ro reserved 10 0 r/w interrupt disable (id) 0 = when cleared, irq14 may be asserted 1 = when set, irq14 is deasserted 9:3 00h ro reserved 2 0 r/w bus master enable (bme): this bit controls the host controller?s ability to act as a master. 10reserved 0 0 r/w i/o space enable (iose) 0 = disable 1 = enable. access to the ata port s and the dma registers is enabled bit default and access description 15:4 00h ro reserved 3 0 ro interrupt status (is): reflects the state of in terrupt at the input of the enable/disable circuit. this bit is a 1 when the interrupt is asserted. this bit is a 0 after the interrupt is cleared (independent of the state of the interrupt disable bit in the command register). 2:0 000b ro reserved
datasheet 347 parallel ata (d31:f1) 16.2.4 rid?revision id register offset: 08h attribute: ro, r/w default value: see description size: 8 bits the value reported in this register comes from the rid register in the lpc bridge. 16.2.5 cc?class code register offset: 09h?0bh attribute: ro default value: 010180h size: 24 bits 16.2.6 cls?cache line size register offset: 0ch attribute: ro default value: 0000h size: 16 bits 16.2.7 mlt?master latency timer register offset: 0dh attribute: ro default value: 0000h size: 16 bits bit default and access description 7:0 see description ro revision id : refer to the intel ? system controller hub (intel ? sch) specification update for the value of the revision id register. bit default and access description 23:16 01h ro base class code (bcc): this field indicates that this is a mass storage device. 15:8 01h ro sub class code (scc): this field indicates that this is a device. 7:0 80h ro programming interface (pip): 80h indicates this is a bus master. bit default and access description 15:0 0000h ro reserved bit default and access description 15:0 0000h ro reserved
parallel ata (d31:f1) 348 datasheet 16.2.8 bmbar?bus master base address register offset: 20h?23h attribute: ro, r/w default value: 00000001h size: 32 bits this bar is used to allocate i/o space for the sff-8038i mode of operation (dma). 16.2.9 ss?sub system identifiers register offset: 2ch?2fh attribute: ro, r/w default value: 00000000h size: 32 bits the value reported in this register comes fr om the value of the ss register in the lpc bridge. 16.2.10 intr?interrupt information register offset: 3ch?3dh attribute: ro, r/w default value: see description size: 16 bits bit default and access description 31:16 0000h ro reserved 15:4 00h r/w base address (ba): this field is the base address of the i/o space (16, consecutive i/o locations). 3:1 000b ro reserved 0 1 ro resource type indicator (rte): this bit indicate s a request for i/o space. bit default and access description 15:8 00h ro interrupt pin (ipin): reserved 7:0 00h r/w interrupt line (iline): this field is a software written value to indicate which interrupt line (vecto r) the interrupt is connected to. no hardware action is taken on this register.
datasheet 349 parallel ata (d31:f1) 16.2.11 mc?miscellaneous configuration register offset: 60h?63h attribute: ro, r/w default value: 00000000h size: 32 bits this register provides global configuration parameters for the controller. 16.2.12 d0tim/d1tim?device 0/1 timing register offset: d0tim: 80h?83h attribute: ro, r/w d1tim: 84h?87h default value: 00000000h size: 32 bits bit default and access description 31:3 0s ro reserved 2 0 r/w drive bus to ground (dbc) 0 = pins are in their normal mode 1 = all pata interface pins are driven to ground 1 0 r/w tristate bus (tb) 0 = pins are in their normal mode 1 = all pata interface pins are tri-stated. 0 0 rw base clock lower half (bclh): this bit determines the base clock to use when building counts. 0 = 100 mhz 1 = 133 mhz bit default and access description 31 0 r/w use synchronous dma (usd) 0 = multi-word dma modes are used for dma transfers 1 = synchronous dma modes are used for dma transfers 30 0 r/w prefetch/post enable (ppe): when using pio, this bit enables the prefetch/post buffer. 29:19 0s ro reserved
parallel ata (d31:f1) 350 datasheet 18:16 000b r/w ultra dma mode (udm): this field indicates which timings to use when running synchronous dma cycles to the device. 100 mhz timing: there are also fixed clock counts, regardless of dma mode, that are used when starting and stopping transactions: 15:10 000000b ro reserved 9:8 00b r/w mutli-word dma mode (mdm): this field indicates which timings to use when running multi-word dma cycles to the device. 7:3 00000b reserved 2:0 000b r/w pio mode (pm): this filled indicates which timings to use when running pio cycles to the dataport. bit default and access description bits mode intel? sch receiving intel? sch driving t cyc t rp t cyc 000 mode 0 7 16 12 001 mode 1 5 13 8 010 mode 2 4 10 6 011 mode 3 2 10 4 100 mode 4 1 10 3 101 mode 5 1 9 2 110 ? 111 reserved mc.bc tenv tli tmli tss 003036 014047 104048 114049 bits mode 100 mhz clock stb rec 00 mode 0 22 26 01 mode 1 8 7 10 mode 2 7 5 11 reserved bits mode startup strobe recovery 100 mhz timings -register72924 000 mode 0 7 17 37 001 mode 1 5 13 21 010 mode 2 3 10 11 011 mode 3 3 8 7 100 mode 4 3 7 3 111 reserved
datasheet 351 parallel ata (d31:f1) 16.3 i/o registers intel? sch uses 16 bytes of i/o space, a llocated by bmbar. reading reserved bits returns an indeterminate, inconsistent value, and writes to reserved bits have no effect. note: the secondary registers are availabl e, but provide no functionality. 16.3.1 pcmd?primary command register offset: 00h attribute: ro, r/w default value: 00h size: 8 bits table 52. pata memory-mapped i/o register address map offset mnemonic register name default access 00h pcmd primary command 00h ro, r/w 02h psts primary status 00h ro, r/w, r/wc 04h pdtp primary data table pointer see description ro, r/w 10h scmd secondary command see note 12h ssts secondary status 14h sdtp secondary data table pointer bit default and access description 7:4 0000b ro reserved 3 0 r/w read/write (rwc): this bit sets the direction of the bus master transfer: this bit must not be change d when the bus mast er function is active. 0 = memory to device 1 = device to memory 2:1 00b ro reserved 0 0 r/w start/stop bus master (start): this bit, when set, enables bus master operation of the controller. all state information is lost when this bit is cleared. master mode operatio n cannot be paused. if this bit is reset while bus master operation is still active and the device has not yet finished its data transfer, the bus master command is said to be aborted.
parallel ata (d31:f1) 352 datasheet 16.3.2 psts?primary status register offset: 02h attribute: ro, r/w, r/wc default value: 00h size: 8 bits 16.3.3 pdtp?primary descript or table pointer register offset: 04h attribute: ro, r/w default value: see description size: 32 bits bit default and access description 7 0 ro reserved 6 0 r/w device 1 dma capable (d1dc): a scratchpad bit set by device dependent code to indicate that device 1 of this channel is capable of dma transfers. this bit has no effect on hardware. 5 0 r/w device 0 dma capable (d0dc): a scratchpad bit set by device dependent code to indicate that device 0 of this channel is capable of dma transfers. this bit has no effect on hardware. 4:3 00b ro reserved 2 0 r/wc interrupt (i): this bit is set when ideirq goes active. when set, all data transferred from the device is valid at its destination. if cleared while the interrupt is still active, this bit re mains cleared until another assertion edge is detected on the interrupt line. 1 0 ro error (err): intel? sch will never set this bit. 0 0 ro active (act): this bit is set by the host when pcmd.start is set, and cleared by the host when the last tran sfer for a region is performed, where eot for that region is set in the re gion descriptor, and when pcmd.start is cleared and the controller has returned to an idle condition. bit default and access description 31:2 see description r/w descriptor base address (dba): this field corresponds to a[31:2]. this table must not cross a 64 kb bo undary in memory. when read, the current value of the pointer is returned. 1:0 00b ro reserved
datasheet 353 lpc interface (d31:f0) 17 lpc interface (d31:f0) 17.1 functional overview the lpc controller implements a low pin count interface that supports the lpc 1.1 specification: ? lsmi# can be connected to any of the smi capable gpio signals. ? the ec's pme# should connect it to gpe#. ? the lpc controller's sus_stat# signal is connected directly to the lpcpd# signal. the lpc controller does not implement dma or bus mastering cycles. the lpc bridge function of the intel? sch resides in pci device 31:function 0. this function contains many other functional units, such as interrupt controllers, timers, power management, system management , gpio, rtc, and lpc configuration registers. this section contains the pci configuration registers for the primary lpc interface. power management details are foun d in a separate chapter, and other acpi functions (rtc, smbus, gpio, interrupt cont rollers, timers, etc.) can be found in the acpi chapter. 17.1.1 memory cycle notes for cycles below 16m, the lpc controller will perform standard lpc memory cycles. for cycles targeting firmware, firmware memory cycles are used. only 8-bit transfers are performed. if a larger transfer appears, th e lpc controller will break it into multiple 8-bit transfers until the request is satisfied. if the cycle is not claimed by any peripheral (and subsequently aborted), the lpc controller will return a value of all 1s to the processor. 17.1.2 tpm 1.2 support the lpc interface supports accessing tpm 1.2 devices by lpc tpm start encoding. memory addresses within the range fed40000h to fed4bfffh will be accepted by the lpc bridge and sent on lpc as tpm special cycles. no additional checking of the memory cycle is performed. 17.1.3 fwh cycle notes the intel? sch has been designed to accommodate both lpc and fwh interfaces which allows the fwh interface signals to be communicated over the same set of pins as lpc. the fwh interface is designed to use an lpc-compatible start cycle, with a reserved cycle type code. this ensures that all lpc devices present on the shared interface will ignore cycles destined for th e fwh, without becoming ?confused? by the different protocol. if a flash device connects to lpc interface, it must be compliant with fwh specification 1.0e. the first bios commands issued to the lpc bus use the fwh instruction set and will not execute properly unless a fwh-compatible flash device is used. if the lpc controller receives any sync re turned from the device other than short (0101), long wait (0110), or ready (0000) when running a fwh cycle, indeterminate results may occur. a fwh device is not allowed to assert an error sync.
lpc interface (d31:f0) 354 datasheet 17.1.4 lpc output clocks the intel? sch provides three output clocks to drive external lpc devices that may require a pci-like clock (25 mhz or 33 mhz). the lpc output clocks operate at 1/4th the frequency of h_clkin[p/n]. lpc_clkout0 should be used to provide clocking to the fwh boot device. because lpc_clkout0 is the first clock to be used in the system, configuring its drive strength is done by a strapping option on the reserved1 pin. (refer to ta b l e 3 .) the buffer strengths of lpc_clkout1 an d lpc_clkout2 default to 2-loads per clock and can be reprogrammed by the cmc by using the softstrap utility. note: by default, the lpc clocks are only active when lpc bus transfers occur. because of this behavior, lpc clocks must be routed dire ctly to the bus devices; they cannot go through a clock buffer or other circuit that could delay the signal going to the end device. 17.2 pci configuration registers note: address locations that are not shown should be treated as reserved. . table 53. lpc interface pci register address map offset mnemonic register name default type 00h?01h vid vendor identification 8086h ro 02h?03h did device identification 8119h ro 04h?05h pcicmd pci command 0003h ro 06h?07h pcists pci status 0000h ro 08h rid revision identification see register description ro 09h?0bh cc class codes 060100h ro 0eh headtyp header type 80h ro 2ch?2fh ss sub system identifiers 00000000h r/wo 40h?43h smbase smbus base address 00000000h ro. r/w 44h?47h gpiobase gpio base address 00000000h r/w, ro 48h?4bh pm1base pm1_blk base address 00000000h ro/ r/w 4ch?4fh gpebase gpe1_blk base address 00000000h ro, r/w 54h?57h lpcs lpc clock control 00000000h ro, r/w 58h?5bh acpi_ctl acpi control 00000000h ro, r/w 5ch?5fh mc miscellaneous control 00000000h ro, r/w 60h?67h pirq[x]_rt pirq[a?h] routing control 80h ro, r/w 68h sirq_ctl serial irq control 00h r/w, ro d4h?d7h bde bios decode enable ff000000h ro, r/w d8h?dbh bios_ctl bios control 00000100h ro, r/w f0h?f3h rcba root complex base address 00000000h ro, r/w
datasheet 355 lpc interface (d31:f0) 17.2.1 vid?vendor iden tification register offset: 00h ? 01h attribute: ro default value: 8086h size: 16 bit 17.2.2 did?device identification register offset: 02h ? 03h attribute: ro default value: see bit description size: 16 bit 17.2.3 pcicmd?pci command register offset: 04h ? 05h attribute: ro default value: 0003h size: 16 bit 17.2.4 pcists?pci status register offset: 06 ? 07h attribute: ro default value: 0000h size: 16 bit bit default and access description 15:0 8086h ro vendor id: this is a 16-bit value assigned to intel. bit default and access description 15:0 8119h ro device id: this is a 16-bit value assign ed to the intel? sch lpc bridge. bit default and access description 15:3 0 ro reserved 1 1 ro memory space enable (mse): memory space cannot be disabled on lpc. 0 1 ro i/o space enable (iose): i/o space cannot be disabled on lpc. bit default and access description 15:0 0000h ro reserved
lpc interface (d31:f0) 356 datasheet 17.2.5 rid?revision iden tification register offset: 08h attribute: ro default value: see bit description size: 8 bits 17.2.6 cc?class codes register offset: 09h?0bh attribute: ro default value: 060100h size: 24 bits 17.2.7 headtyp?header type register offset: 0eh attribute: ro default value: 80h size: 8 bits bit default and access description 7:0 ro revision id: refer to the intel ? system controller hub (intel ? sch) specification update for the value of the revision id register. bit default and access description 23:16 06h ro base class code (bcc): this field indicates the de vice is a bridge device. 15:8 01h ro sub-class code (scc): this field indicates the device is a pci to isa bridge. 7:0 00h ro programming interface (pi): the lpc bridge has no programming interface. bit default and access description 7 1 ro multi-function device (mfd): this bit is 1 to indicate a multi-function device. 6:0 00h ro header type (htype): identifies the header la yout is a generic device.
datasheet 357 lpc interface (d31:f0) 17.2.8 ss?sub system identifiers register offset: 2ch?2fh attribute: r/wo default value: 00000000h size: 32 bits this register is initialized to logic 0 by th e assertion of reset#. this register can be written only once afte r reset# deassertion. 17.3 acpi device configuration 17.3.1 smbase?smbus ba se address register offset: 40h?43h attribute: ro, r/w default value: 00000000h size: 32 bits bit default and access description 31:16 0000h r/wo subsystem id (ssid): this is written by bios . no hardware action taken. 15:00 0000h r/wo subsystem vendor id (ssvid): this is written by bios. no hardware action is taken. bit default and access description 31 0b r/w enable (en) 1 = decode of the i/o range pointed to by the smbase.ba field is enabled. 30:16 0s ro reserved 15:6 0s r/w base address (ba): this field provides the 64 bytes of i/o space for smbus 5:0 0s ro reserved
lpc interface (d31:f0) 358 datasheet 17.3.2 gpiobase?gpio ba se address register offset: 44h?47h attribute: ro, r/w default value: 00000000h size: 32 bits 17.3.3 pm1base?pm1_blk base address register offset: 48?4bh attribute: ro, r/w default value: 00000000h size: 32 bits bit default and access description 31 0 r/w enable (en) 1 = decode of the i/o range pointed to by the gpiobase.ba is enabled. 30:16 0s ro reserved 15:6 0s r/w base address (ba): this field provides the 64 bytes of i/o space for gpio. 5:0 0s ro reserved bit default and access description 31 0 r/w enable (en) 1 = decode of the i/o range pointed to by the pm1base.ba is enabled. 30:16 0s ro reserved 15:4 0s r/w base address (ba): this field provides the 16 bytes of i/o space for pm1_blk. 3:0 0s ro reserved
datasheet 359 lpc interface (d31:f0) 17.3.4 gpe0base?gpe0_blk base address register offset: 4ch?4fh attribute: ro, r/w default value: 00000000h size: 32 bits for processor c-state microcode to function correctly, gpe0base must be located 16 bytes after pm1base. system bios has the responsibility to ensure these address are placed correctly. 17.3.5 lpcs?lpc clock control register offset: 54h?57h attribute: ro, r/w default value: 00000000h size: 32 bits the lpc clock 2 and 1 are controlled using the softstrap software. bit default and access description 31 0 r/w enable (en) 1 = decode of the io range pointed to by the gpe0base.ba is enabled. 30:16 0s ro reserved 15:6 0s r/w base address (ba): this field provides the 64 bytes of i/o space for pm1_blk 5:0 0s ro reserved bit default and access description 31:19 0s ro reserved 18 1 r/w clock 2 enable (en) 1 = enabled. 0 = disabled. 17 1 r/w clock 1 enable (en) 1 = enabled. 0 = disabled. 16:0 0s ro reserved
lpc interface (d31:f0) 360 datasheet 17.3.6 acpi_ctl?acpi control register offset: 58h?5bh attribute: ro, r/w default value: 00000001h size: 32 bits 17.3.7 mc - miscellaneous control register offset: 5ch?5fh attribute: ro, r/w default value: 00000000h size: 32 bits bit default and access description 31:3 0s ro reserved 2:0 001b r/w sci irq select (scis): this field specifies on which irq sci will rout to. if not using apic, sci must be routed to irq9?11, and that interrupt is not sharable with serirq, but is shar eable with other in terrupts. if using apic, sci can be mapped to irq20?23, and can be shared with other interrupts. when the interrupt is mapped to apic interrupts 9, 10 or 11, apic must be programmed for active -high reception. when the interrupt is mapped to apic interrupts 20 through 23, apic must be programmed for active- low reception. bits sci map bits sci map 000irq9100irq20 001 irq10 101 irq21 010 irq11 110 irq22 011 sci disabled 111 irq23 bit default and access description 31:0 0s ro reserved
datasheet 361 lpc interface (d31:f0) 17.4 interrupt control 17.4.1 pirq[n]_rout?pirq[a,b,c ,d] routing control register offset: pirqa ? 60h, pirqb ? 61h attribute: ro, r/w pirqc ? 62h, pirqd ? 63h pirqe ? 64h, pirqf ? 65h pirqg ? 66h, pirqh ? 67h default value: 80h size: 8 bits 17.4.2 sirq_ctl?serial irq control register offset: 68h attribute: ro, r/w default value: 00h size: 8 bits bit default and access description 7 1 r/w interrupt routing enable (irqen) 0 = the corresponding pirq is routed to one of the isa-compatible interrupts specifie d in bits[3:0]. 1 = the pirq is not routed to the 8259. note: bios must program this bit to 0 during post for any of the pirqs that are being used. the value of this bit may subsequently be changed by the os when setting up for i/o apic interrupt delivery mode. 6:4 000b ro reserved bit default and access description 7 0 r/w mode (md): this bit must be set to ensure that the first ac tion of intel? sch is a start frame. 0 = intel? sch is in quiet mode 1 = intel? sch is in continuous mode 6:0 0s ro reserved
lpc interface (d31:f0) 362 datasheet 17.5 fwh configuration registers 17.5.1 fwh_idsel?fwh id select register offset: d0h?d3h attribute: ro, r/w default value: 00112233h size: 32 bits bit default and access description 31:28 0h ro f8-ff idsel (if8): idsel to use in fwh cycle for range enabled by bde.ef8. the address ranges are: fff80000h ? ffffffffh, ffb80000h ? ffbfffffh and 000e0000h ? 000fffffh 27:24 0h r/w f0-f7 idsel (if0): idsel to use in fwh cycle for range enabled by bde.ef0. the address ranges are: fff00000h ? fff7ffffh, ffb00000h ? ffb7ffffh 23:20 1h r/w e8-ef idsel (ie8): idsel to use in fwh cycle for range enabled by bde.ee8. the address ranges are: ffe800 00h ? ffefffffh, ffa80000h ? ffafffffh 19:16 1h r/w e0-e7 idsel (ie0): idsel to use in fwh cycle for range enabled by bde.ee0. the address ranges are: ffe 00000h ? ffe7ffffh, ffa00000h ? ffa7ffffh 15:12 2h r/w d8-df idsel (id8): idsel to use in fwh cycle for range enabled by bde.ed8. the address ranges are: ffd80000h ? ffdfffffh, ff980000h ? ff9fffffh 11:8 2h r/w d0-d7 idsel (id0): idsel to use in fwh cycle for range enabled by bde.ed0. the address ranges are: ffd00000h ? ffd7ffffh, ff900000h ? ff97ffffh 7:4 3h r/w c8-cf idsel (ic8): idsel to use in fwh cycle for range enabled by bde.ec8. the address ranges are: ffc80000h ? ffcfffffh, ff880000h ? ff8fffffh 3:0 3h r/w c0-c7 idsel (ic0): idsel to use in fwh cycle for range enabled by bde.ec0. the address ranges are: ffc00000h ? ffc7ffffh, ff800000h ? ff87ffffh
datasheet 363 lpc interface (d31:f0) 17.5.2 bde?bios decode enable offset: d4h?d7h attribute: ro, r/w default value: 7f000000h size: 32 bits bit default and access description 31 0b ro f8?ff enable (ef8): enables decoding of bios range fff80000h ? ffffffffh and ffb80000h ? ffbfffffh. 0 = disable 1 = enable 30 1b r/w f0?f8 enable (ef0): enables decoding of bios range fff00000h ? fff7ffffh an d ffb00000h ? ffb7ffffh. 0 = disable 1 = enable 29 1b r/w e8?ef enable (ee8): enables decoding of bios range ffe80000h ? ffefffffh and ffa80000h ? ffafffffh. 0 = disable 1 = enable 28 1b r/w e0?e8 enable (ee0): enables decoding of bios range ffe00000h ? ffe7ffffh and ffa00000h ? ffa7ffffh. 0 = disable 1 = enable 27 1b r/w d8?df enable (ed8): enables decoding of bios range ffd80000h ? ffdfffffh and ff980000h ? ff9fffffh. 0 = disable, 1 = enable 26 1b r/w d0?d7 enable (ed0): enables decoding of bios range ffd00000h ? ffd7ffffh and ff900000h ? ff97ffffh. 0 = disable 1 = enable 25 1b r/w c8?cf enable (ec8): enables decoding of bios range ffc80000h ? ffcfffffh and ff880000h ? ff8fffffh. 0 = disable 1 = enable 24 1b r/w c0?c7 enable (ec0): enables decoding of bios range ffc00000h ? ffc7ffffh and ff800000h ? ff87ffffh. 0 = disable 1 = enable 23:00 000000h ro reserved
lpc interface (d31:f0) 364 datasheet 17.5.3 bios_ctl?bios control register offset: d8h?dbh attribute: ro, r/w default value: 00000100h size: 32 bits 17.6 root complex regist er block configuration 17.6.1 rcba?root complex base address register offset: f0h?f3h attribute: ro, r/w default value: 00000000h size: 32 bits bit default and access description 31:9 0 ro reserved 8 1 r/w prefetch enable (pfe) 0 = disable. 1 = enable bios prefetching. an access to bios causes a 64-byte fetch of the line starting at th at region. subsequent accesses within that region result in data being re turned from the prefetch buffer. note: the prefetch buffer is invalidated when this bit is cleared, or a bios access occurs to a different li ne than what is currently in the buffer. 7:2 000000b ro reserved 1 0 r/wlo lock enable (le): when set, setting the wp bit will cause smis. when cleared, setting the wp bit will not cause smis. once set, this bit can only be cleared by a reset#. 0 = setting the bioswe will not cause smis. 1 = enables setting the bi oswe bit to cause smis. once set, this bit can only be cleared by a reset# 0 0 r/w write protect (wp): when set, access to bios is enabled for both read and write cycles. when cleared, only read cycles are permitted to bios. when written from a 0 to a 1 and le is also set, an smi# is generated. this ensures that only smm code can update bios. bit default and access description 31:14 0 r/w base address (ba): base address for the root complex register block decode range. this address is aligned on a 16 kb boundary. 13:1 0 ro reserved 0 0 r/w enable (en) 1 = enables the range specified in rcba.ba to be claimed as the rcrb.
datasheet 365 acpi functions 18 acpi functions acpi (advanced configuration and power interf ace) is an open industry specification co-developed by compaq*, intel, microsof t*, phoenix*, and tosh iba*. it establishes industry-standard interfaces for os-directe d configuration and power management on laptops, desktops, and servers. the intel? sch includes several internal acpi devices: ?two timers ? an 8254 timer ? precision event timer ? real time clock ? various interrupt controllers ? two, 8259 programmable interrupt controllers ? an advanced programmable interrupt controller (ioxapic) ? a serial interrupt controller ? smbus controller 18.1 8254 timer 18.1.1 overview the 8254 timer is clocked by a 14.31818-mhz clock and contains three counters which have fixed uses. ? counter 0: system timer ? counter 1: refresh request ? counter 2: speaker tone 18.1.1.1 counter 0, system timer this counter functions as the system timer by controlling the state of irq0 and is typically programmed for mode 3 operation. the counter produces a square wave with a period equal to the product of the counter period (838 ns) and the initial count value. the counter loads the initial count value one counter period after software writes the count value to the counter i/o address. the counter initially asserts irq0 and decrements the count value by two each counter period. the counter negates irq0 when the count value reaches 0. it then reloads the initial count value and again decrements the initial count value by tw o each counter period. the counter then asserts irq0 when the count value reaches 0, reloads the initial count value, and repeats the cycle, alternately asserting and negating irq0. 18.1.1.2 counter 1, refresh request signal this counter is typically programmed for mo de 2 operation and impacts the period of the ref_toggle bit in port 61. programming the counter to anything other than mode 2 will result in undefined behavior for the ref_toggle bit.
acpi functions 366 datasheet 18.1.1.3 counter 2, speaker tone this counter typically programmed for mode 3 operation. 18.1.2 timer programming the counter/timers are programmed in the following fashion: 1. write a control word to select a counter 2. write an initial count for that counter. 3. load the least and/or most significant byte s (as required by control word bits 5, 4) of the 16-bit counter. 4. repeat with other counters only two conventions need to be observed when programming the counters. first, for each counter, the control word must be written before the initial count is written. second, the initial count must follow the count format specified in the control word (least significant byte only, most significant byte only, or least significant byte and then most significant byte). a new initial count may be written to a counter at any time without affecting the counter's programmed mode. counting will be affected as described in the mode definitions. the new count must follow the programmed count format. if a counter is programmed to read/write 2-byte counts, the following precaution applies: a program must not transfer contro l between writing the first and second byte to another routine which also writes into that same counter. otherwise, the counter will be loaded with an incorrect count. the control word register at port 43h controls the operation of all three counters. several commands are available: ? control word command: specifies which counter to read or write, the operating mode, and the count format (binary or bcd). ? counter latch command: latches the current count so that it can be read by the system. the countdown process continues. ? read back command: reads the count value, programmed mode, the current state of the out pins, and the state of the null count flag of the selected counter. table 54. counter operating modes mode function description 0 out signal on end of count (=0) output is 0. when count goes to 0, output goes to 1 and stays at 1 until counter is reprogrammed. 1 hardware retriggerable one- shot output is 0. when count goes to 0, output goes to 1 for one clock time. 2 rate generator (divide by n counter) output is 1. output goes to 0 for one clock time, then back to 1 and counter is reloaded. 3square wave output output is 1. output goes to 0 when counter rolls over, and counter is reloaded. output goes to 1 when counter rolls over, and counter is reloaded, etc. 4 software triggered strobe output is 1. output goes to 0 when count expires for one clock time. 5 hardware triggered strobe output is 1. output goes to 0 when count expires for one clock time.
datasheet 367 acpi functions 18.1.3 reading from the interval timer it is often desirable to read the value of a counter without disturbing the count in progress. there are three methods for reading the counters: a simple read operation, counter latch command, and the read-back command. each is explained below. with the simple read and counter latch co mmand methods, the count must be read according to the programmed format; specifically, if the counter is programmed for 2-byte counts, two bytes must be read. th e two bytes do not have to be read in sequence (one right after the other). read, write, or programming operations for other counters can be inserted between them. 18.1.3.1 simple read the first method is to perform a simple read operation. the counter is selected through port 40h (counter 0), 41h (counter 1), or 42h (counter 2). note: performing a direct read from the counter will not return a determinate value, because the counting process is asynchronous to read operations. however, in the case of counter 2, the count can be stopped by writing to nsc.tc2e. 18.1.3.2 counter latch command the counter latch command, written to port 43h, latches the count of a specific counter at the time the command is received. this command is used to ensure that the count read from the counter is accurate, pa rticularly when reading a 2-byte count. the count value is then read from each counter's count register as was programmed by the control register. the count is held in the latch until it is re ad or the counter is reprogrammed. the count is then unlatched. this allows reading the contents of the counters on the fly without affecting counting in progress. multiple co unter latch commands may be used to latch more than one counter. counter latch comman ds do not effect the programmed mode of the counter in any way. if a counter is latched and then, some time later, latched again before the count is read, the second counter latch command is ignored. the count read will be the count at the time the first counter latch command was issued. 18.1.3.3 read back command the read back command, written to port 43h, latches the count value, programmed mode, and current states of the out pin and null count flag of the selected counter or counters. the value of the counter and its status may then be read by i/o access to the counter address. the read back command may be used to la tch multiple counter outputs at one time. this single command is functionally equivalent to several counter latch commands, one for each counter latched. each counter's la tched count is held until it is read or reprogrammed. once read, a counter is unlatched. the other counters remain latched until they are read. if multiple count read back commands are issued to the same counter without reading the count, all but the first are ignored. the read back command may additionally be used to latch status information of selected counters. the status of a counter is accessed by a read from that counter's i/o port address. if multiple counter status latch operations are performed without reading the status, all but the first are ignored.
acpi functions 368 datasheet both count and status of the selected counters may be latched simultaneously. this is functionally the same as issuing two consec utive, separate read back commands. if multiple count and/or status read back commands are issued to the same counters without any intervening reads, all but the first are ignored. if both count and status of a counter are latched, the first read operation from that counter will return the latched status, regardless of which was latched first. the next one or two reads, depending on whether th e counter is programmed for one or two type counts, return the latched count. su bsequent reads return unlatched count. 18.1.4 i/o registers all registers are powered by the core power well. table 55. i/o register map port n register name/function default value type 40h counter 0 interval time st atus byte format 0uuuuuuub ro 41h counter 1 interval time st atus byte format 0uuuuuuub ro 42h counter 2 interval time st atus byte format 0uuuuuuub ro 43h timer control word register uuh wo 50h counter 0 counter acce ss port register uuh r/w 51h counter 1 counter acce ss port register uuh r/w 52h counter 2 counter acce ss port register uuh r/w
datasheet 369 acpi functions 18.1.4.1 counter [0..2] interval ti mer status byte format register offset/port: 40h, 41h, 42h attribute: ro default value: 0uuuuuuub size: 8 bits each counter's status byte can be read follo wing a read back command. if latch status is chosen (bit 4=0, read back command) as a read back option for a given counter, the next read from the counter's counter access ports register (40h for counter 0, 41h for counter 1, and 42h for counter 2) returns the status byte. bit default and access description 7 0 ro counter out pin state: 0 = out pin of the counter is 0 1 = out pin of the counter is 1 6 u ro count register status: this bit indicates when the last count written to the count register (cr) has been loaded into the counting element (ce). the exact time this happens depends on the counter mode, but until the count is loaded into the counting element (ce), the count value will be incorrect. 0 = count has been transferred from cr to ce and is available for reading 1 = null count. count has not been tr ansferred from cr to ce and is not yet available for reading 5:4 uu ro read/write selection status: these reflect the read/write selection made through bits[5:4] of the control register. th e binary codes returned during the status read match the codes used to program the counter read/ write selection. 00 = counter latch command 01 = read/write least significant byte (lsb) 10 = read/write most significant byte (msb) 11 = read/write lsb then msb 3:1 uuu ro mode selection status: these bits return the counter mode programming. the binary code returned matche s the code used to program the counter mode, as list ed under the bit function above. 000 = out signal on end of count (=0) 001 = hardware retriggerable one-shot x10 = rate generator (divide by n counter) x11 = square wave output 100 4 software triggered strobe 101 5 hardware triggered strobe 0 u ro countdown type status: this bit reflects the current countdown type. 0 = binary countdown 1 = binary coded decimal (bcd) countdown
acpi functions 370 datasheet 18.1.4.2 tcw?timer control word register offset/port: 43h attribute: wo default value: uuh size: 8 bits this register is programmed prior to any counter being accessed to specify counter modes. following reset, the control words for each register are undefined and each counter output is 0. each timer must be programmed to bring it into a known state. there are two special commands that can be issued to the counters through this register, the read back command and the counter latch command. when these commands are chosen, several bits within this register are redefined. these register formats are described in the following sections. bit default and access description 7:6 uu wo counter select (cs): the counter selection bits select the counter that the control word acts upon as show n below. the read back command is selected when bits[7:6] are both 1. 00 = counter 0 select 01 = counter 1 select 10 = counter 2 select 11 = read back command 5:4 uu wo read/write select rws): these bits are the read/write control bits. the actual counter programming is done through the counter port (40h for counter 0, 41h for counter 1, and 42h for counter 2). 00 = counter latch command 01 = read/write least significant byte (lsb) 10 = read/write most significant byte (msb) 11 = read/write lsb then msb 3:1 uuu wo counter mode selection (cms): these bits select one of six possible modes of operation for the selected counter. 000 = out signal on end of count (=0) 001 = hardware retriggerable one-shot x10 = rate generator (divide by n counter) x11 = square wave output 100 = software triggered strobe 101 = hardware triggered strobe 0 u wo binary/bcd countdown select (bcs): 0 = binary countdown is used. the largest possible binary count is 216 1 = binary coded decimal (bcd) count is used. the largest possible bcd count is 104
datasheet 371 acpi functions 18.1.4.3 tcw?timer control word register (read back command) the read back command is used to determine the count value, programmed mode, and current states of the out pin and null count flag of the selected counter or counters. status and/or count may be latched in any or all of the counters by selecting the counter during the register write. the count and status remain latched until read, and further latch commands are ignored until the count is read. both count and status of the selected counters may be latched simultaneously by setting both bit 5 and bit 4 to 0. if both ar e latched, the first read operation from that counter returns the latched status. the next one or two reads, (d epending on whether the counter is programmed for 1- or 2-byte counts) return a latched count. subsequent reads return an unlatched count. bit default and access new description 7:6 read back command: must be ?11? to select the read back command 5 latch count of selected counters: 0 = current count value of the sele cted counters will be latched 1 = current count will not be latched 4 latch status of selected counters: 0 = status of the selected counters will be latched 1 = status will not be latched 3 counter 2 select (c2s): when set to 1, counte r 2 count and/or status will be latched. 2 counter 1 select (c1s): when set to 1, counte r 1 count and/or status will be latched. 1 counter 0 select (c0s): when set to 1, counte r 0 count and/or status will be latched. 0 reserved
acpi functions 372 datasheet 18.1.4.4 tcw?timer control word re gister (counter latch command) this latches the current count value and is used to ensure the count read from the counter is accurate. the count value is then read from each counter's count register through the counter ports access ports register (40h for counter 0, 41h for counter 1, and 42h for counter 2). the count must be read according to the programmed format, i.e., if the counter is programmed for 2-byte counts, two bytes must be read. it is not necessary to read the two bytes in sequence. that is, the two bytes do not have to be read one right after the other (read, writ e, or programming operations for other counters may be inserted between the reads). if a counter is latched once and then latched again before the count is read, th e second counter latch command is ignored. 18.1.4.5 counter access ports register offset/port: 50h, 51h, 52h attribute: r/w default value: uuh size: 8 bits bit default and access description 7:6 counter selection: these bits select the counte r for latching. if ?11? is written, then the write is interpreted as a read back command. 00 = counter 0 01 = counter 1 10 = counter 2 5:4 counter latch command: write ?00? to select the counter latch command. 3:0 reserved. must be 0. bit default and access description 7:0 undefined r/w counter port: each counter port a ddress is used to program the 16-bit count register. the order of programm ing, either lsb only, msb only, or lsb then msb, is defined with the in terval counter control register at port 43h. the counter port is also used to read the current count from the count register, and return the st atus of the counter programming following a read back command.
datasheet 373 acpi functions 18.2 high precision event timer the high precision event timer (hpet) function provides a set of timers that to be used by the operating system for timing events. one timer block is implemented, containing one counter and three timers. 18.2.1 functional overview 18.2.1.1 non-periodic mode?all timers this mode can be thought of as creating a one-shot. when a timer is set up for non- periodic mode, it generates an interrupt when the value in the main counter matches the value in the timer?s comparator register . as timers 1 and 2 are 32-bit, they will generate another interrupt when the main counter wraps. t0cv cannot be programmed reliably by a sing le 64-bit write in a 32-bit environment, unless only the periodic rate is being chan ged. if t0cv needs to be reinitialized, the following algorithm is performed: 1. set t0cc.tvs 2. set the lower 32 bits of t0cv 3. set t0cc.tvs 4. set the upper 32 bits of t0cv every timer is required to support the non-periodic mode of operation. 18.2.1.2 periodic mode?timer 0 only when set up for periodic mo de, when the main counter value matches the value in t0cv, an interrupt is generated (if enabled). hardware then increases t0cv by the last value written to t0cv. during run-time, t0cv can be read to find out when the next periodic interrupt will be generated. software is expected to remember the last value written to t0cv. example: if the value written to t0cv is 00000123h, then ? an interrupt will be generated when the main counter reaches 00000123h ? t0cv will then be adjusted to 00000246h ? another interrupt will be generated when the main counter reaches 00000246h ? t0cv will then be adjusted to 00000369h ? when the incremented value is greater th an the maximum value possible for tncv, the value will wrap around through 0. for example, if the current value in a 32-bit timer is ffff0000h and the last value written to this register is 20000, then after the next interrupt the value will change to 00010000h. if software wants to change the periodic rate, it writes a new value to t0cv. when the timer?s comparator matches, the new value is added to derive the next matching point. if software resets the main counter, the value in the comparator?s value register must also be reset by setting t0cc.tvs. to avoid race conditions, this should be done with the main counter halted. the follo wing usage model is expected: 1. software clears gc.en to prevent any interrupts 2. software clears the main counter by writing a value of 00h to it 3. software sets t0cc.tvs 4. software writes the new value in t0cv 5. software sets gc.en to enable interrupts.
acpi functions 374 datasheet 18.2.1.3 interrupts if each timer has a unique interrupt and the timer has been configured for edge- triggered mode, then there are no specific steps required. if configured to level- triggered mode, then its interrupt must be cl eared by software by writing a 1 back to the bit position for the interrupt to be cleared. interrupts associated with the various timers have several interrupt mapping options. software should mask gc.lre when reprog ramming hpet interrupt routing to avoid spurious interrupts. 18.2.1.3.1 mapping option #1: legacy option (gc.lre set) setting the gc.lre bit high forces the following mapping: 18.2.1.3.2 mapping option #2: st andard option (gc.lre cleared) each timer has its own routing control. the interrupts can be routed to various interrupts in the i/o apic. tnc.irc indica tes which interrupts are valid options for routing. if a timer is set for edge-triggered mode, the timers should not be shared with any other interrupts. 18.2.2 registers the hpet register space is memory mapped to a 1 kb block starting at address fed00000h. all registers are in the core well and reset by reset#. accesses that cross register boundaries result in undefined behavior. table 56. legacy time r interrupt mapping timer 8259 mapping apic mapping comment 0 irq0 irq2 the 8254 timer will not cause any interrupts. 1 irq8 irq8 rtc will not cause any interrupts. 2t2c.irq t2c.irc offset/ port mnemonic register default access 000h?007h gcid general capabilities and id 0429b17f_8086a201h ro 010h?017h gcfg general configuration 0000000000000000h ro, r/w 020h?027h gis general interrupt status 0000000000000000h ro, r/wc 0f0h?0f7h mcv main counter value 0000000000000000h r/w 100h?107h t0c timer 0 configuration and capabilities see description ro, r/w 108h?10fh t0cv timer 0 comparator value 0000000000000000h ro, r/w 120h?127h t1c timer 1 configuration and capabilities see description ro, r/w 128h?12fh t1cv timer 1 comparator value 0000000000000000h ro, r/w 140h?147h t2c timer 2 configuration and capabilities see description ro, r/w 148h?14fh t2cv timer 2 comparator value 0000000000000000h ro, r/w
datasheet 375 acpi functions 18.2.2.1 gcid?general capabilities and id register offset/port: 000?007h attribute: ro default value: 0429b17f_8086a201h size: 64 bits 18.2.2.2 gc?general configuration register offset/port: 010?017h attribute: ro, r/w default value: 00000000h size: 64 bits bit default and access description 63:32 0429b17fh ro counter tick period (ctp): this field indicates a period of 69.841279 ns, (14.31818-mhz clock period). 31:16 8086h ro vendor id (vid): value of 8086h indicates intel corporation. 15 1 ro legacy rout capable (lrc): this bit indicates support for legacy interrupt rout. 14 0 ro reserved 13 1 ro counter size (cs): this bit is set to indicate that the main counter is 64 bits wide. 12:8 02h ro number of timers (nt) : indicates that 3 timers are supported. 7:0 01h ro revision id (rid) : indicates that revision 1.0 of the specification is implemented. bit default and access description 63:02 0 ro reserved 1 0 r/w legacy rout enable (lre): when set, interrupts will be routed as follows: ? timer 0 will be routed to irq0 in 8259 or irq2 in the i/o apic ? timer 1 will be routed to irq8 in 8259 and i/o apic ? timer 2 will be routed as per the routing in t2c when set, the tnc.ir will have no impact for timers 0 and 1. 0 0 r/w overall enable (en): when set, the timers ca n generate interrupts. when cleared, the main co unter will halt and no in terrupts will be caused by any timer. for level-triggered interrupts, if an interrupt is pending when this bit is cleared, the gis.tx will not be cleared.
acpi functions 376 datasheet 18.2.2.3 gis?general interrupt status register offset/port: 020?027h attribute: ro, r/wc default value: 0s size: 64 bits 18.2.2.4 mcv?main counter value register offset/port: 0f0?0f7h attribute: r/w default value: 0s size: 64 bits bit default and access description 63:03 0 ro reserved 2 0 r/wc timer 2 status (t2): same functionality as t0, for timer 2. 1 0 r/wc timer 1 status (t1): same functionality as t0, for timer 1. 0 0 r/wc timer 0 status (t0): in edge triggered mode, this bit alwa ys reads as 0. in level triggered mode, this bit is set when an inte rrupt is active. bit default and access description 63:0 0 r/w counter value (cv): reads return the current value of the counter. writes load the new value to the coun ter. timers 1 and 2 return 0 for the upper 32-bits of this register.
datasheet 377 acpi functions 18.2.2.5 t[0:2]cc?timer n config uration and capabilities register offset/port: 100h, 120h, 140h attribute: ro, r/w default value: see description size: 64 bits bit default and access description 63:32 see description ro interrupt rout capability (irc): this field indicates i/oxapic interrupts the timer can use: ? timer 0,1: 00f00000h. indicates support for irq20, 21, 22, 23 ? timer 2: 00f00800h. indicates support for irq11, 20, 21, 22, and 23 31:16 0 ro reserved 15 ro fsb interrupt delivery (fid): not supported 14 0 ro fsb enable (fe): not supported, since fid is not supported. 13:9 0 r/w interrupt rout (ir): this field indicates the ro uting for the interrupt to the ioxapic. if the value is not suppo rted by this particular timer, the value read back will not match what is written. if gc.l re is set, then timers 0 and 1 have a fixed routin g, and this field has no effect. 8 0 ro/r/w timer 32-bit mode (t32m): when set, this bit forces a 64-bit timer to behave as a 32-bit timer. for timer 0, this bit will be read/write and default to 0. for timers 1 and 2, this bit is read only 0. 7 0 ro reserved 6 0 ro/r/w timer value set (tvs): this bit will return 0 when read. writes will only have an effect for timer 0 if it is set to periodic mode. writes will have no effect for timers 1 and 2. 5 0/1 ro timer size (ts): 1 = 64-bit, 0 = 32-bit. set for timer 0. cleared for timers 1 and 2. 4 0/1 ro periodic interrupt capable (pic): when set, hardware supports a periodic mode for this timer?s interrup t. this bit is se t for timer 0, and cleared for timers 1 and 2. 3 0 ro/r/w timer type (typ): if pic is set, this bit is read/write, and can be used to enable the timer to generate a periodic interrupt. this bit is r/w for timer 0, and ro for timers 1 and 2. 2 0 r/w interrupt enable (ie): when set, enables the timer to cause an interrupt when it times out. when cl eared, the timer co unt and generates status bits, but will not cause an interrupt. 1 0 r/w timer interrupt type (it): when cleared, interrupt is edge triggered. when set, interrupt is level triggered and will be held active until it is cleared by writing 1 to gis.tn. if another interrupt oc curs before the interrupt is cleared, the interrupt remains active. 0 0 ro reserved
acpi functions 378 datasheet 18.2.2.6 t[0:2]cv?timer n comparator value register offset/port: 108h, 128h, 148h attribute: ro, r/w default value: 1s size: 64 bits reads to this register return the current va lue of the comparator. the default value for each timer is all 1s for the bits that are implemented. timer 0 is 64-bits wide. timers 1 and 2 are 32-bits wide. bit description 63:0 timer compare value ? r/w. reads to this register return the current value of the comparator timers 0, 1, or 2 are config ured to non-periodic mode: writes to this register load the value against which the main counter should be compared for this timer. ? when the main counter equals the valu e last written to this register, the corresponding interrupt can be generated (if so enabled). ? the value in this register does no t change based on the interrupt being generated. timer 0 is configured to periodic mode: ? when the main counter equals the valu e last written to this register, the corresponding interrupt can be generated (if so enabled). ? after the main counter equals the value in this register, the value in this register is increased by the value last written to the register. as each periodic interrupt oc curs, the value in this register will increment. when the incremented value is greater than the maximum value possible for this register (ffffffffh for a 32-bit timer or ffffffffffffffffh for a 64-bit timer), the value will wrap around through 0. for example, if the current value in a 32-bit timer is ffff0000h and the last value writte n to this register is 20000, then after the next interrupt the valu e will change to 00010000h default value for each timer is all 1s for th e bits that are implemented. for example, a 32-bit timer has a default value of 00000000ffffffffh. a 64-bit timer has a default value of ffffffffffffffffh.
datasheet 379 acpi functions 18.3 8259 interrupt controller 18.3.1 overview the isa-compatible interrupt controller (825 9) incorporates the functionality of two 8259 interrupt controllers: a master and a slave. the following table shows how the cores are connected: the slave controller is cascaded onto the master controller through master controller interrupt input 2. interrupts can individually be programmed to be edge or level, except for irq0, irq2, irq8#. active-low interrupt sources, such as the pirq#s, are internally inverted before being sent to th e 8259. in the following descriptions of the 8259s, the interrupt levels are in reference to the signals at the internal interface of the 8259s, after the required inversions have occurred. therefore, the term ?high? indicates ?active?, which means ?low? on an originating pirq#. table 57. master 8259 input mapping 8259 input connected pin/function 0 internal timer/counter 0 output or multimedia timer #0 1 irq1 through serirq 2 slave controller intr output 3 irq3 through serirq, pirqx 4 irq4 through serirq, pirqx 5 irq5 through serirq, pirqx 6 irq6 through serirq, pirqx 7 irq7 through serirq, pirqx table 58. slave 8259 input mapping 8259 input connected pin/function 0 inverted irq8# from internal rtc or hpet 1 irq9 through serirq, sci, or pirqx 2 irq10 through serirq, sci, or pirqx 3 irq11 through serirq, sci, or pirqx 4 irq12 through serirq, sci, or pirqx 5pirqx 6 ideirq, serirq, pirqx 7pirqx
acpi functions 380 datasheet 18.3.2 interrupt handling 18.3.2.1 generating the 8259 interrupt sequence involves three bits, from the irr, isr, and imr, for each interrupt level. these bits are used to de termine the interrupt vector returned, and status of any other pending interrupts. these bits are defined as follows: ? interrupt request register (irr): set on a low to high transition of the interrupt line in edge mode, and by an active high level in level mode. ? interrupt service register (isr): set, and the corresponding irr bit cleared, when an interrupt acknowledge cycle is seen, and the vector returned is for that interrupt. ? interrupt mask register (imr): determines whether an interrupt is masked. masked interrupts will not generate intr. 18.3.2.2 acknowledging the cpu generates an interrupt acknowledge cy cle which is translated into an interrupt acknowledge special cycle to the intel? sch. the 8259 translates this cycle into two internal inta# pulses expected by the 8259 cores. the 8259 uses the first internal inta# pulse to freeze the state of the interru pts for priority resolution. on the second inta# pulse, the master or slave will sends the interrupt vector to the processor with the acknowledged interrupt code. this co de is based upon bits [7:3] of the corresponding icw2 register, combined with th ree bits representing the interrupt within that controller. table 59. content of interrupt vector byte master,slave interrupt bits [7:3] bits [2:0] irq7,15 icw2[7:3] 111 irq6,14 110 irq5,13 101 irq4,12 100 irq3,11 011 irq2,10 010 irq1,9 001 irq0,8 000
datasheet 381 acpi functions 18.3.2.3 hardware/softw are interrupt sequence 1. one or more of the interrupt request lines (irqs) are raised high in edge mode, or seen high in level mode, setting the corresponding irr bit. 2. the 8259 sends intr active (high) to the cpu if an asserted interrupt is not masked. 3. the cpu acknowledges the intr and re sponds with an interrupt acknowledge cycle. 4. upon observing the special cycle the intel? sch converts it into the two cycles that the internal 8259 pair can respond to. each cycle appears as an interrupt acknowledge pulse on the internal inta# pin of the cascaded interrupt controllers. 5. upon receiving the first internally genera ted inta# pulse, the highest priority isr bit is set and the corresponding irr bit is reset. on the trailing edge of the first pulse, a slave identification code is broa dcast internally by the master 8259 to the slave 8259. the slave controller uses these bits to determine if it must respond with an interrupt vector during the second inta# pulse. 6. upon receiving the second internally ge nerated inta# pulse, the 8259 returns the interrupt vector. if no interrupt request is present, the 8259 will return vector 7 from the master controller. 7. this completes the interrupt cycle. in aeoi mode the isr bit is reset at the end of the second inta# pulse. otherwise, the isr bit remains set until an appropriate eoi command is issued at the end of the interrupt subroutine. 18.3.3 initialization command words (icw) before operation can begin, each 8259 must be initialized. in the intel? sch this is a four byte sequence to icw1, icw2, ic w3, and icw4. the address for each 8259 initialization command word is a fixed locati on in the i/o memory space: 20h for the master controller, and a0h for the slave controller. 18.3.3.1 icw1 a write to the master or slave controller base address with data bit 4 equal to 1 is interpreted as a write to icw1. upon sensin g this write, intel? sch 8259 expects three more byte writes to 21h for the master controller, or a1h for the slave controller to complete the icw sequence. 1. a write to icw1 starts the initializati on sequence during which the following automatically occur: a. following initialization, an interrupt request (irq) input must make a low-to- high transition to generate an interrupt b. the interrupt mask register is cleared c. irq7 input is assigned priority 7 d. the slave mode address is set to 7 e. special mask mode is cleared and status read is set to irr. 18.3.3.2 icw2 the second write in the sequence, icw2, is programmed to provide bits [7:3] of the interrupt vector that will be released during an interrupt acknowledge. a different base is selected for each interrupt controller.
acpi functions 382 datasheet 18.3.3.3 icw3 the third write in the sequence, icw3, has a different meaning for each controller. ? for the master controller, icw3 is used to indicate which irq input line is used to cascade the slave controller. within the intel? sch, irq2 is used. therefore, bit 2 of icw3 on the master controller is set to a 1, and the other bits are set to 0s. ? for the slave controller, icw3 is the sl ave identification code used during an interrupt acknowledge cycle. on interrupt acknowledge cycles, the master controller broadcasts a code to the slave controller if the cascaded interrupt won arbitration on the master controller. the slave controller compares this identification code to the value stored in its icw3, and if it matches, the slave controller assumes responsibility for broadcasting the interrupt vector. 18.3.3.4 icw4 the final write in the sequence, icw4, must be programmed both controllers. at the very least, bit 0 must be set to a 1 to indi cate that the controllers are operating in an intel architecture-based system. 18.3.4 operation command words (ocw) these command words reprogram the interrupt controller to operate in various interrupt modes. ? ocw1 masks and unmasks interrupt lines ? ocw2 controls the rotation of interrupt priorities when in rotating priority mode, and controls the eoi function ? ocw3 is sets up isr/irr reads, enables/ disables the special mask mode smm, and enables/ disables polled interrupt mode. 18.3.5 modes of operation 18.3.5.1 fully nested mode in this mode, interrupt requests are ordered in priority from 0 through 7, with 0 being the highest. when an interrupt is acknow ledged, the highest priority request is determined and its vector placed on the bus. additionally, the isr for the interrupt is set. this isr bit remains set until: the cpu issues an eoi command immediately before returning from the service routine; or if in aeoi mode, on the trailing edge of the second inta#. while the isr bit is set, a ll further interrupts of the same or lower priority are inhibited, while higher levels will generate another interrupt. interrupt priorities can be change d in the rotating priority mode. 18.3.5.2 special fully nested mode this mode will be used in the case of a system where cascading is used, and the priority has to be conserved within each slave. in this case, the special fully nested mode is programmed to the master controller. this mode is similar to the fully nested mode with the following exceptions: ? when an interrupt request from a certain slav e is in service, this slave is not locked out from the master's priority logic and further interrupt requests from higher priority interrupts within the slave will be recognized by the master and will initiate interrupts to the processor. in the normal nested mode, a slave is masked out when its request is in service. ? when exiting the interrupt service routine, software has to check whether the interrupt serviced was the only one from that slave. this is done by sending a non- specific eoi command to the slave and then reading its isr. if it is 0, a non- specific eoi can also be sent to the master.
datasheet 383 acpi functions 18.3.5.3 automatic rotation mo de (equal priority devices) in some applications, there are a number of interrupting devices of equal priority. automatic rotation mode provides for a sequential 8-way rotation. in this mode, a device receives the lowest priority after being serviced. in the worst case, a device requesting an interrupt will have to wait unt il each of seven other devices are serviced at most once. there are two ways to accomplish automatic rotation using ocw2; the rotation on non-specific eoi command (r=1, sl=0, eo i=1) and the rotate in automatic eoi mode which is set by (r=1, sl=0, eoi=0). 18.3.5.4 specific rotation mode (specific priority) software can change interrupt priorities by programming the bottom priority. for example, if irq5 is programmed as the botto m priority device, then irq6 will be the highest priority device. the set priority comma nd is issued in ocw2 to accomplish this, where: r=1, sl=1, and lo-l2 is the binary priority level code of the bottom priority device. in this mode, internal status is updated by software control during ocw2. however, it is independent of the eoi command. priority changes can be executed during an eoi command by using the rotate on specific eoi command in ocw2 (r=1, sl=1, eoi=1 and lo-l2=irq level to receive bottom priority. 18.3.5.5 poll mode poll mode can be used to conserve space in the interrupt vector table. multiple interrupts that can be serviced by one inte rrupt service routine?do not need separate vectors if the service routine uses the poll command. polled mode can also be used to expand the number of interrupts. the po lling interrupt service routine can call the appropriate service routine, instead of prov iding the interrupt vectors in the vector table. in this mode, the intr output is not used and the microprocessor internal interrupt enable flip-flop is reset, disabling its interrupt input. service to devices is achieved by software using a poll command. the poll command is issued by setting p=1 in ocw3. the 8259 treats its next i/o read as an interrupt acknowledge, sets the appr opriate isr bit if there is a request, and reads the priority level. interrupts are frozen from the ocw3 write to the i/o read. the byte returned during the i/o read will contain a 1 in bit 7 if there is an interrupt, and the binary code of the highes t priority level in bits 2:0. 18.3.5.6 edge and level triggered mode in isa systems this mode is programmed usin g bit 3 in icw1, which sets level or edge for the entire controller. in the intel? sch, this bit is disabled and a new register for edge and level triggered mode selection, per interrupt input, is included. this is the edge/level control registers elcr1 and elcr2. if an elcr bit is 0, an interrupt request will be recognized by a low to high transition on the corresponding irq input. the irq input can remain high without generating another interrupt. if an elcr bit is 1, an in terrupt request will be recognized by a high level on the corresponding irq input and ther e is no need for an edge detection. the interrupt request must be removed before the eoi command is issued to prevent a second interrupt from occurring. in both the edge and level triggered modes, the irq inputs must remain active until after the falling edge of the first internal in ta#. if the irq input goes inactive before this time, a default irq7 vector will be returned.
acpi functions 384 datasheet 18.3.6 end of in terrupt (eoi) 18.3.6.1 normal eoi in normal eoi, software writes an eoi command before leaving the interrupt service routine to mark the interrupt as complete d. there are two forms of eoi commands: specific and non- specific. when a non-specific eoi command is issued, the 8259 will clear the highest isr bit of those that are set to 1. a non-specific eoi is the normal mode of operation of the 8259 within the in tel? sch, as the interrupt being serviced currently is the interrupt entered with th e interrupt acknowledge. when the 8259 is operated in modes which preserve the fully nested structure, software can determine which isr bit to clear by issuing a specific eoi. an isr bit that is masked will not be cleared by a non-specific eoi if the 8259 is in the special mask mode. an eoi command must be issued for both the master and slave controller. 18.3.6.2 automatic eoi in this mode, the 8259 will automatically pe rform a non-specific eoi operation at the trailing edge of the last interrupt acknowle dge pulse. from a system standpoint, this mode should be used only when a nested mu lti-level interrupt structure is not required within a single 8259. the aeoi mode can only be used in the master controller. 18.3.7 masking interrupts 18.3.7.1 masking on an indi vidual interrupt request each interrupt request can be masked individually by the interrupt mask register (imr). this register is programmed through ocw1. each bit in the imr masks one interrupt channel. masking irq2 on the ma ster controller will mask all requests for service from the slave controller. 18.3.7.2 special mask mode some applications may require an interrupt service routine to dynamically alter the system priority structure during its executio n under software control. for example, the routine may wish to inhibit lower priority requests for a portion of its execution but enable some of them for another portion. the special mask mode enables all interrupts not masked by a bit set in the mask register. normally, when an interrupt service routine acknowledges an interrupt without issuing an eoi to clear the isr bit, the interrupt controller inhibits all lower priority requests. in the special mask mode , any interrupts may be selectively enabled by loading the mask register with the appropriate pattern. the special mask mode is set by ocw3.s smm and ocw3.smm set, and cleared when ocw3.ssmm and ocw3.smm are cleared.
datasheet 385 acpi functions 18.3.8 steering of pci interrupts the intel? sch can be programmed to allow pirq[a:h]# to be internally routed to interrupts 3-7, 9-12, 14 or 15, through the parc, pbrc, pcrc, pdrc, perc, pfrc, pgrc, and phrc registers in the chipset co nfiguration section. one or more pirqx# lines can be routed to the same irqx input. the pirqx# lines are defined as active low, level sensitive. when pirqx# is routed to specified irq line, software must change the corresponding elcr1 or elcr2 register to level sensitive mode. the intel? sch will inte rnally invert the pirqx# line to send an active high level to the 8259. when a pci interrupt is routed onto the 8259, the selected irq can no longer be used by an isa device. 18.3.9 i/o registers the interrupt controller registers are locate d at 20h and 21h for the master controller (irq0?7), and at a0h and a1h for the slave controller (irq8?13). these registers have multiple functions, depending upon the data written to them. ta b l e 6 0 provides a description of the different register possibilities for each address. table 60. 8259 i/o register mapping port register name/function aliases 20h micw1 master init. cmd word 1 24h, 28h, 2ch, 30h, 34h, 38h, 3ch mocw2 master op ctrl word 2 mocw3 master op ctrl word 3 21h micw2 master init. cmd word 2 25h, 29h, 2dh, 31h, 35h, 39h, 3dh micw3 master init. cmd word 3 micw4 master init. cmd word 4 mocw1 master op ctrl word 1 a0h sicw1 slave init. cmd word 1 a4h, a8h, ach, b0h, b4h, b8h, bch socw2 slave op ctrl word 2 socw3 slave op ctrl word 3 a1h sicw2 slave init. cmd word 2 a5h, a9h, adh, b1h, b5h, b9h, bdh sicw3 slave init. cmd word 3 sicw4 slave init. cmd word 4 socw1 slave op ctrl word 1 4d0h elcr1 master edge /level triggered - 4d1h e:cr2 slave edge/level triggered -
acpi functions 386 datasheet 18.3.9.1 micw1/sicw1?master/slave initialization command word 1 register offset/port: master: 20h attribute: wo slave: a0h default value: uuh size: 8 bits initialization command word 1 starts the in terrupt controller initialization sequence, during which the following occurs: ? the interrupt mask register is cleared ? irq7 input is assigned priority 7 ? the slave mode address is set to 7 ? special mask mode is cleared and status read is set to irr. once this write occurs, the controller expects writes to icw2, icw3, and icw4 to complete the initialization sequence. bit default and access description 7:5 undefined wo these bits are mcs-85 specific, and not needed. should be programmed to ?000?. 4 undefined wo icw/ocw select: this bit must be a 1 to select icw1 and enable the icw2, icw3, and icw4 sequence. 3 undefined wo edge/level bank select (ltim): disabled. replaced by elcr1 and elcr2. 2 undefined wo adi: ignored for the intel? sch. should be programmed to 0. 1 undefined wo single or cascade (sngl): must be programmed to a 0 to indicate two controllers operating in cascade mode. 0 undefined wo wicw4 write required (ic4): this bit must be programmed to a 1 to indicate that icw4 needs to be programmed.
datasheet 387 acpi functions 18.3.9.2 micw2/sicw2?master/slave initialization command word 2 register offset/port: master: 21h attribute: wo slave: a1h default value: uuh size: 8 bits micw2 and sicw2 are used to initialize the master or slave interrupt controller with the five most significant bits of the interru pt vector address. the value programmed for bits[7:3] is used by the cpu to define the ba se address in the interrupt vector table for the interrupt routines associated with each irq on the controller. typical isa values are 08h for the micw2 and 70h for the sicw2. bit default and access description 7:3 undefined wo interrupt vector base address: bits [7:3] define the base address in the interrupt vector table for the inte rrupt routines associated with each interrupt request level input. 2:0 undefined wo interrupt request level: when writing icw2, these bits should all be 0. during an interrupt ackn owledge cycle, these bits are programmed by the interrupt controller with the interrupt to be serviced. this is combined with bits 7:3 to form the interrupt vector driven onto the data bus during the second inta# cycle. the code is a 3-bit binary code: code master interrupt slave interrupt 000 irq0 irq8 001 irq1 irq9 010 irq2 irq10 011 irq3 irq11 100 irq4 irq12 101 irq5 irq13 110 irq6 irq14 111 irq7 irq15
acpi functions 388 datasheet 18.3.9.3 micw3?master initializ ation command word 3 register offset/port: 21h attribute: wo default value: uuh size: 8 bits 18.3.9.4 sicw3?slave initializat ion command word 3 register offset/port: a1h attribute: wo default value: 00h size: 8 bits bit default and access description 7:3 undefined wo these bits must be programmed to 0. 2 undefined wo cascaded controller connection (ccc): this bit must always be programmed to a 1 to indicate the slave controller for interrupts 8-15 is cascaded on irq2. 1:0 undefined wo these bits must be programmed to 0. bit default and access description 7:3 x wo reserved. must be 0. 2:0 0 wo slave identification code: this field must be programmed to 02h to match the code broadcast by the master controller during the inta# sequence.
datasheet 389 acpi functions 18.3.9.5 micw4/sicw4?master/slave initialization command word 4 register offset/port: master: 21h attribute: wo slave: a1h default value: 00h size: 8 bits 18.3.9.6 mocw1/socw1?master/slave operational co ntrol word 1 (interrupt mask) register offset/port: master: 21h attribute: r/w slave: a1h default value: 00h size: 8 bits bit default and access description 7:5 0 wo reserved. must be 0. 4 0 wo special fully nested mode (sfnm): should normally be disabled by writing a 0 to this bit. if sfnm=1, the special fully nested mode is programmed. 3 0 wo buffered mode (buf): must be cleared for no n-buffered mode. writing 1 will result in undefined behavior. 2 0 wo master/slave in buffered mode (msbm): not used. should always be programmed to 0. 1 0 wo automatic end of interrupt (aeoi): this bit should normally be programmed to 0. this is the normal en d of interrupt. if th is bit is 1, the automatic end of interrupt mode is programmed. aeoi is discussed in section 18.3.6.2 . 0 0 wo microprocessor mode (mm): this bit must be written to 1 to indicate that the controller is operating in an intel architecture-based system. writing 0 will result in undefined behavior. bit default and access description 7:0 00h r/w interrupt request mask (irm): when a 1 is written to any bit in this register, the corresponding irq line is masked. when a 0 is written to any bit in this register, the correspondi ng irq mask bit is cleared, and interrupt requests will again be acce pted by the controller. masking irq2 on the master controller will also mask the interrupt requests from the slave controller.
acpi functions 390 datasheet 18.3.9.7 mocw2/mocw2?master/slave operational control word 2 register offset/port: master: 20h attribute: wo slave: a0h default value: 001uuuuub size: 8 bits following a part reset or icw initialization, the controller enters the fully nested mode of operation. non-specific eoi without rotati on is the default. both rotation mode and specific eoi mode are disabled following initialization. bit default and access description 7:5 001 wo rotate and eoi codes: r, sl, eoi - these three bits control the rotate and end of interrupt modes and combinat ions of the two. a chart of these combinations is listed above under the bit definition. 000 = rotate in auto eoi mode (clear) 001 = non-specific eoi command 010 = no operation 011 = *specific eoi command 100 = rotate in auto eoi mode (set) 101 = rotate on non-specific eoi command 110 = *set priority command 111 = *rotate on specific eoi command *l0 ? l2 are used 4:3 undefined wo ocw2 select: when selecting ocw2, bits 4:3 = ?00? 2:0 undefined wo interrupt level select (l2, l1, l0): l2, l1, and l0 determine the interrupt level acted upon when the sl bit is active. a simple binary code, outlined above, selects the channel for the command to act upon. when the sl bit is inactive, these bits do not have a defined function; programming l2, l1 and l0 to 0 is sufficient in this case. code interrupt level 000 irq0/8 001 irq1/9 010 irq2/10 011 irq3/11 100 irq4/12 101 irq5/13 110 irq6/14 111 irq7/15
datasheet 391 acpi functions 18.3.9.8 mocw3/socw3?master/slave operational co ntrol word 3 register offset/port: master: 20h attribute: ro, wo slave: a0h default value: 001xxx10b size: 8 bits 18.3.9.9 elcr1?master edge/level control register offset/port: 4d0h attribute: ro, r/w default value: 00h size: 8 bits bit default and access description 7 0 ro reserved. must be 0. 6 0 wo special mask mode (smm): if this bit is set, the special mask mode can be used by an interrupt service routine to dynamically alter the system priority structure while the routin e is executing, through selective enabling/ disabling of the other channe l's mask bits. bit 6, the esmm bit, must be set for this bi t to have any meaning. 5 1 wo enable special mask mode (esmm) 0 = smm bit becomes a ?don't care? 1 = smm bit is enabled to set or reset the special mask mode 4:3 x wo ocw3 select (o3s): when selecting ocw3, bits 4:3 = ?01?. 2 x wo poll mode command (pmc): when cleared, poll command is not issued. when set, the next i/o re ad to the interrupt controller is treated as an interrupt acknowledge cycle. an encoded byte is driven onto the data bus, representing the highest priori ty level reques ting service. 1:0 10 wo register read command (rrc): these bits provide control for reading the isr and interrupt irr. when bit 1=0, bit 0 will not effect the register read selection. following icw initialization, the default ocw3 port address read will be ?read irr?. to retain th e current selection (read isr or read irr), always write a 0 to bit 1 wh en programming this register. the selected register can be read repe atedly without reprogramming ocw3. to select a new status register, oc w3 must be reprogrammed prior to attempting the read. 00 = no action 01 = no action 10 = read irq register 11 = read is register bit default and access description 7:3 0 r/w edge level control (ecl[7:3]) : in edge mode, (bit cleared), the interrupt is recognized by a low to high transition. in level mode (bit set), the interrupt is recognized by a high level. 2:0 0 ro reserved. the cascade channel, ir q2, heart beat timer (irq0), and keyboard controller (irq1), cannot be put into level mode.
acpi functions 392 datasheet 18.3.9.10 elcr2?slave edge/level control register offset/port: 4d1h attribute: ro, r/w default value: 00h size: 8 bits 18.4 advanced peripheral interrupt controller (ioxapic) 18.4.1 functional overview delivery of interrupts with the ioxapic is done by writing to a fixed set of memory locations in cpu(s). the following sequence is used: ? when the intel? sch detects an interrupt event (active edge for edge-triggered mode or a change for level-triggered mode), it sets or resets the internal irr bit associated with that interrupt. ? the intel? sch delivers the message by performing a write cycle to the appropriate address with the appropriate data. when either an edge-triggered or level-triggered interrupt is detected, the ?assert message? is sent by the ioxapic controller. in the case of a level-triggered interrupt, however, if the interrupt is still active after the eoi, then another ?assert message? is sent to indicate that the interrupt is still active. 18.4.2 unsupported modes these delivery modes are not supported for the following reasons: ? nmi/init: this cannot be delivered while the cpu is in the stop grant state. in addition, this is a break event for power management ? smi: there is no way to block the delivery of the smi#, except through bios ? virtual wire mode b: the intel? sch does not support the intr of the 8259 routed to the i/oxapic pin 0. bit default and access description 7 0 r/w edge level control (ecl[15:14]): in edge mode, (bit cleared), the interrupt is recognized by a low to high transition. in level mode (bit set), the interrupt is recognized by a high level. bit 7 applies to irq15, and bit 6 to irq14. 5 0 ro reserved 4 0 r/w edge level control (ecl[12:9]: in edge mode, (b it cleared), the interrupt is recognized by a low to high transition. in level mode (bit set), the interrupt is recognized by a high le vel. bit 4 applies to irq12, bit 3 to irq11, bit 2 to irq10, and bit 1 to irq9. 0 0 ro reserved
datasheet 393 acpi functions 18.4.2.1 eoi (end of interrupt) an eoi is performed as a pci express eoi me ssage. the data of the eoi message is the vector. this value is compared with all th e vectors inside the ioxapic, and any match causes rte[x].rirr to be cleared. 18.4.2.2 interrupt message format the intel? sch writes the message to the backbone as a 32-bit memory write cycle. it uses the following formats the address and data: 18.4.3 pci express interrupts when external devices through pci express generate an interrupt, they will send the message defined in the pci express specification for generating inta# ? intd#. these will be translated internal assertions/deassertions of inta# ? intd#. table 61. interrupt delivery address value bit description 31:20 feeh 19:12 destination id: rte[x].did 11:4 extended destination id: rte[x].edid 3 redirection hint: if rte[x].dlm = ?lowest priority ? (001), this bit will be set. otherwise, this bit will be cleared. 2 destination mode: rte[x].dsm 1:0 00 table 62. interrupt delivery data value bit description 31:16 0000h 15 trigger mode: rte[x].tm 14 delivery status: 1 = assert, 0 = deassert. only assert messages are sent. this bit is always set to 1 13:12 00 11 destination mode: rte[x].dsm 10:8 delivery mode: rte[x].dlm 7:0 vector: rte[x].vct
acpi functions 394 datasheet 18.4.4 routing of intern al device interrupts the internal devices on the intel? sch dr ive pci interrupts. these interrupts can be routed internally to any of pirqa# ? pi rqh#. this is done utilizing the ?device x interrupt pin? and ?device x interrupt route? registers located in chipset configuration space. see section 6.2 . for each device, the ?device x interrupt pin? register exists which tells the functions which interrupt to report in their pci header space, in the ?interrupt pin? register, for the operating system. additionally, the ?device x interrupt route? register tells the interrupt controller, in conjunction with the ?device x interrupt pin? register, which of the internal pirqa# ? pirqh# to drive the devices interrupt onto. this requires the interrupt controller to know which function each device is connected to. 18.4.5 memory registers the apic is accessed through an indirect addressing scheme. these registers are mapped into memory space starting at address fec00000h. the registers are shown below. 18.4.5.1 address fec00000h: idx?index register this 8-bit register selects which indirect register appears in the window register to be manipulated by software. software will progra m this register to select the desired apic internal register. the registers listed below can be accessed through the idx register. when accessing these registers, accesses must be done as dws, otherwise unsp ecified behavior will result. software should not attempt to writ e to reserved registers. some reserved registers may return non-zero values when read. table 63. apic memory-mapped register locations address symbol register fec00000h idx index register fec00010h wdw window register fec00040h eoi eoi register table 64. idx register values offset symbol register default access 00h id identification 0000000h ro, r/w 01h vs version 0000000h ro, r/w 10h?11h rte0 redirection table 0 0000000h ro, r/w 12h?13h rte1 redirection table 1 0000000h ro, r/w 3eh?3fh rte23 redirection table 23 0000000h ro, r/w
datasheet 395 acpi functions 18.4.5.2 id?identification register offset: 00h attribute: ro, r/w default value: 00000000h size: 32 bits 18.4.5.3 vs?version register offset: 01h attribute: ro, r/w default value: 00000000h size: 32 bits bit default and access description 31:28 0 ro reserved 27:24 0h r/w apic identification (aid): software must progra m this value prior to using the controller. 23:16 0 ro reserved 15 0 r/w scratchpad 14 0 r/w reserved. writes to this bit have no effect. 13:0 0 ro reserved bit default and access description 31:24 00h ro reserved 23:16 17h ro maximum redirection entries (mre): this is the entry number (0 being the lowest entry) of the highest entry in the redirection table. in intel? sch this field is hardwired to 17h to indicate 24 interrupts. 15 0 ro pin assertion register supported (prq): this bit indicates that the ioxapic does not implement the pin assertion register. 14:8 0 ro reserved 7:0 20h ro version (vs): this field identifies the implementation version as ioxapic.
acpi functions 396 datasheet 18.4.5.4 rte[0-23]?redirection table entry register offset: 10h?3fh attribute: ro, r/w default value: see table below size: 64 bits there are a total of 24 redirection table entry registers, each at a different 8-bit offset address, starting at 10h. bit default and access description 63:56 x r/w destination id (did): destination id of the local apic. 55:48 x r/w extended destination id (edid): extended destination id of the local apic. 47:17 0 ro reserved 16 1 r/w mask (msk): when set, interrupts are not delivered nor held pending. when cleared, and edge or level on this interrupt results in the delivery of the interrupt. 15 x r/w trigger mode (tm): when cleared, the interrupt is edge sensitive. when set, the interrupt is level sensitive. 14 x r/w remote irr (rirr): this is used for level triggered interrupts its meaning is undefined for edge triggere d interrupts. this bit is set when ioxapic sends the level interrupt messag e to the cpu. this bit is cleared when an eoi message is re ceived that matches the vct field. this bit is never set for smi, nmi, init , or extint delivery modes. 13 x r/w polarity (pol): this specifies the polarity of each interrupt input. when cleared, the signal is active high. when set, the signal is active low. 12 x ro delivery status (ds): this field contains the current status of the delivery of this interrupt. when set, an interrupt is pending and not yet delivered. when cleared, there is no activity for this entry 11 x r/w destination mode (dsm): this field is used by the local apic to determine whether it is the destination of the message. 10:8 x r/w delivery mode (dlm): this field specifies how the apics listed in the destination field should ac t upon reception of this signal. certain delivery modes will only operate as intended when used in conjunction with a specific trigger mode. these encodings are as follows: 10:0 x r/w vector (vct): this field contains the interru pt vector for this interrupt. values range between 1-h and feh. value name/notes 000 fixed 001 lowest priority 010 smi/not supported 011 reserved 100 nmi/not supported 101 init/not supported 110 reserved 111 extint
datasheet 397 acpi functions 18.4.5.5 address fec00010h: wdw?window register this 32-bit register specifies the data to be re ad or written to the register pointed to by the idx register. this register can be accessed only in dw quantities. 18.4.5.6 address fec00040h: eoi?eoi register when a write is issued to this register, the ioxapic will check the lower 8 bits written to this register, and compare it with the vector field for each entry in the i/o redirection table. when a match is found, rte.rirr for that entry will be cleared. if multiple entries have the same vector, each of thos e entries will have rte.rirr cleared. only bits 7:0 are used. bits 31:8 are ignored. 18.5 serial interrupt 18.5.1 overview the interrupt controller supports a serial irq scheme. the signal used to transmit this information is shared betwee n the interrupt controller and all peripherals that support serial interrupts. the signal line, serirq, is synchronous to lpc clock, and follows the sustained tri-state protocol that is used by lpc signals. the serial irq protocol defines this sustained tri-state signaling in the following fashion: ? s - sample phase: signal driven low ? r - recovery phase: signal driven high ? t - turn-around phase: signal released the interrupt controller supports 21 serial interrupts. these represent the 15 isa interrupts (irq0- 1, 3-15), the four pci interrupts, and the control signals smi# and iochk#. serial interrupt information is transferred using three types of frames: ? start frame: serirq line driven low by the interrupt controller to indicate the start of irq transmission ? data frames: irq information transmitted by pe ripherals. the interrupt controller supports 21 data frames. ? stop frame: serirq line driven low by the interrupt controller to indicate end of transmission and next mode of operation. 18.5.2 start frame the serial irq protocol has two modes of operation which effect the start frame: ? continuous mode: the interrupt controller is solely responsible for generating the start frame ? quiet mode: peripheral initiates the start frame, and the interrupt controller completes it. these modes are entered through the length of the stop frame. see section 13.5.4 for information on how this is done. continuous mode must be entered first, to start the first frame. this start frame width is determined by the scnt.sfpw field in d3 1:f0 configuration space. this is a polling mode. in quiet mode, the serirq line remains inactive and pulled up between the stop and start frame until a peripheral drives serirq low. the interrupt controller senses the line low and drives it low for the remainder of the start frame. since the first lpc clock of the start frame was driven by the peripheral, the interrupt controller drives serirq low for 1 lpc clock less than in continuous mode. this mode of operation allows for lower power operation.
acpi functions 398 datasheet 18.5.3 data frames once the start frame has been initiated, the serirq peripherals start counting frames based on the rising edge of serirq. each of the irq/data frames has exactly 3 phases of one clock each: ? sample phase: during this phase, a device drives serirq low if its corresponding interrupt signal is low. if its correspon ding interrupt is high, then the serirq devices tri-state serirq. serirq remains high due to pull-up resistors. ? recovery phase: during this phase, a device drives serirq high if it was driven low during the sample phase. if it was not driven during the sample phase, it remains tri-stated in this phase. ? turn-around phase: the device tri-states serirq. 18.5.4 stop frame after the data frames, a stop frame will be driven by the interrupt controller. serirq will be driven low for 2 or 3 lpc clocks. th e number of clocks is determined by the scnt.md field in d31:f0 configuration space. the number of clocks determines the next mode: 18.5.5 unsupported se rial interrupts there are four interrupts on the serial stream which are not supported by the serial interrupt controller of the intel? sch. th ese interrupts are generated internally, and are not sharable with other devices within the system. these interrupts are: ? irq0: heartbeat interrupt generated off of the internal 8254, counter 0. ? irq8#: rtc interrupt can only be generated internally. ? irq13: this interrupt is not supported by the intel? sch. ? irq14: pata interrupt can only be generated from the external p-device. the interrupt controller will ignore the st ate of these interrupts in the stream. table 65. serial interrupt mode selection stop frame width next mode 2 lpc clocks quiet mode: any serirq device initiates a start frame 3 lpc clocks continuous mode: only the interrupt controller initiates a start frame
datasheet 399 acpi functions 18.5.6 data frame format ta b l e 6 6 shows the format of the data frames. the decoded int[a:d]# values are anded with the corresponding pci express input signals (pirq[a:d]#). this way, the interrupt can be shared. the other interrupts decoded through serirq are also anded with the corresponding internal interrupts. for example, if irq10 is set to be used as the sci, then it is anded with the decoded value for irq10 from the serirq stream. table 66. data frame format data frame # interrupt clocks past start frame comment 1irq0 2 ignored. irq0 can only be generated through the internal 8524 2 irq1 5 before port 60h latch 3smi# 8 causes smi# if low. will set bit 15 in the smi_sts register 4irq3 11 5irq4 14 6irq5 17 7irq6 20 8irq7 23 9 irq8 26 ignored. irq8# can on ly be generated internally 10 irq9 29 11 irq10 32 12 irq11 35 13 irq12 38 before port 60h latch 14 irq13 41 ignored 15 irq14 44 ignored 16 irq15 47 17 iochck# 50 same as isa iochck# going active. 18 pci inta# 53 19 pci intb# 56 20 pci intc# 59 21 pci intd# 62
acpi functions 400 datasheet 18.6 real time clock 18.6.1 overview the real time clock (rtc) module provides a battery backed-up date and time keeping device. three interrupt features are available: time of day alarm with once a second to once a month range, periodic rates of 122 ms to 500 ms, and end of update cycle notification. seconds, minutes, hours, days, day of week, month, and year are counted. the hour is represented in twelve or tw enty-four hour format, and data can be represented in bcd or binary format. the desi gn is meant to be functionally compatible with the motorola ms146818b. the time keep ing comes from a 32.768-khz oscillating source, which is divided to achieve an update every second. the lower 14 bytes on the lower ram block have very specific functi ons. the first ten are for time and date information. the next four (0ah to 0dh) ar e registers, which configure and report rtc functions. a host-initiated write takes precedence over a hardware update in the event of a collision. 18.6.2 update cycles an update cycle occurs once a second, if b.set bit is not asserted and the divide chain is properly configured. during this proc edure, the stored time and date will be incremented, overflow will be checked, a ma tching alarm condition will be checked, and the time and date will be rewritten to the ra m locations. the update cycle will start at least 488 s after a.uip is asserted, and the entire cycle will not take more than 1984 s to complete. the time and date ram lo cations (0-9) will be disconnected from the external bus during this time. 18.6.3 interrupts the rtc interrupt is internally routed within the intel? sch to interrupt vector 8. this interrupt is not it shared with any other interrupt. irq8# from the serirq stream is ignored. the hpet can also be mapped to irq8#; in this case, the rtc interrupt is blocked. 18.6.4 lockable ram ranges the rtc?s battery-backed ram supports two 8- byte ranges that can be locked through the pci config spac e. if the locking bit is set, the corresponding range in the ram will not be readable or writeable. a write cycle to those locations has no effect. a read cycle to those locations will not return the location?s actual value (undefined). once a range is locked, the range can be unlocked only by a warm reset, which will invoke the bios and allow it to relock the ram range. 18.6.5 month and year alarms month and year alarms are not supported in the intel? sch.
datasheet 401 acpi functions 18.6.6 i/o registers the rtc internal registers and ram are or ganized as two banks of 128 bytes each, called the standard and extended banks. the first 14 bytes of the standard bank contain the rtc time and date information along with four registers, a?d, that are used for configuration of the rtc. the extended bank contains a full 128 bytes of battery backed sram. all data movement between the host cpu and the rtc is done through registers mapped to the standard i/o space. notes: 1. i/o locations 70h and 71h are the standard is a location for the real -time clock. locations 72h and 73h are for accessing the extended ram. the extended ram bank is also accessed using an indexed scheme. i/o a ddress 72h is used as the a ddress pointer and i/o address 73h is used as the data register. index addresses above 127h are not valid. 2. software must preserve the value of bit 7 at i/o addresses 70h and 74h. when writing to this address, software must fi rst read the value, and then write the same value for bit 7 during the sequential address write. note: port 70h is not directly readable. the only way to read this register is through alt access mode. although rtc index bits 6:0 are readable from port 74h, bit 7 will always return 0. if the nmi# enable is not chan ged during normal operation, software can alternatively read this bit once and then re tain the value for all subsequent writes to port 70h. 18.6.7 indexed registers the rtc contains two sets of indexed registers that are accessed using the two separate index and target registers (70/71h or 72/73h), as shown in ta b l e 6 8 . table 67. rtc i/o registers i/o locations function 70h and 74h real-time clock (s tandard ram) index register 71h and 75h real-time clock (s tandard ram) target register 72h and 76h extended ram in dex register (if enabled) 73h and 77h extended ram targ et register (if enabled) table 68. rtc (standard) ram bank index name 00h seconds 01h seconds alarm 02h minutes 03h minutes alarm 04h hours 05h hours alarm 06h day of week 07h day of month 08h month 09h year 0ah register a 0bh register b 0ch register c 0dh register d 0eh?7fh 114 bytes of user ram
acpi functions 402 datasheet 18.6.7.1 rtc_rega?register a offset: 0a attribute: r/w default value: uuh size: 8 bit this register is used for general configuratio n of the rtc functions. none of the bits are affected by reset# or any other intel? sch reset signal. bit default and access description 7 undefined r/w update in progress (uip): this bit may be monito red as a status flag. 0 = the update cycle will not start fo r at least 488 s. the time, calendar, and alarm information in ram is alwa ys available when the uip bit is 0. 1 = the update is soon to occur or is in progress. 6:4 undefined r/w division chain select (dv[2:0]): these three bits co ntrol the divider chain. the division chain itself is re set by rsmrst# to all 0s and it can also be cleared to 0s by firmware th rough programming of dv. the periodic event (setting of rtcis.pf and the as sociated interrupt) can be based on the time as measured from rsmrst# deassertion until a divider reset (dv=?11x? to ?010?) is performed by firmware. dv2 corresponds to bit 6. 010 = normal operation 11x = divider reset 101 = bypass 15 stages (test mode only) 100 = bypass 10 stages (test mode only) 011 = bypass 5 stages (test mode only) 001 = invalid 000 = invalid 3:0 undefined r/w rate select (rs[3:0]): selects one of 13 taps of the 15 stage divider chain. the selected tap can generate a periodic interrupt if the pie bit is set in register b. otherwise this tap will set the pf flag of register c. if the periodic interrupt is not to be used, th ese bits should all be set to 0. rs3 corresponds to bit 3. 0000 = interrupt never toggles 0001 = 3.90625 ms 0010 = 7.8125 ms 0011 = 122.070 s 0100 = 244.141 s 0101 = 488.281 s 0110 = 976.5625 s 0111 = 1.953125 ms 1000 = 3.90625 ms 1001 = 7.8125 ms 1010 = 15.625 ms 1011 = 31.25 ms 1100 = 62.5 ms 1101 = 125 ms 1110 = 250 ms 1111= 500 ms
datasheet 403 acpi functions 18.6.7.2 rtc_regb?register b, genera l configuration (lpc i/f?d31:f0) offset: 0bh attribute: r/w default value: u0u00uuu size: 8 bit this register resides in the resume well. bits are reset by rsmrst#. bit default and access description 7 undefined r/w update cycle inhibit (set): enables/inhibits the u pdate cycles . this bit is not affected by rsmrst# nor any other reset signal. 0 = update cycle occurs normally once each second. 1 = a current update cycle will abort and subsequent upda te cycles will not occur until set is re turned to 0. when set is 1, the bios may initialize time and calendar bytes safely. note: this bit should be set then cleare d early in bios post after each powerup. 6 0 r/w periodic interrupt enable (pie): this bit is cleared by rsmrst#, but not on any other reset. 0 = disable. 1 = enable. allows an interrupt to occu r with a time base set with the rs bits of register a. 5 undefined r/w alarm interrupt enable (aie): this bit is cleared by rtcrst#, but not on any other reset. 0 = disable. 1 = enable. allows an interrupt to oc cur when the af is set by an alarm match from the update cycle. an alarm can occur once a second, once an hour, once a day, or once a month. 4 0 r/w update-ended interrupt enable (uie): this bit is cleared by rsmrst#, but not on any other reset. 0 = disable. 1 = enable. allows an interrupt to occur when the update cycle ends. 3 0 r/w square wave enable (sqwe): this bit serves no function in the intel? sch. it is left in this register bank to provide compatibility with the motorola 146818b. the intel? sch has no sqw pin. this bit is cleared by rsmrst#, but not on any other reset. 2 undefined r/w data mode (dm). this bit specifies either binary or bcd data representation. this bit is not affe cted by rsmrst# nor any other reset signal. 0 = bcd 1 = binary 1 undefined r/w hour format (hourform): this bit indicates the hour byte format. this bit is not affected by rs mrst# nor any other reset signal. 0 = 12-hour mode. in twelve-hour mode , the seventh bit represents a.m. as 0 and p.m. as 1. 1 = 24-hour mode.
acpi functions 404 datasheet 18.6.7.3 rtc_regc?register c (flag register) offset: 0ch attribute: ro default value: 00u00000 size: 8 bit writes to register c have no effect. 0 undefined r/w daylight savings enable (dse): this bit triggers two special hour updates per year. the days for the hour adjustment are those specified in united states federal law as of 1987, which is different than previous years. this bit is not affected by rsmrst# nor any other reset signal. 0 = daylight savings time updates do not occur. 1 = a) update on the first sunday in april, where time increments from 1:59:59 a.m. to 3:00:00 a.m. b) update on the last sunday in october when the ti me first reaches 1:59:59 a.m. it is changed to 1:00:00 a.m. the time must increment normally for at least two update cy cles (seconds) previous to these conditions for the time change to occur properly. bit default and access description bit default and access description 7 0 ro interrupt request flag (irqf): irqf = (pf * pie) + (af * aie) + (uf *ufe). this bit also causes the rt c interrupt to be asserted. this bit is cleared upon rsmrst# or a read of register c. 6 0 ro periodic interrupt flag (pf): this bit is cleared upon rsmrst# or a read of register c. 0 = if no taps are specified through the rs bits in register a, this flag will not be set. 1 = periodic interrupt flag will be 1 wh en the tap specified by the rs bits of register a is 1. 5 undefined ro alarm flag (af): 0 = this bit is cleared upon rtcrst# or a read of register c. 1 = alarm flag will be set after all alarm values match the current time. 4 0 ro update-ended flag (uf): 0 = the bit is cleared upon rsmrst# or a read of register c. 1 = set immediately following an update cycle for each second. 3:0 0h ro reserved.
datasheet 405 acpi functions 18.6.7.4 rtc_regd?register d (flag register) offset: 0dh attribute: r/w default value: 10uuuuuu size: 8 bit 18.7 general purpose i/o 18.7.1 functional description 18.7.1.1 power wells gpio[6:0], gpio[9:8], and slpiovr# are in the core well. gpiosus[3:0] are in the resume well. 18.7.1.2 smi# and sci routing if gpgpe.en[n] is set, and the gpio is conf igured as an input, the gpe bit gpe0s.gpio will be set. if gpsmi.en[n] is set, and the gp io is configured as an input, the smi bit smis.gpio will be set. 18.7.1.3 triggering a gpio (whether in the core well or resume well) can cause an wake event and smi/ sci on either its rising edge, its falling edge , or both. these are controlled through the cgtpe and cgtne registers for the core well gpios, and rgtpe and rgtne for the resume well gpios. if the bit corresponding to the gpio is set, the transition will cause a wake event/smi/sci, and the corresponding bit in the trigger status register (cgts for core well gpios, rgts for resume well gpios). the event can be cleared by writing a 1 to the status bit position. bit default and access description 7 1 r/w valid ram and time bit (vrt): 0 = this bit should always be written as a 0 for write cycle, however it will return a 1 for read cycles. 1 = this bit is hardwired to 1 in the rtc power well. 6 0 r/w reserved. this bit always returns a 0 and should be set to 0 for write cycles. 5:0 undefined r/w date alarm: these bits store the date of month alarm value. if set to 000000b, then a don?t care state is assumed. the host must configure the date alarm for these bits to do anything, yet they can be written at any time. if the date alarm is not enabled, these bits will return 0s to mimic the functionality of the motorola 14681 8b. these bits are not affected by any reset assertion.
acpi functions 406 datasheet 18.7.2 i/o registers the control for the general purpose i/o si gnals is handled through an independent 64-byte i/o space. the base offset for this space is selected by the gpiobase register in d31:f0 config space. if a bit is allocated for a gpio that doesn?t exist, unless otherwise indicated, the bit will always read as 0 and values written to that bit will have no effect. all core well bits are reset by the standard conditions that assert reset#, and all suspend well bits are reset by the standard conditions that clear internal suspend registers. table 69. gpio i/o register map offset mnemonic name default access 00h?03h cgen core well gpio enable 000003ffh ro, r/w 04h?07h cgio core well gpio input/output select 000003ffh ro, r/w 08h?0bh cglv core well gpio level for input or output 00000000h ro, r/w 0ch?0fh cgtpe core well gpio trigger positive edge enable 00000000h ro, r/w 10h?13h cgtne core well gpio trigger negative edge enable 00000000h ro, r/w 14h?17h cggpe core well gpio gpe enable 00000000h ro, r/w 18h?1bh cgsmi core well gpio smi enable 00000000h ro, r/w 1ch?1fh cgts core well gpio trigger status 00000000h ro, r/w 20h?23h rgen resume well gpio enable 0000000fh ro, r/w 24h?27h rgio resume well gpio input/output select 0000000fh ro, r/w 28h?2bh rglv resume well gpio level for input or output 00000000h ro, r/w 2ch?2fh rgtpe resume well gpio trigger positive edge enable 00000000h ro, r/w 30h?33h rgtne resume well gpio tr igger negative edge enable 00000000h ro, r/w 34h?37h rggpe resume well gpio gpe enable 00000000h ro, r/w 38h?3bh rgsmi resume well gpio smi enable 00000000h ro, r/w 3ch?3fh rgts resume well gpio trigger status 00000000h ro, r/w
datasheet 407 acpi functions 18.7.2.1 cgen?core well gpio enable register offset: 00?03h attribute: ro, r/w default value: 000003ffh size: 32 bits 18.7.2.2 cgio?core well gpio in put/output select register offset: 04?07h attribute: ro, r/w default value: 000003ffh size: 32 bits bit default and access description 31:10 0s ro reserved 9 1 r/w gpio 9 enable (gp9en) 0 = neither gpio9 or extts1# functionality is usable. 1 = gpio9 will behave as a gpio9 and allows extts1# input to pass to the thermal management controller when cgio[9] is set for input. 8 1 r/w gpio 8 enable (gp8en) 0 = gpio8 will behave as prochot# output 1 = gpio8 will behave as a gpio 7 1 ro reserved. gpio7 is configured by the cmc as slpiovr# 6:0 7fh ro reserved. all unmultiplexed gp ios are enabled by default. bit default and access description 31:10 0s ro reserved 9:0 3ffh r/w input/output (i/o) 1 = the gpio signal (if enabled) is programmed as an input. 0 = the gpio signal is programmed as an output. if the pin is multiplexed, and not enab led, writes to these bits have no effect. note: do not write a ?0? to bit 7, it may affect the slpiovr# configuration done by the cmc. note: bit 9 must be set in order for gpio[9] to function as extts1# input.
acpi functions 408 datasheet 18.7.2.3 cglvl?core well gpio leve l for input or output register offset: 08?0bh attribute: ro, r/w default value: 00000000h size: 32 bits 18.7.2.4 cgtpe?core well gpio trigge r positive edge enable register offset: 0c?0fh attribute: ro, r/w default value: 00000000h size: 32 bits bit default and access description 31:10 0s ro reserved 9:0 0s r/w level (lvl): if the gpio is programmed to be an output (cgio.io[n] = 0), then this bit is used by software to drive a value on the pin. 1 = high, 0 = low. if the gpio is programmed as an input, then this bit refl ects the state of the input signal (1 = high, 0 = low. ) and writes will have no effect. the value of this bit has no me aning if the gpio is disabled (cgen.en[n] = 0). bit default and access description 31:10 0s ro reserved 9:0 0s r/w trigger enable (te) 1 = corresponding gpio, if enabled as input using gio.io[n], will case an smi#/sci when a 0-to-1 transition occurs. 0 = gpio is not enabled to trigger an smi#/sci on a 0-to-1 transition. this bit has no meaning if cgio.io[ n] is cleared (i.e., programmed for output)
datasheet 409 acpi functions 18.7.2.5 cgtne?core well gpio trigge r negative edge enable register offset: 10?13h attribute: ro, r/w default value: 00000000h size: 32 bits 18.7.2.6 cggpe?core well gp io gpe enable register offset: 14?17h attribute: ro, r/w default value: 00000000h size: 32 bits 18.7.2.7 cgsmi?core well gp io smi enable register offset: 18?1bh attribute: ro, r/w default value: 00000000h size: 32 bits bit default and access description 31:10 0s ro reserved 9:0 0s r/w trigger enable (te) 1 = corresponding gpio, if enabled as input using cgio.i o[n], will case an smi#/sci when a 1-to -0 transition occurs. 0 = gpio is not enabled to trigger an smi#/sci on a 1-to-0 transition. this bit has no meaning if cgio.io[n] is cleared (i.e., programmed for output) bit default and access description 31:10 0s ro reserved 9:0 0s r/w enable (en): when set, when cgts.ts[n] is set, the acpi gpe0e.gpio bit will be set. bit default and access description 31:10 0s ro reserved 9:0 0s r/w enable (en): when set, when cgts.ts[n] is set, the acpi smie.gpio bit will be set.
acpi functions 410 datasheet 18.7.2.8 cgts?core well gpio trigger status register offset: 1c?1fh attribute: ro, r/w default value: 00000000h size: 32 bits 18.7.3 resume well gp io i/o registers the resume-well i/o registers starting at offsets 20h through 3ch follow the same format as their core-well counter parts detailed above. the only difference is that these registers live in the resume well and are not reset during removal of the core power supply. notable differences between the core well re gisters and the resume well versions are described below: 18.7.3.1 rgen?resume well gpio enable register offset: 20?23h attribute: ro, r/w default value: 0000000fh size: 32 bits bit default and access description 31:10 0s ro reserved 9:0 0s r/wc trigger status (ts) 1 = the corresponding cgpio, if en abled as input using cgio.io[n], triggered an smi#/sci. th is will be set if a 0-to-1 transition occurred and cgtpe.te[n] was set, or a 1-to-0 transition occurred and cgtne.te[n] was set. if both cgtpe.te[n] and cgtne.te[n] are set, then this bit will be set on both a 0-to-1 and a 1-to-0 transition. this bit will not be set if the core we ll gpio[n] is configured as an output. bit default and access description 31:4 0s ro reserved 3 1 r/w resume well gpio 3 enable (rgp3en) 0 = gpio3 will behave as usbcc input 1 = gpio3 will behave as a gpio 2:0 111b ro reserved. all unmultiplexed resume well gpios are enabled by default.
datasheet 411 acpi functions 18.8 smbus controller 18.8.1 overview the intel? sch provides an smbus 1.0-compliant host controller. the host controller provides a mechanism for the cpu to init iate communications with smb peripherals (slaves). the host controller is used to send commands to other smb devices. it runs off of the backbone clock, with a minimum smbclk fr equency the backbone clock divided by 4 (i.e., smbclk, at a minimum, is 4 backbone clocks). the frequency to use for smbclk is chosen by programming hclk.div. to ensure proper data capture, the minimum value to be programmed into this register is 9h (for 33-mhz backbone), or 7h (for 25-mhz clock), resulting in a frequency ro ughly equivalent to 1 mhz. software then sets up the host controller with an address, command, and for writes, data, and then tells the controller to start. when the controller has finished transmitting data on writes, or receiving data on reads, it will generate an sm i# or interrupt, if enabled. the host controller supports eight command protocols of the smb interface (see the smbus specification): quick command, send byte, receive byte, write byte/word, read byte/word, process call, block read , block write and block write-block read process call. the host controller requires the various data and command fields be setup for the type of command to be sent. when software sets hctl.st, the host controller will perform the requested transaction and generate an interrupt or smi# (if enabled) when finished. once started, the values of the hctl, hcmd, tsa, hd0, and hd1 should not be changed or read until hsts.intr has been set. the host controller will update all registers while completing the new command. 18.8.2 bus arbitration several masters may attempt to get on the bus at the same time by driving smbdata low to signal a start condition. when the in tel? sch releases smbdata, and samples it low, then some other master is driving the bus and intel? sch must stop transferring data. if the intel? sch loses arbitration, it sets hsts.be, and if enabled, generates an interrupt or smi#. the cpu is responsible for restarting the transaction. 18.8.3 bus timings the smbus runs at between 10?100 khz. th e intel? sch smbus will run off of the backbone clock. table 70. smbus timings timing min ac spec name t low 4.7 s clock low period t high 4.0 s clock high period t su:dat 250 ns data setup to rising smbclk t hd:dat 0 ns data hold from falling smbclk t hd:sta 4.0 s repeat start condition generated from rising smbclk t su:sta 4.7 s first clock fall from start condition t su:sto 4.0 s last clock rising edge to last data rising edge (stop condition) t buf 4.7 s time between consecutive transactions
acpi functions 412 datasheet the min ac column indicates the minimum times required by the smbus specification. the intel? sch tolerates these timings. wh en the intel? sch is sending address, command, or data bytes, it will drive data relative to the clock it is also driving. it will not start toggling the clock until the start or stop condition meets proper setup and hold. the intel? sch will also ensure mini mum time between smbus transactions as a master. 18.8.3.1 clock stretching devices may stretch the low time of the cl ock. when the intel? sch attempts to release the clock (allowing the clock to go high), the clock will remain low for an extended period of time. the intel? sch moni tors smbclk after it releases the bus to determine whether to enable the counter for th e high time of the clock. while the bus is still low, the high time counter must not be enabled. the low period of the clock can be stretched by an smbus master if it is not ready to send or receive data. 18.8.3.2 bus time out if there is an error in the transaction, such that a device does not signal an acknowledge, or holds the clock lower than the allowed time-out time, the transaction will time out. the intel? sch will discard the cycle, and set hs ts.de. the time out minimum is 25 ms. the time-out counter insi de the intel? sch will start when the first bit of data is transferred by intel? sch. 18.8.4 smi# the system can be set up to ge nerate smi# by setting hctl.se. 18.8.5 i/o registers table 71. smbus i/o register map address mnemonic register name default access 00h hctl host control 00h ro, r/w 01h hsts host status 00h r/w 02h?03h hclk host clock divider 0000h r/w 04h tsa transmit slave address 00h r/w 05h hcmd host command 00h r/w 06h hd0 host data 0 00h r/w 07h hd1 host data 1 00h r/w 20h?3fh hbd host block data 00h r/w
datasheet 413 acpi functions 18.8.5.1 hctl?host control register offset: 00h attribute: ro, r/w default value: 00h size: 8 bits bit default and access description 7 0 r/w smi enable (se): enable generation of an sm i# upon completion of the command. 6 0 ro reserved 5 0 r/w alert enable (ae): software sets this bit to enable an interrupt/smi# due to smbalert#. 4 0 r/w start/stop (st): initiates the command descri bed in the cmd field. this bit always reads zero. hsts.bsy id entifies when the intel? sch has finished the command. if this bi t is cleared prior to the command completing, the transaction will be st opped, and hsts.cs will be cleared. 3 0 ro reserved 2:0 r/w command (cmd): indicates the command that the intel? sch is to perform. if enabled, the intel? sch will generate an interrupt or smi# when the command has completed. if a reserved command is issued, the intel? sch will set hsts.de and pe rform no command, and will not operate until hsts.de is cleared. bits command description 000 quick : uses tsa. 001 byte : uses tsa and cmd regist ers. tsa.r determines the direction. 010 byte data : uses tsa, cmd, and hd0 registers. tsa.r determines the direct ion. if a read, hd0 will contain the read data. 011 word data : uses tsa, cmd, hd0, and hd1 registers. tsa.r determines th e direction. if a read, hd0 and hd1 contain the read data. 100 process call: uses tsa, hcmd, hd0, and hd1 registers. tsa.r determines th e direction. upon completion, hd0 and hd1 contain the read data. 101 block : uses tsa, cmd, hd0, and hbd registers. for writes, the count is stored in hd0 and indicates how many bytes of data will be transferred. for reads, the count is received and stored in hd0. tsa.r determines the direction. for writes, data is retrieved from the first n (where n is equal to the specified count) addresses of hbd. for reads, the data is stored in hbd. 110 - 111 reserved
acpi functions 414 datasheet 18.8.5.2 hsts?host status register offset: 01h attribute: ro, r/w default value: 00h size: 8 bits 18.8.5.3 hclk?host clock divider register offset: 02h attribute: r/w default value: 0000h size: 8 bits bit default and access description 7:4 0h ro reserved 3 0 ro busy (bsy): when set, indicates that the intel? sch is running a command. no smb registers should be accessed while this bit is set. 2 0 r/wc bus error (be): when set, indicates a transaction collision. 1 0 r/wc device error (de): when set, this indicates one of the following errors: invalid command field, an unclai med cycle, or a time-out error. 0 0 r/wc completion status (cs): when bsy is cleared, if this bit is set, the command completed successfully. if cleared, the command did not complete successfully. bit default and access description 15:0 00h r/w divider (div): this controls how many ba ckbone clocks should be counted for the generation of smbc lk. recommended values are listed below: sm bus frequency backbone frequency 33 mhz 25 mhz 1 khz 208eh 186ah 10 khz 0342h 0271h 50 khz 00a7h 007dh 100 khz 0054h 003fh 400 khz 0015h 0010h 1 mhz 0009h 0007h
datasheet 415 acpi functions 18.8.5.4 tsa?transmit slave address register offset: 04h attribute: r/w default value: 00h size: 8 bits 18.8.5.5 hcmd?host command register offset: 05h attribute: r/w default value: 00h size: 8 bits this field is transmitted in the command field of the smb protocol during the execution of any command. 18.8.5.6 hd0?host data 0 register offset: 06h attribute: r/w default value: 00h size: 8 bits this field is transmitted in the data0 field of an smbus cycle. for block writes, this register reflects the number of bytes to tran sfer. this register should be programmed to a value between 1h (1 bytes) and 20h (32 by tes) for block counts. a count of 00h or above 20h will result in no transfer and will set hsts.f. bit default and access description 7:1 0 r/w address (ad): 7-bit address of the targeted slave. 0 0 r/w read (r): direction of the host transfer. 0 = write 1 = read bit default and access description 7:0 00h r/w command (cmd) bit default and access description 7:0 00h r/w data 0
acpi functions 416 datasheet 18.8.5.7 hd1?host data 1 register offset: 07h attribute: r/w default value: 00h size: 8 bits this field is transmitted in the data1 field of an smbus cycle. 18.8.5.8 hbd?host data block register offset: 20h?3fh attribute: 4r/w default value: 00h size: 256 bits bit default and access description 7:0 00h r/w data 1 bit default and access description 255:0 0 r/w data (d): this contains block data to be sent on a block write command, or received block data, on a block re ad command. any data received over 32-bytes will be lost.
datasheet 417 absolute maximums and operating conditions 19 absolute maximums and operating conditions 19.1 absolute maximums ta b l e 7 2 lists the intel? sch maximum enviro nmental stress ratings. functional operating parameters at the absolute ma ximum and minimum is neither implied nor ensured. the voltage on a specific pin shall be denoted as ?v? followed by the subscripted name of that pin. for example: ?v tt refers to the voltage applied to the v tt signal (in the case of power supply signal names, the second v is not re peated in the subscripted portion.) ?v h_swing would refer to the voltage level of the h_swing signal. caution: at conditions outside functional operatio n limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. if a device is returned to conditions within f unctional operation limit s after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits. if the component is exposed to co nditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function, or its reliability will be severely degraded. although the device contains protective circuitry to resist damage from electro-static discharge, precautions should always be taken to avoid high static voltages or electric fields. table 72. intel? sch absolute maximum ratings (sheet 1 of 2) parameter description/ signal names min max unit t die die temperature under bias 1 090oc t storage (short-term) t storage (sustained exposure) storage temperature 2, 3,5 storage temperature 2, 3,5 -45 -10 75 45 oc voltage on any 3.3-v pin with respect to ground -0.5 v cc33 + 0.5 v voltage on any 5-v tolerant pin with respect to ground (v cc5ref = 5 v) -0.5 v cc5ref + 0.5 v 1.05-v supply voltage with respect to v ss vcc, vtt, vccsusbyp, vccsususbbyp -0.5 2.1 v 1.5 v supply voltage with respect to v ss vccahpll, vccdhpll, vcclvds, vccsdvo, vccpcie, vccapciepll, vccadplla, vccadpllb, vcc15, vcc15, vcc15usb, vcc15usbsusbyp, vccausbpll, vcc15sus, vccrtcbyp, vcchda 4 -0.5 2.1 v
absolute maximums and operating conditions 418 datasheet notes: 1. functionality is not ensured for parts that exceed t die temperature above 90oc. t die is measured at top center of the package. full performance may be a ffected if the on-die th ermal sensor is enabled. 2. possible damage to the intel? sch may occur if the intel? sch storage temperature exceeds 75oc. intel does not ensure functionality for parts that have exceeded temperatures above 75oc due to specification violation. 3. storage temperature is ap plicable to storage condit ions only. in this scenario, the device must not receive a clock, and no pins can be connected to a voltage bias. st orage within these limits will not effect the long-term reliab ility of the device. this rating applies to the silicon and do es not include any tray or packaging. 4. vcchda is configurable for 1.5- v or 3.3-v operation. use the appropriate maximum limits for the selected configuration. 5. in addition to this storage temperature specificat ion, compliance to the latest ipc/jedec j-std-033b.1 joint industry standard is required for all surface mount devices (smds). this document governs handling, packing, shipping and use of moisture/reflow sensitive smds. notes: 1. this specification applies for worst case scenario pe r rail. in this context, a cumulative use of these values will represent a non realistic application. 2. these power numbers should not be used for average battery shelf life projections since these are absolute worst case numbers. 1.8 v supply voltage with respect to v ss vccsm -0.3 2.3 v 3.3 v supply voltage with respect to v ss vccapciebg, vcc33, vcc33, vccp33usbsus, vccausbbgsus, vcc33sus, vcc33rtc, vcchda -0.5 4.6 v 5.0 v supply voltage with respect to v ss vcc5ref, vcc5refsus -0.5 5.5 v table 72. intel? sch absolute maximum ratings (sheet 2 of 2) parameter description/ signal names min max unit table 73. intel? sch maximum power consumption power plane maximum power consumption unit notes symbol s0 s3 s4/s5 see ta b l e 7 6 50m 100u w 1, 2
datasheet 419 dc characteristics 20 dc characteristics 20.1 signal groups the signal description includes the type of buffer used for the particular signal. table 74. intel? sch buffer types buffer type description agtl+ assisted gunning transceiver logic plus. open drain interface signals that require termination. refer to the agtl+ i/o specification for complete details. cmos, cmos open drain 1.05-v cmos buffer cmos_hda cmos buffers for intel hd audio inte rface that can be configured for either 1.5-v or 3.3-v operation. cmos1.8 1.8-v cmos buffer. these buffers ca n be configured as stub series te r m i n a t i o n l o g i c ( s s t l 1 . 8 ) cmos3.3, cmos3.3 open drain 3.3-v cmos buffer cmos3.3-5 3.3-v cmos buffer, 5-v tolerant usb compliant with usb1.1 and usb2.0 specifications. pcie pci express interface signals. these signals are compatible with pci express 1.0a signaling environmen t ac specifications and are ac coupled. the buffers are not 3.3- v tolerant. differential voltage specification = (|d+ - d-|) * 2 = 1.2 v max . single-ended maximum = 1.5 v. single-ended minimum = 0 v. sdvo serial-dvo differential output bu ffers. these signal s are ac coupled. lvds low voltage differential signal bu ffers. these signals should drive across a 100-ohm resistor at the receiver when driving. analog analog reference or output. can be used as a threshold voltage or for buffer compensation.
dc characteristics 420 datasheet notes: 1. these are 1.05-v buffers powered by vtt (exc ept bsel and tck which are powered by vcc). 2. the intel hd audio interface signals can operate in either 1.5-v or 3.3-v ranges. 3.3 v operation is the default. the hda interface can be configured to use the low voltage range by setting the low voltage mode enable bit of the hdctl pci configuratio n register (d27:f0, offset 40h, bit 0). table 75. intel? sch signal group definitions s signal group signals notes agtl+ h_ads#, h_adstb[1:0]#, h_dbsy#, h_ defer#, h_drdy#, h_dstbn[3:0]#, h_dstbp[3:0]#, h_bpri#, h_cpurst #, h_trdy#, h_rs [2:0]#, h_dpwr# cmos h_a[31:3]#, h_bnr#, h_breq0#, h_d[63:0 ]#, h_dinv[3:0]#, h_hit#, h_hitm#, h_req[4:0]#, h_lock#, h_ thrmtrip#, h_cpuslp#, h_pbe#, h_intr, h_nmi, h_smi#, tdi, tms, trst#, h_stpclk#, h_dpslp#, h_dprstp#, h_cpupwrgd, bsel2, cfg[1:0], tck 1 cmos open drain h_init#, tdo cmos_hda hda_rst#, hda_sync, hda_sdo, hd a_sdi[1:0], hda_dock en#, hda_dockrst# 2 cmos1.8 sm_dq[63:0], sm_dqs[7:0], sm_ma[14: 0], sm_bs[2:0], sm_ras#, sm_cas#, sm_we#, sm_rcvenin#, sm_rcvenou t#, sm_cs[1:0]#, sm_cke[1:0] cmos3.3 lpc_ad[3:0], lpc_frame#, lpc_serirq, lpc_clkrun# sd2_data[7:0], sd[0:2]_cmd, sd[0:2]_wp, sd[0:2]_cd#, sd[0:2]_led, intvrmen, spkr, smi#, extts, thrm#, reset#, pwrok, rsmrst#, rtcrst#, susclk, wake#, stpcpu#, dprslpvr, sl pmode, rstwarn, slprdy#, rstrdy#, l_vdden, l_bklten, l_bkltctl, usb_oc[7:0]#, gpio[9:8], slpiovr#, gpio[6:0], gpiosus[3:0] cmoss3.3 open drain clkreq#, gpe#, l_ddc_clk, l_ddc_data, l_ctla_clk, l_ctlb_clk, sdvo_ctrlclk, sdvo_ctrldata, smb_data, smb_alert# cmos3.3-5 pata_dd[15:0], pata_da[2:0], pata_dior#, pata_diow#, pata_ddack#, pata_dcs3#, pata_dcs1#, pata_ddreq, pata_iordy, pata_ideirq pcie pcie_petp[2:1], pcie_petn[2:1] , pcie_perp[2:1], pcie_pern[2:1] sdvo sdvob_red+, sdvob_red- , sdvob_green+, sdvob_green-, sdvob_blue+, sdvob_blue-, sdvob_clk+, sdvob_clk- sdvob_int+, sdvob_int-, sdvo_tvclkin +, sdvo_tvclkin-, sdvo_stall+, sdvo_stall- lvds la_datap[3:0], la_datan[3:0], la_clkp, la_clkn usb usb_dp[7:0], usb_dn[7:0] analog, reference h_rcompo, h_swing, h_gvref, h_cgvref , pcie_icompo, sm_vref, sm_rcompo, pcie_icompi, rtc_x1, rtc_x2, usb_rbiasp, usb_rbiasn clocks h_clkinp, h_clkinn, pcie_clkinp, pc ie_clkinn, usb_clk48, smb_clk, lpc_clkout[1:0], da_refclkinp, da_refclkinn, db_refclkinpscc, db_refclkinnscc, hda_clk, susclk, sd[2 :0]_clk, sm_ck[1:0], sm_ck[1:0]#, clk14, rtc_x1, rtc_x2
datasheet 421 dc characteristics 20.2 power and current characteristics notes: 1. this specification is the thermal design power and is the estimated maximum possible expected power generated in a component by a realistic applicatio n. it is based on extrapolations in both hardware and software te chnology over the life of the component. it does not represent the expect ed power generated by a powe r virus. studies by intel indicate that no application will cause ther mally significant power dissipation exceeding this specification, although it is possible to concoct higher power synthetic workloads that write but never read. under real istic read/write conditions, th is higher power workload can only be transient and is accounte d in the ac (max) specification. table 76. thermal design power symbol parameter range unit notes tdp thermal design power (under nominal voltages) 1.6 ? 2.5 w 1 table 77. dc current charac teristics (she et 1 of 2) symbol parameter signal names max 1,2 unit notes i vtt 1.05-v v tt supply current vtt 739 ma 3 i vcc_105 1.05-v core supply current vcc 1800 ma 4,5,12 1990 i vcc_15 1.5-v core supply current vcc15 10 ma i vccpcie 1.5-v pci express supply current vccpcie, vccpciepll 250 ma 6,7 i vcclvds 1.5-v lvds supply current vcclvds 62 ma i vccsdvo 1.5-v sdvo supply current vccsdvo 73 ma i vccpciebg 3.3-v pci express band gap vccpciebg 5 ma i vcc33 3.3-v hv cmos supply current vcc33 100 ma i vcchpll 1.5-v host pll supply current vccahpll, vccdhpll 15 42 ma ma i vccadplla,b 1.5-v display plla and pllb supply current vccadplla, vccadpllb 48 48 ma ma i vccusb15 1.5-v usb core current vccusbcore 322 ma i vccusbsus 3.3-v usb suspend current vcc33usbsus 32 ma i vccusbsusbg 3.3-v usb suspend bandgap current vcc33usbbgsus 5 ma i vccusbpll 1.5-v usb pll current vccausbpll 11 ma i vccsus33 3.3-v suspend current vcc33sus 5 ma i vcc33rtc 3.3-v real time clock vcc33rtc 6 a i vcc5ref 5-v reference current vcc5ref 3 ma i vcc5refsus 5-v suspend current vcc5refsus 1 ma
dc characteristics 422 datasheet notes: 1. this note has been removed. 2. i ccmax is determined on a per- interface basis, and all cannot happen simultaneously. 3. can vary from cpu. this estimate does not in clude sense amps, as they are on a separate rail, or processor-specific signals. 4. estimate is only for max current co ming through the chipset?s supply balls. 5. includes maximum leakage. 6. rail includes pll current. 7. i ccmax number includes max current for all signal names listed in the table. 8. determined with 2x intel? sch ddr2 buffer strength sett ings into a 50 ohms to ? vccsm (ddr/ddr2) test load. 9. specified at the measurement point into a ti ming and voltage compliance test load as shown in transmitter compliance eye diagram of pci express specification and measured over any 250 consecutive tx ul's. specified at the measurement point and measured over any 250 consecutive uls. the test load shown in receiver compliance eye diagram of pci express specification. should be used as the rx device when taking measurements 10. standby refers to syst em memory in self refresh during s3 (str). 11. the lower value is specified between 0oc and 50oc. the higher value is specified between 50oc and 90oc. 12. the lower value is for all skus. the higher value is for us15x sku with 266 mhz graphics core frequency enabled. ddr2 interface 8,9 i vccsm ddr2 system memory: (1.8-v, 533 mts) (1.5-v, 533 mts) vccsm 568 473 ma i sus_vccsm ddr2 system memory interface (1.8-v) standby supply current vccsm ~5 ma 10, 11 1255 i smvref ddr2 system memory interface reference voltage (0.90 v) supply current 10 a i sus_smvref ddr2 system memory interface reference voltage (0.90 v) standby supply current 10 a 10 i ttrc ddr2 system memory interface resister compensation voltage (1.8 v) supply current vccsm 20 ma i sus_ttrc ddr2 system memory interface resister compensation voltage (1.8 v) standby supply current vccsm 15 a 10 table 77. dc current characteristics (sheet 2 of 2) symbol parameter signal names max 1,2 unit notes
datasheet 423 dc characteristics 20.3 general dc characteristics the voltage on a specific pin shall be denoted as ?v? followed by the subscripted name of that pin. for example: ?v tt refers to the voltage applied to the vt t signal. (in the case of power supply signal names, the second v is not re peated in the subscripted portion.) ?v h_swing would refer to the voltage level of the h_swing signal table 78. operating condition power supply and reference dc characteristics (sheet 1 of 2) signal name parameter min nom max unit notes power supply voltages vcc 1.05 v intel? sch core supply voltage 0.9975 1.05 1.1025 v vtt 1.05 v host agtl+ termination voltage 0.9975 1.05 1.1025 v vcc15 vccpcie vccsdvo vcclvds vcc15usb 1.5 v supply voltage 1.425 1.50 1.575 v vccahpll vccdhpll vccapciepll vccadplla vccadpllb vccausbpll various 1.5 v pll supply voltages 1.425 1.5 1.575 v 1 vccsm 1.8 v ddr2 i/o supply voltage 1.5 v ddr2 i/o supply voltage 1.7 1.425 1.8 1.5 1.9 1.575 v vcc33 vccpciebg 3.3 v power supply voltage 3.135 3.3 3.465 v vcchda 1.5/3.3 v supply for intel high definition audio 1.425 3.135 1.5 3.3 1.575 3.465 v vcc33sus vccp33usbsus vccausbbgsus 3.3 v suspend-well power supplies 3.135 3.3 3.465 v vcc5ref vcc5refsus 5 v reference voltages 4.75 5.0 5.25 v vcc33rtc real time clock voltage 2.0 3.3 3.6 v reference signals h_swing host compensation reference voltage 0.3125 x v tt ? 1% 0.3125 x v tt 0.3125 x v tt + 1% v h_gvref host agtl+ reference voltage 2/3 x v tt ? 1% 2/3 x v tt 2/3 x v tt + 1% v
dc characteristics 424 datasheet h_cgvref host cmos refe rence voltage 0.49 x v tt 0.50 x v tt 0.51 x v tt v sm_vref ddr2 reference voltage 0.49 x v ccsm 0.50 x v ccsm 0.51 x v ccsm h_rcompo sm_rcompo pcie_icompo pcie_icompi usb_rbiasp usb_rbiasn table 79. active signal dc characteristics (sheet 1 of 3) symbol parameter min nom max unit notes agtl+ v il input low voltage ?0.1 0.0 2 / 3 v tt ? 0.1 v v ih input high voltage 2 / 3 v tt + 0.1 v tt v tt + 0.1 v v ol output low voltage ? ? 1 / 3 v tt + 0.1 v v oh output high voltage v tt ? 0.1 ? vtt v i ol output low current ? ? v ttmax (1.5 r ttmin ) ma 1 i leak input leakage current ? ? 20 a 2 c in input capacitance 2 ? 3.5 pf cmos, cmos open drain v il input low voltage ?0.1 ? ? v tt ? 0.1 v 4 v ih input high voltage ? v tt + 0.1 ? v tt + 0.1 v 4 v ol output low voltage ? ? 0.1 x vtt v 4 v oh output high voltage 0.9 x v tt ?vttv4 i leak input leakage current ? ? 20 a 2, 3 c in input capacitance 1 ? 3.5 pf cmos_hda v il input low voltage ?0.1 0.0 ? v cchda ? 0.7 v v il, lvm input low voltage (lvm) -0.1 0.0 0.4 v cchda v v ih input high voltage ? v cchda + 0.7 v cchda v cchda + 0.1 v v ih, lvm input high voltage (lvm) 0.6 v cchda v cchda v cchda + 0.1 v v ol output low voltage ? ? 0.1 v cchda v v oh output high voltage 0.9 v cchda ??v i leak input leakage current ? ? 20 a c in input capacitance 2 ? 3.5 pf cmos1.8 table 78. operating condition power supply an d reference dc characteristics (sheet 2 of 2) signal name parameter min nom max unit notes
datasheet 425 dc characteristics v il input low voltage ? ? v sm_vref ? 0.250 v v ih input high voltage v sm_vref + 0.250 ? ? v v ol output low voltage ? ? v sm_vref ? 0.250 v v oh output high voltage v sm_vref + 0.250 ? ? v i ol output low current ? ? 0.3 ma i leak input leakage current ? ? 1.4 a 5 c in input capacitance 2.0 ? 3.4 pf cmos3.3, cmos3.3 open drain v il input low voltage ?0.1 0.0 ? v cc33 ? 0.7 v v ih input high voltage ? v cc33 + 0.7 v cc33 v cc33 + 0.1 v v ol output low voltage ? ? 0.1 v cc33 v3 v oh output high voltage 0.9 v cc33 ??v3 i ol output low current ? ? 1.5 ma i oh output high current ? ? -0.5ma ma i leak input leakage current ? ? 20 a 3 c in input capacitance 1 ? 3.5 pf cmos3.3?5 v il input low voltage ?0.1 0.0 ? v cc33 ? 0.7 v v ih input high voltage ? v cc33 + 0.7 v cc33 v cc33 + 0.1 v v ol output low voltage ? ? 0.1 v cc33 v v oh output high voltage 0.9 v cc33 ??v i leak input leakage current ? ? 20 a c in input capacitance 1 ? 3.5 pf usb refer to the universal serial bus (usb) base specification, rev. 2.0 . pcie v tx-diff p-p differential peak to peak output voltage 0.4 ? 0.6 v 6 v tx_cm-acp ac peak common mode output voltage ??20mv6 z tx-diff-dc dc differential tx impedance 80 100 120 v rx-diff p-p differential input peak to peak voltage 0.175 ? 1.2 v 6 v rx_cm-acp ac peak common mode input voltage ??150mv sdvo v tx-diff p-p differential peak to peak output voltage 0.4 ? 0.6 v 6 table 79. active signal dc ch aracteristics (sheet 2 of 3) symbol parameter min nom max unit notes
dc characteristics 426 datasheet notes: 1. r ttmin = 50 ohm 2. v ol < v pad < v tt 3. for cmos open drain signals defined in ta b l e 7 9 , v oh , v ol , and i leak dc specifications are not applicable due to the pull-up/pull-down resister that is required on the board. 4. bsel2, cfg[1:0] and tck signals reference v cc , not v tt . 5. at vccsm = 1.7 v. 6. specified at the measurement point into a ti ming and voltage compliance test load as shown in transmitter compliance eye diagram of pci express specification and measured over any 250 consecutive tx uls. specified at the measurement poin t and measured over any 250 consecutive uls. the test load shown in receiver compliance eye diagram of pci express specification. should be used as the rx device when taking measurements. 7. applicable to the following sign als: h_clkinn/p, pcie_clkinn/p, db_drefclkin[n,p]scc, da_drefclkinn/p v tx_cm-acp ac peak common mode output voltage ??20mv6 z tx-diff-dc dc differential tx impedance 80 100 120 v rx-diff p-p differential input peak to peak voltage 0.175 ? 1.2 v 6 v rx_cm-acp ac peak common mode input voltage ??150mv lvds v od differential output voltage 250 350 450 mv v od change in v od between complementary output states 0.8 ? 50 mv v os offset voltage ? 1.25 1.375 v v os change in v os between complementary output states ??50 i os output short circuit current ? -3.5 -10 i oz output tristate current ? 1 10 differential clocks v swing input swing 300 ? ? mv 7, 8 v cross crossing point 300 ? 550 mv 7, 9, 10, 11 v cross_var v cross variance ? ? 140 mv 7, 9, 10, 12 v ih maximum input voltage ? ? 1.15 v 7, 9, 13 v il minimum input voltage -0.3 ? ? v 7, 9, 14 rtc_x1, rtc_x2 v il input low voltage -0.5 ? 0.1 v v ih input high voltage 0.4 ? 1.2 v c in input capacitance 3.5 pf table 79. active signal dc characteristics (sheet 3 of 3) symbol parameter min nom max unit notes
datasheet 427 dc characteristics 8. measurement taken from differential waveform. 9. measurement taken from single ended waveform. 10. v cross is defined as the volt age where clock = clock#. 11. only applies to the differential rising edge (that is, clock rising and clock# falling) 12. the total variation of all v cross measurements in any particular system. this is a subset of v cross min /v cross max (v cross absolute) allowed. the intent is to limit v cross induced modulation by setting v cross_var to be smaller than v cross absolute. 13. the max voltage including overshoot. 14. the min voltage including undershoot. s table 80. pll noise rejection specifications pll noise rejection specification notes vccahpll 34 db(a) attenuation of power supply noise in 1-mhz (f1) to 66- mhz (f2) range, <0.2 db gain in pass band and peak to peak noise should be limited to < 120 mv vccdhpll peak to peak noise sh ould be limited to < 120 mv vccapcie < 0 db(a) in 0 to 1mhz, 20 db(a) attenuation of power supply noise in 1 mhz(f1) to 1.25 ghz(f2) range, <0.2 db gain in pass band and peak to peak noise should be limited to < 40 mv vccadplla 20 db(a) attenuation of power supply noise in 10-khz(f1) to 2.5-mhz(f2) range, <0.2 db gain in pass band and peak to peak noise should be limited to < 100 mv vccadpllb 20 db(a) attenuation of power supply noise in 10-khz(f1) to 2.5-mhz(f2) range, <0.2 db gain in pass band and peak to peak noise should be limited to < 100 mv vccausbpll usb pll
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datasheet 429 ballout and package information 21 ballout and package information the intel? sch comes in an flip-chip ball grid array (fcbga) package and consists of a silicon die mounted face down on an organic substrate populated with 1249 solder balls on the bottom side. capacitors may be placed in the area surrounding the die. because the die-side capacitors are electrically conductive, and only slightly shorter than the die height, care should be taken to avoid contacting the capacitors with electrically conductive materials. doing so may short the capacitors and possibly damage the device or render it inactive. the use of an insulating material between the capacitors and any thermal solution should be considered to prevent capacitor shorting. an exclusion, or keep out zone, surrounds the die and capacitors, and identifies the contact area for the package. care should be taken to avoid contact with the package inside this area. unless otherwise specified, interpret the dime nsions and tolerances in accordance with asme y14.5-1994. the dimensions are in millim eters. key package attributes are listed below: dimensions: ? package parameters: 22 mm x 22 mm ? ball count: 1249 ? land metal diameter: 375 microns ? solder resist opening: 321 microns to l e ra n c e s : ? .x - 0.1 ? .xx - 0.05 ? angles - 1.0 degrees
ballout and package information 430 datasheet 21.1 package diagrams figure 7. package dime nsions (top view)
datasheet 431 ballout and package information figure 8. package dimensions (bottom view)
ballout and package information 432 datasheet note: maximum outgoing package coplan arity not to exceed 8 mils. figure 9. package dimensio ns (side view, unmounted)
datasheet 433 ballout and package information figure 10. package dimensions (solder ball detail ?c?) figure 11. package dimens ions (underfill detail ?b?)
ballout and package information 434 datasheet figure 12. package dimensio ns (solder resist opening)
datasheet 435 ballout and package information 21.2 ballout definition and signal locations figure 13 , figure 14 , and figure 15 provide the ballout as viewed from the top of the package. ta b l e 8 1 lists the ballout alphabetically by signal name.
ballout and package information 436 datasheet figure 13. intel? sch ball map (top view, columns 1?17) # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 # a vss_nctf vss_nctf h_a20# h_a21# h_a22# hda_rst # vss sd0_dat a1 a b vss_nctf h_a30# h_a23# h_adstb 1# h_a26# h_a29# hda_sdi1 reserve d19 b c vss_nctf vss vss vss vss vss vss vss vss c d h_a12# h_a16# h_a27# h_a31# h_a28# h_a17# hda_sdo xor_test d e vss_nctf vss vss vss vss vss hda_syn c hda_doc ken# vss e f h_a15# h_a7# h_a10# h_dpslp # h_a25# h_trdy# hda_sdi0 sd0_dat a3 f g h_a8# vss vss vss vss h_a19# vss vss vss g h h_a13# h_adstb 0# h_a11# h_a24# h_dbsy# h_a18# hda_doc krst# sd0_dat a0 h j h_a14# vss vss vss h_drdy# vcchda vss sd0_cmd vss j k h_req4# h_a5# h_ads# h_req2# h_clkinn vcchda hda_clk reserve d20 k l h_breq0 # vss vss vss vss vss vss vss vss l m h_a3# h_a9# h_cpurs t# h_a4# h_clkinp vtt vtt vcc33 m n h_req1# vss vss vss vss vss vtt vcc33 vcc33 n p h_a6# h_req0# h_dpwr# h_req3# h_bpri# vtt vss vss p r h_bnr# vss vss vss vss vss vtt vcc15 vcc15 r t h_rs1# h_rs0# h_hitm# h_rs2# h_rcomp o vtt vss vcc t u h_d8# vss vss vss vss vss vtt vss vss u v h_d2# h_d6# h_swing h_d0# h_hit# vtt vss vcc v w h_dstbp 0# vss vss vss vss vss vtt vss vss w y h_d7# h_dstbn 0# h_lock# h_d9# h_gvref vtt vss vcc y aa h_d3# vss vss vss vss vss vtt vss vss aa ab h_d10# h_d12# h_smi# h_d15# h_nmi vtt vss vcc ab ac h_d4# vss vss vss vss vss vtt vss vss ac ad h_d5# h_cgvre f h_defer # h_dinv0 # h_stpclk # vtt vss vcc ad ae h_d14# vss vss vss vss vss vtt vss vss ae af h_d11# h_d1# h_intr h_d13# h_init# vtt vss vcc af ag h_d21# vss vss vss vss vss vtt vss vss ag ah h_d17# h_d29# h_pbe# h_d22# h_cpuslp # vtt vss vcc ah aj h_d16# vss vss vss vss vss vtt vss vss aj ak h_d25# h_d20# h_testin # h_d23# h_dprstp # vtt vss vcc ak al h_dstbn 1# vss vss vss vss vss vtt vss vss al am h_dinv1 # h_dstbp 1# h_thrmt rip# h_d18# vss vtt vss vcc am an h_d19# vss vss vss vss vss vtt vss vss an ap h_d31# h_d30# h_cpupw rgd h_d24# reserve d4 vtt vss vccsm ap ar h_d26# vss vss vss vss vss vtt vss vss ar at h_d28# h_d41# h_d38# h_d27# reserve d5 vtt vss vccsm at au h_d37# vss vss vss vss vss vtt vss vss au av h_d44# h_d32# h_d34# h_d39# h_d43# vtt vss vccsm av aw h_dstbn 2# vss vss vss vss vss vtt vss vccsm aw ay h_d47# h_dstbp 2# h_d42# h_d35# h_dinv2 # vss vss vss ay ba h_d36# vss vss vss vss vccahpll sm_cas# sm_cs1# sm_we# ba bb h_d46# h_d40# h_d33# h_d60# vccdhpll vss vss vss bb bc h_d45# vss vss vss vss sm_dq63 sm_dq62 sm_dq57 sm_dq54 bc bd h_d48# h_d53# h_d52# h_d56# h_d50# vss vss vss bd be h_d55# vss vss vss vss sm_ck1 sm_rcom po reserve d2 sm_ma10 be bf h_d54# h_d57# h_d61# h_dstbp 3# h_d62# vss vss vss bf bg vss_nctf vss vss vss vss sm_ck1# sm_dqs7 sm_dq56 sm_dq50 bg bh vss_nctf h_d49# h_d63# h_dstbn 3# h_d58# vss vss vss bh bj vss_nctf vss_nctf vss vss vss vss sm_dq58 sm_dq61 sm_dq51 bj bk vss_nctf vss_nctf h_d59# h_dinv3 # h_d51# sm_dq59 sm_dq60 sm_dq55 bk # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 #
datasheet 437 ballout and package information figure 14. intel? sch ball map (top view, columns 18?33) #1819202122232425262728293031 32 33# a sd2_pwr # sd1_led sd2_data 3 sd2_data 1 l_ddcclk sdvo_ct rldata l_bklten l_bkltct l a b sd0_cd# sd1_wp sd1_cd# sd2_cmd sd2_wp clkreq# smi# reserved 1 b c vss vss vss vss vss vss vss vss c d sd0_clk sd1_pwr # sd1_data 3 sd2_led sd2_clk l_ctla_c lk l_vdden extts d e vss vss vss sd2_data 7 vss vss vss vss e f sd0_wp sd1_cmd sd1_data 0 sd2_data 4 sd2_data 2 bsel2 sdvo_ct rlclk thrm# f g vss reserve d18 vss vss vss gpio0 vss gpio3 g h sd0_led sd0_pwr # sd1_clk sd2_data 5 sd2_data 6 l_ddcda ta stpcpu# clk14 h j sd1_data 1 vss sd2_data 0 vss cfg0 vss gpio7 vss j k sd0_data 2 reserve d21 sd1_data 2 sd2_cd# l_ctlb_d ata gpio9 gpio1 smb_aler t# k l vss vss vss vss vss vss vss vss l m vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 vcc15 m n vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 vcc15 vcc15 n p vss vss vss vss vss vss vss vcc15 p r vcc15 vcc15 vcc15 vcc15 vcc15 vcc15 vcc15 vcc15 r t vcc vcc vcc vcc vcc vcc vcc vcc t u vss vss vss vss vss vss vss vss u v vcc vcc vcc vcc vcc vcc vcc vcc v w vss vss vss vss vss vss vss vss w y vcc vcc vcc vcc vcc vcc vcc vcc15usb y aa vss vss vss vss vss vss vss vss aa ab vcc vcc vcc vcc vcc vcc vcc vcc15usb ab ac vss vss vss vss vss vss vss vss ac ad vcc vcc vcc vcc vcc vcc vcc vcc15usb ad ae vss vss vss vss vss vss vss vss ae af vcc vcc vcc vcc vcc vcc vcc vcc af ag vss vss vss vss vss vss vss vss ag ah vcc vcc vcc vcc vcc vcc vcc vcc ah aj vss vss vss vss vss vss vss vss aj ak vcc vcc vcc vcc vcc vcc vcc vcc ak al vss vss vss vss vss vss vss vss al am vcc vcc vcc vcc vcc vcc vcc vcc am an vss vss vss vss vss vss vss vss an ap vccsm vccsm vccsm vccsm vccsm vccsm vccsm vccsm ap ar vss vss vss vss vss vss vss vss ar at vccsm vccsm vccsm vccsm vccsm vccsm vccsm vccpcie at au vss vss vss vss vss vss vss vss au av vccsm vccsm vccsm vccsm vccsm vccsm vccsm vccsm av aw vccsm vccsm vccsm vccsm vccsm vccsm vccsm vccsm aw ay vss vss vss vss vss vss vss vss ay ba sm_ma1 reserve d3 sm_cs0# sm_ma3 sm_ma2 sm_ma9 sm_ma7 sm_ma8 ba bb vss vss vss vss vss vss vss vss bb bc sm_dq53 sm_dq47 sm_ma5 sm_dq40 sm_bs0 sm_dq35 sm_dq31 sm_dq28 bc bd vss vss vss vss vss vss vss vss bd be sm_ma13 sm_ras# sm_dqs5 sm_bs1 sm_dq36 sm_ma4 sm_ma6 sm_ma12 be bf vss vss vss vss vss vss vss vss bf bg sm_dq52 sm_dq46 sm_dq41 sm_dq38 sm_dqs4 sm_dq33 sm_dq25 sm_dq26 bg bh vss vss vss vss vss vss vss vss bh bj sm_dq49 sm_dq43 sm_dq45 sm_dq39 sm_ma0 sm_dq32 sm_dq30 sm_dq29 bj bk sm_dqs6 sm_dq48 sm_dq42 sm_dq44 sm_dq37 sm_dq34 sm_dq27 sm_dqs3 bk #1819202122232425262728293031 32 33#
438 datasheet ballout and package information figure 15. intel? sch ball map (top view, columns 34?50) #3435363738394041424344454647484950# a lpc_ad2 pata_dio w# pata_dd7 pata_dd9 pata_dd1 0 vcc33rtc vss_nctf vss_nctf a b cfg1 lpc_clko ut1 lpc_seri rq pata_dd1 5 pata_dd6 pata_dd2 pata_dda ck# vss_nctf vss_nctf b c vss vss vss vss vss vss pata_dcs 3# pwrok c d dprslpvr lpc_clkr un# lpc_clko ut2 pata_dd0 pata_dd1 2 pata_dd4 pata_ior dy vss vss_nctf d e vss vss vss vss pata_dd1 4 vss pata_dcs 1# reserve d0 e f gpio2 gpio6 lpc_clko ut0 pata_dd1 1 pata_dd5 pata_dio r# intvrmen rtc_x1 rtc_x2 f g vss smb_dat a vss vss pata_dd1 pata_idei rq vss vss g h gpio8 gpio5 smb_clk pata_da0 pata_dd1 3 vss vss rtcrst# rstrdy# h j spkr vss lpc_ad1 pata_dd8 pata_ddr eq pata_da1 susclk slprdy# j k vcc5ref gpio4 lpc_ad0 lpc_fram e# pata_da2 vss vss tdi rstwarn k l vss vss lpc_ad3 pata_dd3 rsmrst# slpmode vss vss l m vcc15 vcc15 vcc15 vss vss vss vss tdo tms m n reserve d15 reserve d14 vss wake# gpiosus1 gpiosus2 tck trst# n p vcc15 reserve d9 reserve d10 vss vss vss vss vss gpe# p r vss vss vcc33su s gpiosus3 usb_oc0 # usb_oc2 # vss vss r t vcc vss vcc33su s vss vss vss vss usb_dp7 usb_dn7 t u vss vcc33su s vss gpiosus0 usb_oc3 # usb_oc7 # usb_dn6 usb_dp6 u v vcc vss vss vss vss vss vss usb_dp5 usb_dn5 v w vss reserve d13 vccp33us bsus usb_clk4 8 usb_oc6 # usb_oc1 # vss vss w y vcc15us b vss vccp33us bsus vss vss vss vss usb_dn4 usb_dp4 y aa vss reserve d11 vccp33us bsus vcc5refs us usb_oc5 # usb_oc4 # usb_dp3 usb_dn3 aa ab vcc15us b reserve d17 reserve d12 vss vss vss vss usb_dp2 usb_dn2 ab ac vss reserve d16 vccausb pll vssausb bgsus usb_rbia sp usb_rbia sn vss vss ac ad vcc15us b vcclvds vss vss vss vss vss usb_dn1 usb_dp1 ad ae vss vcclvds vccadpll a vccausb bgsus db_refcl kinpssc db_refcl kinnssc usb_dn0 usb_dp0 ae af vcc vcclvds vcclvds vss vss vss vss la_clkp la_clkn af ag vss vcclvds vccadpll b vss la_datap 3 la_datan 3 vss vss ag ah vcc vccsdvo vccsdvo vss vss vss vss la_datan 2 la_datap 2 ah aj vss vccsdvo vss vss la_datan 0 la_datap 0 vss vss aj ak vcc vccsdvo vccsdvo vss vss vss vss la_datan 1 la_datap 1 ak al vss vccsdvo vss vss da_refcl kinp da_refcl kinn vss vss al am vcc vccpcie vss vss vss vss vss sdvob_ red# sdvob_r ed am an vss vccpcie vss vss sdvob_ stall# sdvob_ stall vss vccapcie pll an ap vccsm vccpcie vccpcie vss vss vss vss sdvob_ tvclkin sdvob_ tvclkin# ap ar vss vccpcie vss vss sdvob_ blue# sdvob_ blue vss vss ar at vccpcie vccpcie vccpcie vss vss vss vss sdvob_g reen# sdvob_g reen at au vss vccpcie vss vss reserve d6 reserve d7 sdvob_i nt sdvob_ int# au av vccsm vccsm vccpcie vss vss vss vss sdvob_c lk sdvob_c lk# av a w vccsm vccsm vss vccapcie bg pcie_per p1 pcie_per n1 vss vss a w ay vss vss vss vss vssapcie bg vss vss pcie_clki nn pcie_clki np ay ba sm_bs2 sm_ma14 sm_rcve nin reset# pcie_per n2 pcie_per p2 pcie_ico mpi pcie_ico mpo ba bb vss vss vss vss vss vss vss pcie_pet n1 pcie_pet p1 bb bc sm_dq23 sm_dqs2 sm_dq16 sm_dq11 sm_dq3 sm_dq6 sm_dq5 vss bc bd vss vss vss vss vss vss vss vss pcie_pet p2 bd be sm_ma11 sm_cke1 sm_cke0 sm_rcve nout sm_vref sm_dq2 sm_dq4 pcie_pet n2 be bf vss vss vss vss vss vss vss vss vss_nctf bf bg sm_dq21 sm_dq18 sm_dq15 sm_dq9 sm_dq12 sm_ck0 sm_dq1 sm_dq0 bg bh vss vss vss vss vss vss vss vss vss_nctf bh bj sm_dq22 sm_dq20 sm_dq14 sm_dqs1 sm_dq13 sm_ck0# sm_dqs0 vss_nctf bj bk sm_dq24 sm_dq19 sm_dq17 sm_dq10 sm_dq8 sm_dq7 vss_nctf vss_nctf reserve d8 (nctf) bk #3435363738394041424344454647484950#
datasheet 439 ballout and package information table 81. intel? sch pin list arranged by signal name pin name ball# bsel2 f28 cfg0 j27 cfg1 b34 clk14 h32 clkreq# b28 da_refclkinn al45 da_refclkinp al43 db_refclkinnssc ae45 db_refclkinpssc ae43 dprslpvr d34 extts d32 gpe# p50 gpio0 g29 gpio1 k30 gpio2 f34 gpio3 g33 gpio4 k36 gpio5 h36 gpio6 f36 gpio7 j31 gpio8 h34 gpio9 k28 gpiosus0 u41 gpiosus1 n43 gpiosus2 n45 gpiosus3 r41 h_a3# m2 h_a4# m8 h_a5# k4 h_a6# p2 h_a7# f4 h_a8# g1 h_a9# m4 h_a10# f6 h_a11# h6 h_a12# d2 h_a13# h2 h_a14# j1 h_a15# f2 h_a16# d4 h_a17# d12 h_a18# h12 h_a19# g11 h_a20# a7 h_a21# a9 h_a22# a11 h_a23# b6 h_a24# h8 h_a25# f10 h_a26# b10 h_a27# d6 h_a28# d10 h_a29# b12 h_a30# b4 h_a31# d8 h_ads# k6 h_adstb0# h4 h_adstb1# b8 h_bnr# r1 h_bpri# p10 h_breq0# l1 h_cgvref ad4 h_clkinn k10 h_clkinp m10 h_cpupwrgd ap6 h_cpurst# m6 h_cpuslp# ah10 h_d0# v8 h_d1# af4 h_d2# v2 h_d3# aa1 h_d4# ac1 table 81. intel? sch pin list arranged by signal name pin name ball# h_d5# ad2 h_d6# v4 h_d7# y2 h_d8# u1 h_d9# y8 h_d10# ab2 h_d11# af2 h_d12# ab4 h_d13# af8 h_d14# ae1 h_d15# ab8 h_d16# aj1 h_d17# ah2 h_d18# am8 h_d19# an1 h_d20# ak4 h_d21# ag1 h_d22# ah8 h_d23# ak8 h_d24# ap8 h_d25# ak2 h_d26# ar1 h_d27# at8 h_d28# at2 h_d29# ah4 h_d30# ap4 h_d31# ap2 h_d32# av4 h_d33# bb6 h_d34# av6 h_d35# ay8 h_d36# ba1 h_d37# au1 h_d38# at6 h_d39# av8 h_d40# bb4 table 81. intel? sch pin list arranged by signal name pin name ball#
440 datasheet ballout and package information h_d41# at4 h_d42# ay6 h_d43# av10 h_d44# av2 h_d45# bc1 h_d46# bb2 h_d47# ay2 h_d48# bd2 h_d49# bh4 h_d50# bd10 h_d51# bk10 h_d52# bd6 h_d53# bd4 h_d54# bf2 h_d55# be1 h_d56# bd8 h_d57# bf4 h_d58# bh10 h_d59# bk6 h_d60# bb8 h_d61# bf6 h_d62# bf10 h_d63# bh6 h_dbsy# h10 h_defer# ad6 h_dinv0# ad8 h_dinv1# am2 h_dinv2# ay10 h_dinv3# bk8 h_dprstp# ak10 h_dpslp# f8 h_dpwr# p6 h_drdy# j9 h_dstbn0# y4 h_dstbn1# al1 h_dstbn2# aw1 table 81. intel? sch pin list arranged by signal name pin name ball# h_dstbn3# bh8 h_dstbp0# w1 h_dstbp1# am4 h_dstbp2# ay4 h_dstbp3# bf8 h_gvref y10 h_hit# v10 h_hitm# t6 h_init# af10 h_intr af6 h_lock# y6 h_nmi ab10 h_pbe# ah6 h_rcompo t10 h_req0# p4 h_req1# n1 h_req2# k8 h_req3# p8 h_req4# k2 h_rs0# t4 h_rs1# t2 h_rs2# t8 h_smi# ab6 h_stpclk# ad10 h_swing v6 h_testin# ak6 h_thrmtrip# am6 h_trdy# f12 hda_clk k14 hda_docken# e15 hda_dockrst# h14 hda_rst# a13 hda_sdi0 f14 hda_sdi1 b14 hda_sdo d14 hda_sync e13 table 81. intel? sch pin list arranged by signal name pin name ball# intvrmen f46 l_bkltctl a33 l_bklten a31 l_ctla_clk d28 l_ctlb_data k26 l_ddcclk a27 l_ddcdata h28 l_vdden d30 la_clkn af50 la_clkp af48 la_datan0 aj43 la_datan1 ak48 la_datan2 ah48 la_datan3 ag45 la_datap0 aj45 la_datap1 ak50 la_datap2 ah50 la_datap3 ag43 lpc_ad0 k38 lpc_ad1 j39 lpc_ad2 a35 lpc_ad3 l39 lpc_clkout0 f38 lpc_clkout1 b36 lpc_clkout2 d38 lpc_clkrun# d36 lpc_frame# k40 lpc_serirq b38 pata_da0 h40 pata_da1 j45 pata_da2 k42 pata_dcs1# e47 pata_dcs3# c47 pata_dd0 d40 pata_dd1 g43 pata_dd2 b44 table 81. intel? sch pin list arranged by signal name pin name ball#
datasheet 441 ballout and package information pata_dd3 l41 pata_dd4 d44 pata_dd5 f42 pata_dd6 b42 pata_dd7 a39 pata_dd8 j41 pata_dd9 a41 pata_dd10 a43 pata_dd11 f40 pata_dd12 d42 pata_dd13 h42 pata_dd14 e43 pata_dd15 b40 pata_ddack# b46 pata_ddreq j43 pata_dior# f44 pata_diow# a37 pata_ideirq g45 pata_iordy d46 pcie_clkinn ay48 pcie_clkinp ay50 pcie_icompi ba47 pcie_icompo ba49 pcie_pern1 aw45 pcie_pern2 ba43 pcie_perp1 aw43 pcie_perp2 ba45 pcie_petn1 bb48 pcie_petn2 be49 pcie_petp1 bb50 pcie_petp2 bd50 pwrok c49 reserved0 e49 reserved1 b32 reserved10 p38 reserved11 aa37 table 81. intel? sch pin list arranged by signal name pin name ball# reserved12 ab38 reserved13 w37 reserved14 n37 reserved15 n35 reserved16 ac37 reserved17 ab36 reserved18 g21 reserved2 be15 reserved3 ba21 reserved4 ap10 reserved5 at10 reserved6 au43 reserved7 au45 reserved9 p36 reset# ba41 rsmrst# l43 rstrdy# h50 rstwarn k50 rtc_x1 f48 rtc_x2 f50 rtcrst# h48 sd0_cd# b18 sd0_clk d18 sd0_cmd j15 sd0_data0 h16 sd0_data1 a17 sd0_data2 k18 sd0_data3 f16 reserved20 k16 reserved19 b16 xor_test d16 reserved21 k20 sd0_led h18 sd0_pwr# h20 sd0_wp f18 sd1_cd# b22 table 81. intel? sch pin list arranged by signal name pin name ball# sd1_clk h22 sd1_cmd f20 sd1_data0 f22 sd1_data1 j19 sd1_data2 k22 sd1_data3 d22 sd1_led a21 sd1_pwr# d20 sd1_wp b20 sd2_cd# k24 sd2_clk d26 sd2_cmd b24 sd2_data0 j23 sd2_data1 a25 sd2_data2 f26 sd2_data3 a23 sd2_data4 f24 sd2_data5 h24 sd2_data6 h26 sd2_data7 e25 sd2_led d24 sd2_pwr# a19 sd2_wp b26 sdvo_ctrlclk f30 sdvo_ctrldata a29 sdvob_blue ar45 sdvob_blue# ar43 sdvob_clk av48 sdvob_clk# av50 sdvob_green at50 sdvob_green# at48 sdvob_int au47 sdvob_int# au49 sdvob_red am50 sdvob_red# am48 sdvob_stall an45 table 81. intel? sch pin list arranged by signal name pin name ball#
442 datasheet ballout and package information sdvob_stall# an43 sdvob_tvclkin ap48 sdvob_tvclkin# ap50 slpmode l45 slprdy# j49 sm_bs0 bc27 sm_bs1 be25 sm_bs2 ba35 sm_cas# ba13 sm_ck0 bg45 sm_ck0# bj45 sm_ck1 be11 sm_ck1# bg11 sm_cke0 be39 sm_cke1 be37 sm_cs0# ba23 sm_cs1# ba15 sm_dq0 bg49 sm_dq1 bg47 sm_dq2 be45 sm_dq3 bc43 sm_dq4 be47 sm_dq5 bc47 sm_dq6 bc45 sm_dq7 bk44 sm_dq8 bk42 sm_dq9 bg41 sm_dq10 bk40 sm_dq11 bc41 sm_dq12 bg43 sm_dq13 bj43 sm_dq14 bj39 sm_dq15 bg39 sm_dq16 bc39 sm_dq17 bk38 sm_dq18 bg37 table 81. intel? sch pin list arranged by signal name pin name ball# sm_dq19 bk36 sm_dq20 bj37 sm_dq21 bg35 sm_dq22 bj35 sm_dq23 bc35 sm_dq24 bk34 sm_dq25 bg31 sm_dq26 bg33 sm_dq27 bk30 sm_dq28 bc33 sm_dq29 bj33 sm_dq30 bj31 sm_dq31 bc31 sm_dq32 bj29 sm_dq33 bg29 sm_dq34 bk28 sm_dq35 bc29 sm_dq36 be27 sm_dq37 bk26 sm_dq38 bg25 sm_dq39 bj25 sm_dq40 bc25 sm_dq41 bg23 sm_dq42 bk22 sm_dq43 bj21 sm_dq44 bk24 sm_dq45 bj23 sm_dq46 bg21 sm_dq47 bc21 sm_dq48 bk20 sm_dq49 bj19 sm_dq50 bg17 sm_dq51 bj17 sm_dq52 bg19 sm_dq53 bc19 sm_dq54 bc17 table 81. intel? sch pin list arranged by signal name pin name ball# sm_dq55 bk16 sm_dq56 bg15 sm_dq57 bc15 sm_dq58 bj13 sm_dq59 bk12 sm_dq60 bk14 sm_dq61 bj15 sm_dq62 bc13 sm_dq63 bc11 sm_dqs0 bj47 sm_dqs1 bj41 sm_dqs2 bc37 sm_dqs3 bk32 sm_dqs4 bg27 sm_dqs5 be23 sm_dqs6 bk18 sm_dqs7 bg13 sm_ma0 bj27 sm_ma1 ba19 sm_ma2 ba27 sm_ma3 ba25 sm_ma4 be29 sm_ma5 bc23 sm_ma6 be31 sm_ma7 ba31 sm_ma8 ba33 sm_ma9 ba29 sm_ma10 be17 sm_ma11 be35 sm_ma12 be33 sm_ma13 be19 sm_ma14 ba37 sm_ras# be21 sm_rcompo be13 sm_rcvenin# ba39 sm_rcvenout# be41 table 81. intel? sch pin list arranged by signal name pin name ball#
datasheet 443 ballout and package information sm_vref be43 sm_we# ba17 smb_alert# k32 smb_clk h38 smb_data g37 smi# b30 spkr j35 stpcpu# h30 susclk j47 tck n47 tdi k48 tdo m48 thrm# f32 tms m50 trst# n49 usb_clk48 w41 usb_dn0 ae47 usb_dn1 ad48 usb_dn2 ab50 usb_dn3 aa49 usb_dn4 y48 usb_dn5 v50 usb_dn6 u47 usb_dn7 t50 usb_dp0 ae49 usb_dp1 ad50 usb_dp2 ab48 usb_dp3 aa47 usb_dp4 y50 usb_dp5 v48 usb_dp6 u49 usb_dp7 t48 usb_oc0# r43 usb_oc1# w45 usb_oc2# r45 usb_oc3# u43 table 81. intel? sch pin list arranged by signal name pin name ball# usb_oc4# aa45 usb_oc5# aa43 usb_oc6# w43 usb_oc7# u45 usb_rbiasn ac45 usb_rbiasp ac43 vcc ab16 vcc ad16 vcc af16 vcc ah16 vcc ak16 vcc am16 vcc t16 vcc v16 vcc y16 vcc ab18 vcc ad18 vcc af18 vcc ah18 vcc ak18 vcc am18 vcc t18 vcc v18 vcc y18 vcc ab20 vcc ad20 vcc af20 vcc ah20 vcc ak20 vcc am20 vcc t20 vcc v20 vcc y20 vcc ab22 vcc ad22 vcc af22 table 81. intel? sch pin list arranged by signal name pin name ball# vcc ah22 vcc ak22 vcc am22 vcc t22 vcc v22 vcc y22 vcc ab24 vcc ad24 vcc af24 vcc ah24 vcc ak24 vcc am24 vcc t24 vcc v24 vcc y24 vcc ab26 vcc ad26 vcc af26 vcc ah26 vcc ak26 vcc am26 vcc t26 vcc v26 vcc y26 vcc ab28 vcc ad28 vcc af28 vcc ah28 vcc ak28 vcc am28 vcc t28 vcc v28 vcc y28 vcc ab30 vcc ad30 vcc af30 table 81. intel? sch pin list arranged by signal name pin name ball#
444 datasheet ballout and package information vcc ah30 vcc ak30 vcc am30 vcc t30 vcc v30 vcc y30 vcc af32 vcc ah32 vcc ak32 vcc am32 vcc t32 vcc v32 vcc af34 vcc ah34 vcc ak34 vcc am34 vcc t34 vcc v34 vcc15 r15 vcc15 r17 vcc15 r19 vcc15 r21 vcc15 r23 vcc15 r25 vcc15 r27 vcc15 r29 vcc15 n31 vcc15 r31 vcc15 m32 vcc15 p32 vcc15 n33 vcc15 r33 vcc15 m34 vcc15 p34 vcc15 m36 vcc15 m38 table 81. intel? sch pin list arranged by signal name pin name ball# vcc15usb ab32 vcc15usb ad32 vcc15usb y32 vcc15usb ab34 vcc15usb ad34 vcc15usb y34 vcc33 n15 vcc33 m16 vcc33 n17 vcc33 m18 vcc33 n19 vcc33 m20 vcc33 n21 vcc33 m22 vcc33 n23 vcc33 m24 vcc33 n25 vcc33 m26 vcc33 n27 vcc33 m28 vcc33 n29 vcc33 m30 vcc33rtc a45 vcc33sus u37 vcc33sus t38 vcc33sus r39 vcc5ref k34 vcc5refsus aa41 vccadplla ae39 vccadpllb ag39 vccahpll ba11 vccapciebg aw41 vccapciepll an49 vccausbbgsus ae41 vccausbpll ac39 vccdhpll bb10 table 81. intel? sch pin list arranged by signal name pin name ball# vcchda j11 vcchda k12 vcclvds ad36 vcclvds af36 vcclvds ae37 vcclvds ag37 vcclvds af38 vccp33usbsus y38 vccp33usbsus aa39 vccp33usbsus w39 vccpcie at32 vccpcie at34 vccpcie am36 vccpcie ap36 vccpcie at36 vccpcie an37 vccpcie ar37 vccpcie au37 vccpcie ap38 vccpcie at38 vccpcie av38 vccsdvo ah36 vccsdvo ak36 vccsdvo aj37 vccsdvo al37 vccsdvo ah38 vccsdvo ak38 vccsm ap16 vccsm at16 vccsm av16 vccsm aw17 vccsm ap18 vccsm at18 vccsm av18 vccsm aw19 vccsm ap20 table 81. intel? sch pin list arranged by signal name pin name ball#
datasheet 445 ballout and package information vccsm at20 vccsm av20 vccsm aw21 vccsm ap22 vccsm at22 vccsm av22 vccsm aw23 vccsm ap24 vccsm at24 vccsm av24 vccsm aw25 vccsm ap26 vccsm at26 vccsm av26 vccsm aw27 vccsm ap28 vccsm at28 vccsm av28 vccsm aw29 vccsm ap30 vccsm at30 vccsm av30 vccsm aw31 vccsm ap32 vccsm av32 vccsm aw33 vccsm ap34 vccsm av34 vccsm aw35 vccsm av36 vccsm aw37 vss aa3 vss ac3 vss ae3 vss ag3 vss aj3 table 81. intel? sch pin list arranged by signal name pin name ball# vss al3 vss an3 vss ar3 vss au3 vss aw3 vss ba3 vss bc3 vss be3 vss bg3 vss c3 vss e3 vss g3 vss j3 vss l3 vss n3 vss r3 vss u3 vss w3 vss aa5 vss ac5 vss ae5 vss ag5 vss aj5 vss al5 vss an5 vss ar5 vss au5 vss aw5 vss ba5 vss bc5 vss be5 vss bg5 vss bj5 vss c5 vss e5 vss g5 table 81. intel? sch pin list arranged by signal name pin name ball# vss j5 vss l5 vss n5 vss r5 vss u5 vss w5 vss aa7 vss ac7 vss ae7 vss ag7 vss aj7 vss al7 vss an7 vss ar7 vss au7 vss aw7 vss ba7 vss bc7 vss be7 vss bg7 vss bj7 vss c7 vss e7 vss g7 vss j7 vss l7 vss n7 vss r7 vss u7 vss w7 vss aa9 vss ac9 vss ae9 vss ag9 vss aj9 vss al9 table 81. intel? sch pin list arranged by signal name pin name ball#
446 datasheet ballout and package information vss an9 vss ar9 vss au9 vss aw9 vss ba9 vss bc9 vss be9 vss bg9 vss bj9 vss c9 vss e9 vss g9 vss l9 vss n9 vss r9 vss u9 vss w9 vss am10 vss aa11 vss ac11 vss ae11 vss ag11 vss aj11 vss al11 vss an11 vss ar11 vss au11 vss aw11 vss bj11 vss c11 vss e11 vss l11 vss n11 vss r11 vss u11 vss w11 table 81. intel? sch pin list arranged by signal name pin name ball# vss ay12 vss bb12 vss bd12 vss bf12 vss bh12 vss c13 vss g13 vss j13 vss l13 vss ab14 vss ad14 vss af14 vss ah14 vss ak14 vss am14 vss ap14 vss at14 vss av14 vss ay14 vss bb14 vss bd14 vss bf14 vss bh14 vss p14 vss t14 vss v14 vss y14 vss a15 vss aa15 vss ac15 vss ae15 vss ag15 vss aj15 vss al15 vss an15 vss ar15 table 81. intel? sch pin list arranged by signal name pin name ball# vss au15 vss aw15 vss c15 vss g15 vss l15 vss u15 vss w15 vss ay16 vss bb16 vss bd16 vss bf16 vss bh16 vss p16 vss aa17 vss ac17 vss ae17 vss ag17 vss aj17 vss al17 vss an17 vss ar17 vss au17 vss c17 vss e17 vss g17 vss j17 vss l17 vss u17 vss w17 vss ay18 vss bb18 vss bd18 vss bf18 vss bh18 vss p18 vss aa19 table 81. intel? sch pin list arranged by signal name pin name ball#
datasheet 447 ballout and package information vss ac19 vss ae19 vss ag19 vss aj19 vss al19 vss an19 vss ar19 vss au19 vss c19 vss e19 vss g19 vss l19 vss u19 vss w19 vss ay20 vss bb20 vss bd20 vss bf20 vss bh20 vss p20 vss aa21 vss ac21 vss ae21 vss ag21 vss aj21 vss al21 vss an21 vss ar21 vss au21 vss c21 vss e21 vss j21 vss l21 vss u21 vss w21 vss ay22 table 81. intel? sch pin list arranged by signal name pin name ball# vss bb22 vss bd22 vss bf22 vss bh22 vss p22 vss aa23 vss ac23 vss ae23 vss ag23 vss aj23 vss al23 vss an23 vss ar23 vss au23 vss c23 vss e23 vss g23 vss l23 vss u23 vss w23 vss ay24 vss bb24 vss bd24 vss bf24 vss bh24 vss p24 vss aa25 vss ac25 vss ae25 vss ag25 vss aj25 vss al25 vss an25 vss ar25 vss au25 vss c25 table 81. intel? sch pin list arranged by signal name pin name ball# vss g25 vss j25 vss l25 vss u25 vss w25 vss ay26 vss bb26 vss bd26 vss bf26 vss bh26 vss p26 vss aa27 vss ac27 vss ae27 vss ag27 vss aj27 vss al27 vss an27 vss ar27 vss au27 vss c27 vss e27 vss g27 vss l27 vss u27 vss w27 vss ay28 vss bb28 vss bd28 vss bf28 vss bh28 vss p28 vss aa29 vss ac29 vss ae29 vss ag29 table 81. intel? sch pin list arranged by signal name pin name ball#
448 datasheet ballout and package information vss aj29 vss al29 vss an29 vss ar29 vss au29 vss c29 vss e29 vss j29 vss l29 vss u29 vss w29 vss ay30 vss bb30 vss bd30 vss bf30 vss bh30 vss p30 vss aa31 vss ac31 vss ae31 vss ag31 vss aj31 vss al31 vss an31 vss ar31 vss au31 vss c31 vss e31 vss g31 vss l31 vss u31 vss w31 vss ay32 vss bb32 vss bd32 vss bf32 table 81. intel? sch pin list arranged by signal name pin name ball# vss bh32 vss aa33 vss ac33 vss ae33 vss ag33 vss aj33 vss al33 vss an33 vss ar33 vss au33 vss c33 vss e33 vss j33 vss l33 vss u33 vss w33 vss ay34 vss bb34 vss bd34 vss bf34 vss bh34 vss aa35 vss ac35 vss ae35 vss ag35 vss aj35 vss al35 vss an35 vss ar35 vss au35 vss c35 vss e35 vss g35 vss l35 vss r35 vss u35 table 81. intel? sch pin list arranged by signal name pin name ball# vss w35 vss ay36 vss bb36 vss bd36 vss bf36 vss bh36 vss t36 vss v36 vss y36 vss c37 vss e37 vss j37 vss l37 vss r37 vss ad38 vss am38 vss ay38 vss bb38 vss bd38 vss bf38 vss bh38 vss v38 vss aj39 vss al39 vss an39 vss ar39 vss au39 vss aw39 vss c39 vss e39 vss g39 vss n39 vss u39 vss ab40 vss ad40 vss af40 table 81. intel? sch pin list arranged by signal name pin name ball#
datasheet 449 ballout and package information vss ah40 vss ak40 vss am40 vss ap40 vss at40 vss av40 vss ay40 vss bb40 vss bd40 vss bf40 vss bh40 vss m40 vss p40 vss t40 vss v40 vss y40 vss ag41 vss aj41 vss al41 vss an41 vss ar41 vss au41 vss c41 vss e41 vss g41 vss ab42 vss ad42 vss af42 vss ah42 vss ak42 vss am42 vss ap42 vss at42 vss av42 vss bb42 vss bd42 table 81. intel? sch pin list arranged by signal name pin name ball# vss bf42 vss bh42 vss m42 vss p42 vss t42 vss v42 vss y42 vss c43 vss ab44 vss ad44 vss af44 vss ah44 vss ak44 vss am44 vss ap44 vss at44 vss av44 vss ay44 vss bb44 vss bd44 vss bf44 vss bh44 vss h44 vss k44 vss m44 vss p44 vss t44 vss v44 vss y44 vss c45 vss e45 vss ab46 vss ad46 vss af46 vss ah46 vss ak46 table 81. intel? sch pin list arranged by signal name pin name ball# vss am46 vss ap46 vss at46 vss av46 vss ay46 vss bb46 vss bd46 vss bf46 vss bh46 vss h46 vss k46 vss m46 vss p46 vss t46 vss v46 vss y46 vss ac47 vss ag47 vss aj47 vss al47 vss an47 vss ar47 vss aw47 vss g47 vss l47 vss r47 vss w47 vss bd48 vss bf48 vss bh48 vss d48 vss p48 vss ac49 vss ag49 vss aj49 vss al49 table 81. intel? sch pin list arranged by signal name pin name ball#
450 datasheet ballout and package information vss ar49 vss aw49 vss bc49 vss g49 vss l49 vss r49 vss w49 vss_nctf a3 vss_nctf a5 vss_nctf a47 vss_nctf a49 vss_nctf b2 vss_nctf b48 vss_nctf b50 vss_nctf bf50 vss_nctf bg1 vss_nctf bh2 vss_nctf bh50 vss_nctf bj1 vss_nctf bj3 vss_nctf bj49 vss_nctf bk2 vss_nctf bk4 vss_nctf bk46 vss_nctf bk48 vss_nctf bk50 vss_nctf c1 vss_nctf d50 vss_nctf e1 vssapciebg ay42 vssausbbgsus ac41 vtt ab12 vtt ad12 vtt af12 vtt ah12 vtt ak12 table 81. intel? sch pin list arranged by signal name pin name ball# vtt am12 vtt ap12 vtt at12 vtt av12 vtt m12 vtt p12 vtt t12 vtt v12 vtt y12 vtt aa13 vtt ac13 vtt ae13 vtt ag13 vtt aj13 vtt al13 vtt an13 vtt ar13 vtt au13 vtt aw13 vtt n13 vtt r13 vtt u13 vtt w13 vtt m14 wake# n41 table 81. intel? sch pin list arranged by signal name pin name ball#


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